JP3244623B2 - Low EMI package circuit and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to IC, LS
EM, which is becoming increasingly important as the speed and density of I-elements and circuits increase,
More particularly, the present invention relates to a low EMI package circuit and device provided with a means for suppressing potential fluctuation and unnecessary radiation noise.

[0002]

2. Description of the Related Art In an LSI device or the like, in order to suppress unnecessary radiation, a good frequency characteristic between a power supply terminal (pad) and a ground terminal (pad) of an LSI device or the like, which is a source of noise, is usually used. A bypass capacitor is inserted. However, if such a bypass capacitor is connected to the outside of the LSI device, there is a large current loop from the semiconductor chip to the package lead even if the capacitance of the bypass capacitor is sufficiently large. is there.

Therefore, it is known to adopt a method of reducing the length (area) of a current loop by incorporating a bypass capacitor in an LSI device as described in JP-A-5-267557.

[0004]

However, the resonance current flowing in the current loop causes a potential change between the power supply pad and the ground pad, so that the radiation from the wiring connected to the pad cannot be removed. For this reason, means for suppressing and absorbing such potential fluctuations is required.

The present invention has been made in view of this point, and an object of the present invention is to eliminate the potential change (AC component) of a power supply pad with respect to a ground pad during switching of a semiconductor element or the like without using an EMI measure component. It is an object of the present invention to provide a low EMI package circuit and device that convert the energy into Joule heat, realize high-density mounting, and can effectively suppress unnecessary radiation.

[0006]

In order to achieve the above object, the present invention relates to a method of connecting a resistor to a bypass capacitor formed on a package substrate on which a semiconductor element (LSI device) is mounted. By lowering the Q value of the capacitor, potential fluctuations generated between the power supply pad and the ground pad of the semiconductor element are converted by heat and absorbed, thereby suppressing unnecessary radiation.

On the surface of the package substrate, a series circuit of a second bypass capacitor and a resistor is connected in parallel to a first bypass capacitor connected between a power supply pad and a ground pad of a semiconductor device. As a result, the Q value of the circuit viewed from between the power supply pad and the ground pad can be cut at the same time as the DC component, and the Q value of the AC component can be reduced (a value of 10 or less).

The series circuit of the second bypass capacitor and the resistor is connected to a required frequency region (ω ₁ ≦ ω ≦
ω2), the impedance | Zc ₂ | of the second bypass capacitor (= 1 / ωC ₂ : where C ₂ is the capacitance of the second bypass capacitor) is sufficiently compared with the resistance value R of the resistor. By making the difference smaller (by a difference of about one digit or more), a resistor having a value R is equivalently connected in parallel to the first bypass capacitor. At this time, the Q of the circuit viewed from between the power supply pad and the ground pad of the semiconductor element.
The values are the Q value (= ωC ₁ R: where C ₁ is the capacitance of the first bypass capacitor, and R is the resistance value of the resistor) of an equivalent circuit in which a resistor is connected in parallel to the first bypass capacitor. Become.

As a result, the DC bias component is cut off in a circuit, and at the same time, the Q of the AC component (harmonic component) is reduced. That is, by setting the Q value of the circuit to 10 or less, potential fluctuation (AC component) generated between the power supply pad and the ground pad of the semiconductor element can be converted into heat and effectively absorbed.

On the other hand, when only the first bypass capacitor made of a material having a large tan (δ) is used as the dielectric, or when the bypass capacitor and the resistor are directly connected in parallel in a circuit, the Q is reduced. Although a problem such as a leak current with respect to the application of the DC bias voltage occurs, the present invention solves this problem by the second bypass capacitor.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of a low EMI package circuit and device according to the present invention, wherein 1 is a semiconductor element (here, an LSI chip), and 2 is a low EM package.
I package substrate, 3 is a ground terminal electrode, 4 is a power terminal electrode, 5 and 6 are conductor films, 7 is a resistor film, 8 is a dielectric film, 9 is a conductor film, 10 is a dielectric film, and 11 is a conductor film. , 12
Is an insulating film, 13 is a power supply pad, 14 is a ground pad,
Reference numeral 15 denotes a solder pump, and 16 denotes a connection terminal.

In FIG. 1, this embodiment has a low EMI
The configuration is such that the LSI chip 1 is mounted on the package substrate 2.

The LSI chip 1 has a ground terminal electrode 3 and a power terminal electrode 4 for connection to an external circuit (not shown).
It has terminal electrodes such as signal terminal electrodes (not shown).

In the low EMI package substrate 2, L
For example, a rectangular conductor film 5 and a frame-like conductor film 6 surrounding the conductor film 5 are provided on the surface on which the SI chip 1 is mounted, and a resistor film 7 is provided between the conductor films 5 and 6. ing. A predetermined number of terminal portions 6a protrude from the frame-shaped conductor film 6, and portions of the conductor film 6 excluding the terminal portions 6a, the conductor film 5, and the resistor film 7 are covered with the dielectric film 8. I have. A conductor film 9 facing the conductor film 5 is provided on the dielectric film 8, and a predetermined number of terminal portions 9 a protruding from the conductor film 9 are provided on the low EMI package substrate 2.

With the above structure, the opposing portions of the conductor films 5 and 9 sandwiching the dielectric film 8 form a second bypass capacitor, and the resistor film 7 between the capacitor and the conductor films 5 and 6 forms the second bypass capacitor. The resistance corresponds to the terminal portion 9a of the conductor film 9 and the terminal portion 6a of the conductor film 6.
Are connected in series.

The conductor film 9 is covered with a dielectric film 10 except for the terminal portion 9a, and the conductor film 9 is formed on the dielectric film 10 so as to face a part of the conductor film 9 so as to face the conductor film 9. A membrane 11 is provided. A predetermined number of ends of the conductor film 11 are connected to respective terminal portions 6a of the conductor film 6.
The insulating film 12 is provided so as to cover the respective films.

With the above configuration, the opposing portions of the conductor films 9 and 11 sandwiching the dielectric film 10 form a first bypass capacitor, which is composed of the terminal portion 9a of the conductor film 9 and the conductor film 6.
, And connected in parallel to the series circuit of the second bypass capacitor and the resistor.

A power supply pad 13 is provided on the surface of the terminal portion 9a of the conductor film 9, and a ground pad 14 is provided on the surface of the terminal portion 6a of the conductor film 6, and a signal pad (not shown). ) Is also formed. The power supply pad 13, the ground pad 14, and the signal pad are not covered with the insulating film 12 and are exposed to the outside. The power supply terminal electrode 4, the ground terminal electrode 3, and the signal terminal electrode provided on the LSI chip 1, respectively. (Not shown) and a solder bump 15.

Therefore, according to the above configuration, as shown in FIG. 2, between the power supply pad 13 and the ground pad 14, the second bypass capacitor 18 and the resistor 19 are connected in parallel with the first bypass capacitor 17. Is connected to the series circuit.

The conductor films 5 and 6 are used as the resistor film 7.
The space may be provided in a continuous frame shape, or a plurality of discontinuous rectangular shapes (separated from four sides) arranged between the conductor films 5 and 6 may be used.

A plurality of connection terminals 16-1,..., 16-5 are arranged in a plane on the surface of the low EMI package substrate 2 opposite to the surface on which the LSI chip 1 is mounted.
The power supply pad 13, the ground pad 14, and the signal pad are electrically connected to these. Because of this, low EMI
The package substrate 2 has no structure of a multilayer wiring substrate in which a through-hole or a conductive film is provided inside, so that the pitch of these connection terminals 16-1 to 16-5 is enlarged.

When the LSI chip 1 has electrodes arranged in a matrix, the low EMI package substrate 2
The terminal electrodes are arranged by providing through holes in the portions where the first bypass capacitor 17 and the second bypass capacitor 18 are formed.
Form. When such terminal electrodes are a power supply electrode and a ground electrode, they can be directly connected to the first bypass capacitor 17 without using connection leads, so that the inductance component can be reduced and the frequency characteristics of the first bypass capacitor 17 can be reduced. Significantly improved.

Here, in the series circuit of the second bypass capacitor 18 and the resistor 19 shown in FIG. 2, for the required frequency range (ω ₁ ≦ ω ≦ ω ₂ ), Impedance | Zc ₂ | (= 1 / ω
C ₂ : where C ₂ is the capacitance of the second bypass capacitor) is sufficiently smaller than the resistance value R of the resistor 19 (about 1).
By taking a difference of an order of magnitude or more), the circuit shown in FIG.
Is equivalent to a circuit in which only the resistor 19 having the resistance value R is connected in parallel.

According to this, the Q value of this circuit viewed from between the power supply pad 13 and the ground pad 14 of the LSI chip 1 in FIG. 1 is a diagram in which only the resistor 19 is connected to the first bypass capacitor 17 in parallel. The Q value in the equivalent circuit shown in FIG.

Here, the Q value is given by the ratio between the energy E _C stored in the first bypass capacitor 17 and the energy E _R consumed by the resistor 19. In FIG. C ₁ to capacitance and the resistance of the resistor 19 R, the voltage applied to by V, because it is ^{_{E C = ωC 1 V 2/}} 2 E R = V 2 / 2R, Q value Q = E _C / E _R = ωC ₁ R

With the above configuration, the DC bias component is cut off in circuit by the first bypass capacitor 17 and the second bypass capacitor 18, and the DC bias component is cut off by the resistor 1.
By making the resistance value R of No. 9 sufficiently small, the Q of the AC component (harmonic component) is reduced. This resistance 1
That the resistance value R of No. 9 is sufficiently small to reduce the Q value means that
Based on the above, the energy consumed by the resistor 19 E _R
According to this, the AC component is efficiently converted into heat and absorbed by the resistor 19.
According to experiments, by setting this Q value to 10 or less,
Power supply pad 13 and ground pad 14 of LSI chip 1
It was found that the potential fluctuation (alternating current component) generated during the heat conversion can be effectively converted and absorbed.

The second bypass capacitor 18 cuts the resistance 19 in a DC manner.
The power consumption of the DC bias at the resistor 19 is prevented. The second bypass capacitor 18
As described above, the reactance of the second bypass capacitor 18 is made sufficiently smaller than the resistance value R of the resistor 19 in order to prevent the influence on the lowering of Q due to the circuit shown in FIG. It is to be formed.

FIGS. 4 (a) to 10 (a) are exploded plan views showing the structure of a second embodiment of a low EMI package circuit and device according to the present invention, and FIGS. 4 (b) to 10 (b). ) Are cross-sectional views taken along the line AA ′ in FIGS. 4A to 10A, respectively.
1 is a ceramic substrate, 22 is a semiconductor element (here, L
23-1 to 23-4 are power pads; 24-1 to 24-8 are ground pads;
25-2, 25-3 to 25-4 are signal pads, 27, 2
8 is a conductor film, 29-1 to 29-8 are lead patterns, 3
0 is a resistor film, 31 is a dielectric film, 32 is a conductor film, and 33-
1-34-3 are lead patterns, 34 is a dielectric film, 35
Is a conductor film, 36-1 to 36-8 are lead patterns, 37
Is an insulating film.

As shown in FIG. 10B, in the second embodiment, as in the first embodiment shown in FIG. 1, the LSI chip 22 is mounted on the low EMI package substrate 20.
The low EMI package substrate 20 is formed by laminating plate-shaped films on a ceramic substrate 21 as shown in FIGS. 4 to 10.

4 and 5, the ceramic substrate 21 of the low EMI package substrate 20 has a multilayer wiring structure.
Here, it is assumed that it has a substantially square shape.

On the upper surface of the low EMI package substrate 20,
A substantially square conductor film 27 and a square frame-shaped conductor film 28 around the conductor film 27 are provided apart from each other. Lead patterns 29-1 to 29-8 protrude from the four sides and four corners of the conductor film 28 so as to reach the respective sides and corners of the ceramic substrate 21. Ground pads 24-1 to 24-4 are provided.

Here, these lead patterns 29-1 to 29-1
Reference numerals 29-8 are symmetrical with respect to the virtual center point O of the conductor film 28. That is, the lead pattern 29
-1 and the lead pattern 29-3 have a point-symmetric positional relationship with respect to the center point O, and similarly, the lead pattern 29-2 and the lead pattern 29-4, and the lead pattern 29-5 and the lead pattern 29 -7, the lead pattern 29-6 and the lead pattern 29-8 are symmetrical with respect to the center point O.

Next, as shown in FIGS. 5A and 5B,
A resistor film 30 is provided between the conductor films 27 and 28 and over the sides thereof. Thus, the conductor films 27 and 28 form a counter electrode of the resistance of the resistor film 30. This resistance is the resistance 1 in FIGS.
Equivalent to 9. Although the resistor film 30 in this case has a continuous rectangular frame shape, a rectangular resistor film is provided along the plurality of resistor films 30 as in the first embodiment. You may. In this case, these rectangular resistor films have the same thickness and size and are arranged in a point-symmetrical positional relationship with respect to the center point O.

Next, as shown in FIGS. 6A and 6B, the conductor films 27 and 28 and the resistor film 30 are covered with a dielectric film 31, and FIGS. ), A substantially square conductor film 32 is formed on the dielectric film 31.
Is provided. Here, the conductor film 32 is a conductor film 2
7 and the entire surface of the conductive film 32 is
And a dielectric film 31 interposed therebetween. As a result, the dielectric film 31 and the conductor films 27 sandwiching the dielectric film 31,
The opposing portion of 32 constitutes a capacitor. This capacitor is connected in series with the resistor by the resistor film 30, and corresponds to the second bypass capacitor 18 in FIG.

From each of the four sides of the conductor film 32, a low E
The lead patterns 33-1 to 33-4 protrude so as to reach the respective sides of the MI package substrate 20, and power supply pads 23-1 to 23-4 are provided on the front ends thereof. Also in this case, the lead pattern 33-1 and the lead pattern 33-3 have a point symmetrical positional relationship with respect to the center point O, and the lead pattern 33-2 and the lead pattern 23-4 have a point symmetrical relationship with each other with respect to the center point O. It has to be in a proper positional relationship.

As shown in FIGS. 8A and 8B, a dielectric film 34 is further provided on the conductor film 32 so as to cover the dielectric film 31, and FIG. a), (b)
As shown in FIG. 7, a substantially square conductor film 35 is provided on the dielectric film 34. Here, this conductor film 35
Is substantially the same size as the conductor film 32, and is opposed to the conductor film 32 via the dielectric film. Therefore,
The dielectric film 34 and the opposing portions of the conductor films 35 and 32 sandwiching the dielectric film 34 constitute a capacitor.

From the four sides and four corners of the conductor film 35, the lead patterns 36-1 to 36-8 protrude toward the respective sides and corners of the low EMI package substrate 20. Are connected to the respective lead patterns 29-1 to 29-8 protruding from the four sides and the four corners of the outer edge of the frame-shaped conductor film 28.

With such a configuration, the capacitor including the dielectric film 34 and the opposing portions of the conductor films 35 and 32 sandwiching the dielectric film 34 has the above-described resistance by the resistor film 30 and the dielectric film 31
And the conductor films 27 and 32 are connected in parallel with the series connection circuit of the bypass capacitor, and thus correspond to the first bypass capacitor 17 in FIG.

As shown in FIGS. 10A and 10B, the insulating film 37 covers the entire laminate as described above,
Except for -1 to 23-4 and 24-1 to 24-8,
I'm wearing it. And especially as shown in FIG.
The LSI chip 22 is mounted on the low EMI package substrate 20, and the power supply terminal electrodes 4 are connected to the power supply pads 23-1 to 23-2.
3-4 and the ground terminal electrode 3 is the ground pad 2
4-1 to 24-8 and signal terminal electrodes (not shown) are electrically connected to the signal pads 25 by the solder bumps 15, respectively.

The low EMI package substrate 20 has a multi-layer substrate structure having a conductive film and through holes therein, and as shown in FIGS. 4B to 10B, the low EMI package substrate A plurality of external connection terminals 26 are provided on the lower surface of the power supply pad 20, and power supply pads 23-1 to 23-4 are provided.
And ground pads 24-5 to 24-8, signal pads 25
Are electrically connected to the external connection terminals 26 provided on the lower surface of the low EMI package substrate 20 via the conductor films and the through holes. As a result, the external connection terminals 26 in which the electrode pitches of the power supply pad, the ground pad, and the signal pad are enlarged are provided.

In the above configuration, as described above, the impedance of the second bypass capacitor composed of the dielectric film 31 and the conductor films 27 and 32 is reduced by the resistance of the resistance composed of the conductor films 27 and 28 and the resistor film 30. By making the value sufficiently smaller than the value, the equivalent circuit shown in FIG. 3 can be obtained in the second embodiment as well. The same effects as those of the first embodiment can be obtained.

Also in this second embodiment, L
The power supply terminal electrode 4 of the SI chip 22 is connected to the power supply pad 23-1.
23-4, the ground terminal electrode 3 is electrically connected to the ground pads 24-1 to 24-8, and the signal terminal electrode (not shown) is electrically connected to the signal pad 25 by the solder bump 15. For this reason, the length at this connection portion is very short, and no inductance occurs at this portion.

FIG. 4A, FIG. 5A and FIG.
As described in (a), the conductor films 27 and 32 constituting the electrodes of the capacitor have a substantially square shape, and the lead patterns 33-32 are symmetrically arranged with respect to the center point O on the planar conductor film 32. L is provided with 1-33-4
The lead patterns 24-1 to 24-8 which are connected to the power supply terminal electrode 4 of the SI chip 22 and are provided point-symmetrically with respect to the central point
Since the conductor film 27 is connected to the ground electrode 3 of the chip 22, the current flows through the conductor films 27, 28, 32 and the resistor film 30 at a substantially uniform density everywhere.
The current can be reduced (as a result, the intensity of the generated magnetic field decreases), and the generation of inductance in the second bypass capacitor can be sufficiently suppressed.

Also, as shown in FIG. 9A, the lead patterns 36-1 to 36-8 are similarly provided in the plane conductor film 35 symmetrically with respect to the center point O thereof. Are connected to the ground electrode 3 of the LSI chip 22, current flows at a substantially uniform density everywhere, and generation of inductance in the first bypass capacitor can be sufficiently suppressed.

As for the capacitor, when the frequency of the current flowing therethrough increases, the impedance of the capacitor changes from capacitive to inductive.
However, if the generation of inductance can be sufficiently suppressed as described above, the frequency at which this impedance changes from capacitive to inductive can be made sufficiently high, and high usage can be achieved. Even within the frequency range, the capacitor can maintain good characteristics as capacitance.

As described above, in the second embodiment, the electric path between each terminal electrode and an element (capacitor or resistor) or between each element is reduced to almost zero to suppress the generation of inductance sufficiently. By connecting a resistor in parallel with the first bypass capacitor and reducing the resistance value of the resistor (reducing the Q value), the AC component can be efficiently absorbed, and the first and second bypass capacitors can be used. The generation of inductance can be suppressed, and their characteristics can be kept good.

Next, a specific example of the manufacturing method according to the second embodiment will be described with reference to FIGS.

First, referring to FIG.
500 nm in thickness over the entire surface of the
Is formed. This is converted to a ground pad 24-by a photo process and a reactive dry etching method.
1 to 24-8 and lead patterns 29 connected thereto
The platinum thin film is removed except for -1 to 29-8 and the portions of the conductor films 27 and 28.

Next, in FIG. 5, these conductor films 27,
A resistor film 30 having a frame-shaped pattern is formed between the resistor film 30 and the resistor film 30. In this case, a cermet resistance material of chromium and silicon oxide is used as a material of the resistor film 30, and a resistance thin film is formed on the entire surface of the ceramic substrate 21 to a thickness of 900 nm by a sputtering method. Then, the resistive film is processed by a photo process and a wet etching method to form the resistive film 30 described above. The shape of the resistor film 30 is not limited to a frame shape, but has a symmetric shape in order to equalize the electrical characteristics of the bypass capacitor viewed from the adjacent ground pad 24 and power supply pad 23.

Next, in FIG. 6, a dielectric film 31 is formed in a rectangular pattern. For this purpose, after the resistor film 30 is formed, a tantalum oxide film having a thickness of 200 nm is formed on the entire surface of the ceramic substrate 21 by using a sputtering method. Then, the resistor film 30, the conductor film 27, and the conductor film 28 are formed by a photo process and a wet etching method.
The dielectric film 31 is formed so as to cover a portion excluding the lead patterns 29-1 to 29-8 in the above.

The thickness of the dielectric film 31 is set in consideration of the withstand voltage and capacitance of the second bypass capacitor 18. In order to improve the withstand voltage, the formation process of 100 nm thickness is repeated twice. As the dielectric material, barium titanate (BaTi) is used in order to increase the relative dielectric constant.
O ₃ ) or strontium titanate (SrTiO ₃ ) may be used. As a process, in consideration of composition control and characteristic reproduction, a spin coating method can be used instead of the sputtering method.

Next, in FIG. 7, a conductor film 32 is formed on the dielectric film 31 in a substantially square pattern. That is,
After forming the dielectric film 31, a 500 nm-thick platinum thin film is formed on the entire surface of the ceramic substrate 21 by a sputtering method. Then, the first bypass capacitor 17 and the second bypass capacitor 17 are formed by a photo process and a dry etching method.
Film 3 as electrode layer with bypass capacitor 18
2 is formed on the dielectric film 31.

In this case, the conductor film 32 is
-1 to 23-4 lead pattern 33-
1 to 33-4. When there are a plurality of types of power supplies, the first bypass capacitor 17 is divided into two or more planes and formed in consideration of the arrangement condition of the power supply pads 23. Then, the conductor film 27 is used as a common ground electrode, and the conductor film 32 forms a plurality of power supply electrodes.

Next, in FIG. 8, a dielectric film 34 is formed in a rectangular pattern. That is, after the conductor film 32 is formed, the entire surface of the ceramic substrate 21 is formed by sputtering.
A tantalum oxide thin film having a thickness of 200 nm is formed. As this film forming step, a 50 nm thick film forming step may be repeated four times. Then, the power supply pads 23-1 to 23-4, the ground pads 24-1 to 24-8, and the lead pattern 29 are formed by a photo process and a wet etching method.
Partial upper surfaces of -1 to 29-8 and 33-1 to 33-4 are removed.

As a dielectric material of the dielectric films 31 and 34, barium titanate (Ba) is used in order to increase the relative dielectric constant.
TiO ₃ ) or strontium titanate (SrTiO ₃ ) may be used.

Next, in FIG. 9, a conductor film 35 is formed on the dielectric film 34 in a substantially square pattern. That is,
After the formation of the dielectric film 34, a 500 nm-thick platinum thin film is formed on the entire surface of the ceramic substrate 21 by sputtering. Then, a conductor film 35 as an electrode layer of the first bypass capacitor 17 is formed on the dielectric film 34 by a photo process and a dry etching method. In this case, the conductor film 35 is formed of the ground pads 24-1 to 24-8.
And lead patterns 36-1 to 36-8 for connection with the lead patterns 36-1 to 36-8.
Are the lead patterns 29-1 to 29-1 provided on the conductor film 28.
29-8 and the ground pads 24-1 to 24-8 are electrically connected.

In FIG. 10, after the formation of the conductor film 35, an insulating film 37 as a passivation film is formed next. That is, CVD is applied to the entire surface of the ceramic substrate 21.
By a method, a silicon oxide film having a thickness of 1 μm is formed. This silicon oxide film is formed on the ground pad 24 of the ceramic substrate 21 by a photo process and a dry etching method.
The portions of the electrode pad formation portion such as -1 to 24-8 are removed so that these electrode pads are exposed. Incidentally, in order to improve the moisture resistance, the passivation film may have two layers.

When the insulating film 37 is formed, finally, the portions of the lead patterns 29-1 to 29-8 of the conductor film 28 above the portion excluding the insulating film 37 and the lead patterns 33-1 to 3-1 of the conductor film 32 are formed. The solder is dipped on the portion excluding the insulating film 37 at the tip of 33-4, and the ground pad 24 is
-1 to 24-8 and electrode pads 23-1 to 23-4 are formed.

FIG. 11 is a sectional view showing a third embodiment of the low EMI package circuit and structure according to the present invention.
8 is a metal case, 39 is a module structure, 40 is LS
An I chip, 41 is a pitch expansion electrode, 42 is an external connection terminal, 43 is a solder weld, 44 is an electrode, 45 is a corresponding electrode, 46 is a solder bump, and 47 is a low EMI package substrate.

In the figure, in the third embodiment, a low EMI package substrate 47 is hermetically sealed with a metal case 38 to form a module structure 39 in a pin grid array. .

The low EMI package substrate 47 has a plurality of pitch expanding electrodes 41 arranged in a matrix on the surface opposite to the surface on which the LSI chip 40 is mounted, and external connection terminals 42 are connected to each of them. Have been. In addition, low EMI
Solder welds 43 are formed to connect and hermetically seal the metal case 38 with the electrodes provided around the mounting surface of the LSI chip 40 on the package substrate 47.

The LSI chip 40 has a plurality of electrodes 44 arranged in a matrix and is connected to corresponding electrodes 45 provided on a low EMI package substrate 47 by solder bumps 46.

The low EMI package substrate 47 basically uses the structure and process shown in FIGS.
In the region 47 between the corresponding electrodes 45 on the low EMI package substrate 47, the first bypass capacitor 1 shown in FIG.
7, a second bypass capacitor 18, and a resistor 19 are formed.

In this case, since the corresponding electrodes 45 are arranged in a matrix on the low EMI package substrate 47, a through-hole is provided in a portion where the first bypass capacitor 17 and the second bypass capacitor 18 are formed. ing. When the corresponding electrode 45 is a power electrode or a ground electrode, no lead pattern is required, so that the inductance component can be reduced, and the frequency characteristics of the first bypass capacitor 17 at a high frequency can be greatly improved. The effect of suppressing the potential fluctuation between the ground and the ground is great.

[0066]

As described above, according to the present invention,
On the surface of a package substrate on which a semiconductor element (LSI chip) is mounted, a series circuit of a second bypass capacitor and a resistor is provided for a first bypass capacitor connected between a power supply pad and a ground pad. Are connected in parallel, and the impedance of the second bypass capacitor is sufficiently reduced with respect to the resistance in the required frequency range, so that the direct current component is cut and at the same time, the power supply pad and the ground pad are connected. In the bypass capacitor circuit, it is possible to reduce the Q value (a value of 10 or less) with respect to the AC component (high-frequency component). That is, the electromagnetic radiation from the wiring connected thereto can be largely suppressed.

Further, according to the present invention, the length of the connection lines between the power supply pad and the ground pad and the first and second capacitors and resistors and the length of the connection line between these elements are almost zero. It is possible to reduce the size, sufficiently suppress the generation of inductance, and sufficiently secure the bypass function of the AC component.

Further, according to the present invention, the occurrence of inductance in each of the above elements can be sufficiently suppressed, the characteristics of each element can be kept good, and the bypass function of the AC component can be sufficiently ensured. it can.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of a low EMI package circuit and device according to the present invention.

FIG. 2 is a circuit diagram showing a circuit model formed on a surface of a low EMI package substrate in FIG. 1;

FIG. 3 is a circuit diagram showing an equivalent circuit when a constraint condition is provided in the circuit model shown in FIG. 2;

FIG. 4 is a diagram showing first and second conductive films of a second embodiment of the low EMI package circuit and device according to the present invention.

FIG. 5 is a view showing a resistor film provided between the first and second conductor films shown in FIG. 4;

FIG. 6 is a diagram showing a first dielectric film provided on the first and second conductor films and the resistor film shown in FIG. 5;

FIG. 7 is a view showing a third conductor film provided on the first dielectric film shown in FIG. 6;

FIG. 8 is a diagram showing a second dielectric film provided on the third conductor film shown in FIG. 7;

FIG. 9 is a diagram showing a fourth conductor film provided on the third dielectric film shown in FIG.

FIG. 10 is a view showing an insulating film provided on the fourth conductor film shown in FIG. 9 so as to cover the entire substrate.

FIG. 11 is a sectional view showing a third embodiment of a low EMI package circuit and device according to the present invention.

[Explanation of symbols]

 1, 22, 40 LSI chip (semiconductor element) 2, 20, 47 Low EMI package substrate 5, 6, 9, 27, 28, 32 Conductive film 7, 30 Resistor film 8, 10, 11, 12, 31, 31 , 34, 35 Dielectric film 13, 23-1 to 23-4 Power pad 14, 24-1 to 24-8 Ground pad 17 First bypass capacitor 18 Second bypass capacitor 19 Resistance

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/822 H01L 25/00

Claims (8)

(57) [Claims] In a low EMI package circuit formed on a package substrate on which a semiconductor device is mounted, a first bypass capacitor connected between a power supply pad and a ground pad of the semiconductor device includes a second bypass capacitor and a second bypass capacitor. A low EMI package circuit, wherein a series circuit with a resistor is connected in parallel. 2. The impedance | Zc ₂ | of the second bypass capacitor according to claim 1,
(= 1 / ωC ₂ : where ω is each frequency and C ₂ is the capacitance of the second bypass capacitor) is sufficiently smaller than the resistance value of the resistor. . 3. The circuit according to claim 2, wherein Q (= ωC ₁ R: where ω is each frequency, and C ₁ is the first resistance) is a circuit in which the first bypass capacitor and the resistor are connected in parallel equivalently. Wherein the capacitance of the bypass capacitor and R is the resistance value of the resistor are set to 10 or less. 4. In a low EMI package structure formed on a package substrate on which a semiconductor device is mounted, a first conductor layer, a second conductor layer, a resistor layer, a first dielectric layer, and a third conductor layer , A second dielectric layer, a fourth conductor layer, a third dielectric layer, a power supply pad and a ground pad, wherein the first conductor has the resistor layer as an inner electrode on the surface of the package substrate. A first dielectric layer formed on a surface of the resistor layer, the first conductor layer, and the second conductor layer. Forming a third conductor layer on the surface of the first dielectric layer;
A dielectric layer, the fourth conductor layer, and the third dielectric layer are sequentially formed, and both surfaces of the first dielectric layer are sandwiched between the first conductor layer and the third conductor layer. And sandwiching both surfaces of the second dielectric layer between the third conductor layer and the fourth conductor layer, and connecting the second conductor layer to the fourth conductor layer near the ground pad. Wherein the power pad is provided on the third conductor layer and the ground pad is provided on the second conductor layer.
MI package device. 5. The low EMI package device according to claim 4, wherein the second and third conductor layers are respectively connected to the power supply pad and the ground pad at a plurality of locations. 6. The low EMI package device according to claim 4, wherein the ground pads are arranged adjacent to the power supply pads in pairs. 7. The low EMI package device according to claim 4, wherein an arrangement pattern of the power supply pad and the ground pad is symmetrical. 8. The low EMI package device according to claim 4, wherein a terminal electrode forming surface of the semiconductor device faces a surface of the package substrate.