WO1996017441A1 - Receiving circuit - Google Patents

Receiving circuit

Info

Publication number
WO1996017441A1
WO1996017441A1 PCT/JP1995/002448 JP9502448W WO9617441A1 WO 1996017441 A1 WO1996017441 A1 WO 1996017441A1 JP 9502448 W JP9502448 W JP 9502448W WO 9617441 A1 WO9617441 A1 WO 9617441A1
Authority
WO
Grant status
Application
Patent type
Prior art keywords
frequency
circuit
signal
output
offset
Prior art date
Application number
PCT/JP1995/002448
Other languages
French (fr)
Japanese (ja)
Inventor
Gen-Ichiro Ohta
Kazunori Inokai
Fujio Sasaki
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/0003Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
    • H04B1/0028Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage
    • H04B1/0032Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage with analogue quadrature frequency conversion to and from the baseband
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00Demodulation of amplitude-modulated oscillations
    • H03D1/22Homodyne or synchrodyne circuits
    • H03D1/2245Homodyne or synchrodyne circuits using two quadrature channels
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45Differential amplifiers
    • H03F3/45071Differential amplifiers with semiconductor devices only
    • H03F3/45076Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/50Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/0003Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • H04B1/26Circuits for superheterodyne receivers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B5/00Near-field transmission systems, e.g. inductive loop type
    • H04B5/0075Near-field transmission systems, e.g. inductive loop type using inductive coupling
    • H04B5/0093Near-field transmission systems, e.g. inductive loop type using inductive coupling with one coil at each side, e.g. with primary and secondary coils
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041Functional aspects of demodulators
    • H03D2200/0047Offset of DC voltage or frequency
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041Functional aspects of demodulators
    • H03D2200/005Analog to digital conversion
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041Functional aspects of demodulators
    • H03D2200/0082Quadrature arrangements
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16Multiple-frequency-changing
    • H03D7/165Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/537A transformer being used as coupling element between two amplifying stages
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/10Means associated with receiver for limiting or suppressing noise or interference induced by transmission
    • H04B1/12Neutralising, balancing, or compensation arrangements
    • H04B1/123Neutralising, balancing, or compensation arrangements using adaptive balancing or compensation means
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D70/00Techniques for reducing energy consumption in wireless communication networks
    • Y02D70/40According to the transmission technology
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D70/00Techniques for reducing energy consumption in wireless communication networks
    • Y02D70/40According to the transmission technology
    • Y02D70/42Near-field transmission systems, e.g. inductive or capacitive coupling

Abstract

A receiving circuit for digital demodulation communication system including channels, which reduces the power consumption of the receiving system, has a simple structure and consumes a small power. Two frequencies higher and lower the middle value of the frequencies of the channels are supplied to first and second frequency converting circuit (2 and 3) respectively from a local frequencyt signal generating circuit (4). Two output signals are generated for each of three signals of desired wave, higher channel, and lower channel. The desired wave commonly existing in the circuits (2 and 3) are extracted by means of a common wave extracting circuit (5). The frequency offset φo in the output of the circuit (5) is removed by means of a frequency offset circuit (6) and the unnecessary frequency components are removed through a filter (8). By using a commons wave extracting circuit (5) having a transformer to utilize the mutual inductance, the difference between the common and noncommon waves is twice larger than that of conventional.

Description

Specification reception circuit

Background of the Invention

[Field of the Invention]

The present invention includes a receiving circuit, in particular to reduce the power of the receiving system, it is possible to simplify the circuit configuration, a receiving circuit capable of reducing power consumption.

[Prior art]

One important Bointo in the receiving circuit of the communication apparatus, to reduce the high-frequency circuit portion squid, lies in reducing a space for manufacturing costs and occupy the high power consuming elements and operating uncertainties inherent in the high-frequency circuit, this Bointo is important, such as moving communications machine. The reduction of the high frequency circuit section, a conventional, direct demodulation method is proposed in a multi-frequency conversion Ya conveyance frequency, direct conversion to direct conversion Ya base Ichisu band to a lower frequency band has been achieved. Then, the high frequency circuit section is mainly have a space diversity receiving function for the antenna requires two systems.

Here, considering the direct demodulation method, a signal having a frequency equal to the carrier frequency generated by the local oscillator, a method of taking out a baseband signal by mixing the received input wave is developed many, in this method, from generating a high-frequency signal of the received signal frequency equal to the frequency, Ru is easily radiated into the air through the antenna of the receiver. Therefore, to interfere with other adjacent receiver, interfere with communication. Therefore, this method is exclusively employed for communication relatively strong frequency modulation scheme in a single-frequency interference.

On the other hand, rapid wireless mobile phone in recent years widespread, is used a so-called PSK which is one amplitude transport modulation, single-frequency interference cause offset in the demodulated output, leading to deterioration of the error rate of the received signal it is intended. That is, since the local oscillation frequency can not choose the carrier frequency, making it difficult to direct frequency conversion or direct conversion of this type of communication system. Force, as a method for solving the mow technical problem, the carrier frequency of the wireless mobile phone and fc, if the offset frequency is fo, obtains the fc + fo and f C-f 0, frequency Ofuse' DOO the provided rows of ivy complementary local oscillation frequency is how to perform the frequency conversion. In executing this method, fc + fo and fc- a f C and f 0 in order to obtain the fo may be multiplied treated with mixer (frequency mixer), but the output this time fc + fo and fc signal for one fo will coexist. That is, the need to separate the signal with respective frequencies to perform the above process, the conventional apparatus can not satisfy this requirement in practical use. Force in the conventional device will be used a filter corresponding to necessarily each frequency?, The carrier frequency of the desired signal is variable, there is a problem would request variable special filter.

Summary of the Invention

General object of the present invention is to solve such conventional problems, primarily in the communication system of the digital modulation scheme having a plurality of channels, to reduce the power required in the receiving system, simplify the circuit However, to provide a receiving circuit capable of reducing power consumption.

Another general object of the present invention is to provide a receiving circuit such as a problem with conventional methods such as described above and solved Subeku frequency ics + fo and fc one fo obtained.

The present invention more specifically, performs a direct frequency conversion the frequency at which the valley between the channel as a local frequency of the receiver with the receiving system, the signal of the frequency offset and the adjacent channel occurring on the output signal and an object thereof is to provide a receiving circuit capable of preventing from being mixed.

The present invention aims to achieve a reduction or replacement by others for large functional unit a review of the structure of the row of Iyori power consumption for each function section constituting further receiver circuit.

To achieve the above object, the receiving circuit of the present invention, as an example, the first and second frequency converting circuit which receives the reception signal received by the antenna, a radio carrier frequency received signal Yes thereby generating an intermediate frequency between a radio carrier frequency with the upper and lower channels adjacent to supply upper frequency of the frequency of the upper and lower two waves as conversion frequency input of the first frequency converting circuit, the lower frequency the extraction and the local frequency signal generating circuit for supplying a conversion frequency input of the second frequency converting circuit, a component present in common in both the outputs of the second frequency conversion circuit of the first frequency conversion circuit a common wave extracting circuit, a frequency offset circuit you remove frequency offset component remaining in an output of the common wave extracting circuit, unnecessary circumferential remaining in the output of the frequency offset circuit It is obtained by a filter for removing wavenumber Ingredient.

The present invention also provides the means to solve the conventional problems, which was added to the local frequency complementary offset type direct frequency conversion scheme underlying the present invention, the reception which is based on a single direct quadrature detector to achieve the space diversity function by a circuit. With the above configuration, the reception signal obtained from the antenna is supplied to the first frequency converting circuit and the second frequency converting circuit, comparable from a local frequency signal generating circuit median between two different Sunawa channels by separately supplying the upper and lower frequency to the first frequency converting circuit Oyo Pi second frequency converting circuit, to generate two respective output signals into three signals of the desired wave and upper Chiyane Le and lower channel . The signal of the first frequency converting circuit and the second is a signal component present in common to the frequency conversion circuit rare Mochiha channel extracted by the common wave extracting circuit. The output of the common wave extraction circuit ω. Since the frequency offset is left performs a minute frequency conversion Te offset frequency circuit odor and divided in the frequency offset circuit the offset amount. After further removing the unnecessary frequency component generated in this process by the filter, base - supplies the baseband signal processing section as Subang de signal. A preferred embodiment of the present invention, the receiving circuit comprises a first and a second frequency conversion circuit, the received signal is connected to the first and second frequency converting circuit for receiving the signal received is the antenna thereby generating an intermediate frequency between lifting one radio carrier frequency of the upper and lower channel adjacent the radio carrier frequency having the upper frequency of the frequency of the upper and lower two waves as conversion frequency input of said first frequency conversion circuit output, and the local frequency signal generating circuit for outputting a lower frequency as conversion frequency input of the second frequency converting circuit, the outputs of said second frequency converting circuit of the first frequency conversion circuit a common wave extracting circuit for extracting a component present in common in both a frequency offset circuit for removing a frequency offset component remaining in an output of the common wave extracting circuit Before SL Bei _ Ru and a filter for removing an unnecessary frequency component remaining in an output of the frequency offset circuit.

Also, a preferred form of the invention, the receiving circuit is connected to the first and second frequency converting circuit which receives the reception signal received by the antenna, the first and second frequency conversion circuitry the received signal strength? with generating an intermediate frequency between a radio carrier frequency with the upper and lower Chiyane Le adjacent to the radio carrier frequency having the upper frequency of the upper and lower two waves frequency of said first frequency conversion circuit output as conversion frequency input, the frequencies contained in the output of the station unit frequency signal generating circuit for outputting a lower frequency as conversion frequency input of the second frequency converting circuit, said first frequency conversion circuit first frequency offset circuit and the second frequency offset to eliminate the second frequency offset contained in the output of the frequency conversion circuits for removing the offset component A circuit, a common wave extracting circuit for extracting a component present in common in both outputs of the first frequency offset circuit and said second frequency offset circuit, remaining in the output of the common wave extracting circuit and a filter for removing an unnecessary frequency component.

According to a preferred embodiment of the present invention, the receiving circuit is connected to the first and the second frequency converting circuit, the first and second frequency conversion circuitry for receiving the signal received by the antenna, conversion of radio carrier frequency and the intermediate while generating the frequency of said first frequency converting circuit the upper frequency of the frequency of the upper and lower two waves having the upper and lower channel adjacent to the radio carrier frequency, wherein the received signal has and output as use frequency input, a local frequency signal generating circuit for outputting a lower frequency as conversion frequency input of the second frequency converting circuit, first quantizing an output of the first frequency conversion circuit commonly present quantizing means, both of the output of the second and second quantizing means for quantizing the output of the frequency conversion circuit, said first quantizing means and the second quantizing means formation A common wave extracting circuit for extracting a filter for removing a frequency offset circuit for removing a frequency offsets fraction remaining in the output of the common wave extracting circuit, an unnecessary frequency component remaining in an output of the frequency offset circuit provided with a door.

According to a preferred embodiment of the present invention, the receiving circuit is connected to the first and the second frequency converting circuit, the first and second frequency conversion circuitry for receiving the signal received by the antenna the thereby generating an intermediate frequency between a radio carrier frequency with the upper and lower Chiyane Le adjacent to the radio carrier frequency received signals have, the conversion of the first frequency converting circuit the upper frequency of the upper and lower two waves frequency output as use frequency input, and a station unit frequency signal generating circuit for outputting a lower frequency as conversion frequency input of the second frequency converting circuit, first quantizing an output of the first frequency conversion circuit a quantization means, the removing and second quantizing means for quantizing the output of said second frequency converting circuit, a frequency offset component contained in the output of the first quantizing means 1 of A frequency offset circuit, a second frequency offset circuit for removing a frequency offsets contained in the output of the second quantizing means, said first frequency offset circuitry and the second comprising a common wave extracting circuit you extracting a component present in common in both the outputs of the frequency offset circuit, and a filter for removing an unnecessary frequency component remaining in an output of the common wave extracting circuit.

According to a preferred embodiment of the present invention, the receiving circuit is connected to the first and second quadrature demodulating circuits for receiving a received signal received by the antenna, the first and second orthogonal demodulation circuit thereby generating an intermediate frequency between a radio carrier frequency with the upper and lower Chiyane Le adjacent to the radio carrier frequency, wherein the received signal has the upper frequency of the upper and lower two waves frequency of the first quadrature demodulating circuit output as conversion frequency input, a local frequency signal generating circuit for outputting a lower frequency as conversion frequency input of the second quadrature demodulating circuit, which is connected to said first and second quadrature demodulating circuit first a first common wave extracting circuit for extracting a component present in common in both the I outputs of the second quadrature demodulating circuit and I output of the quadrature demodulation circuit 1, the first and second quadrature demodulating circuits of connection A second common wave extracting circuit for extracting a component present in common in both the inversion output Q output of the second quadrature demodulating circuit and the Q output of the first quadrature demodulating circuit, said first common removing a first frequency offset circuit for removing a frequency offset component remaining in I output extracted with wave extracting circuit, a frequency offset component remaining in the Q output extracted by the second common wave extracting circuit a second frequency offset circuit, a first filter for removing an unnecessary frequency component remaining in an output of the first frequency offset circuit, unnecessary frequency remaining in the output of the previous SL second frequency offset circuit and a second filter for removing components.

According to a preferred embodiment of the present invention, the receiving circuit is connected to the first and second quadrature demodulating circuits for receiving a received signal received by the antenna, the first and second quadrature demodulating circuits of the thereby generating an intermediate frequency between a radio carrier frequency with the upper and lower channel adjacent the radio carrier frequency received signals have, converting the frequency of the first quadrature demodulating circuit an upper frequency of the frequency of the upper and lower two-wave and outputs as an input, frequency contained in the common lower frequency and the local frequency signal generating circuit for outputting a conversion frequency input of the second quadrature demodulating circuit, the I and Q outputs of the respective quadrature demodulating circuits both I outputs of the first and the second frequency offset circuit, said first frequency offset and the second frequency offset circuit and the I output of the circuit to eliminate the number offset amount Present in common in both the inversion output Q output of the first common wave extracting circuit and said first quadrature demodulating circuits Q output of said second quadrature demodulating circuits for extracting a component present in common in comprising a second common wave extracting circuit for extracting a component, and first and second filter for removing an unnecessary frequency component remaining in an output of the respective common wave extracting circuit.

According to a preferred embodiment of the present invention, the receiving circuit is received by the antenna, the first and second quadrature demodulating circuits for receiving a received signal, is connected to the first and second quadrature demodulating circuits for thereby generating an intermediate frequency between a radio carrier frequency with the upper and lower channel adjacent the radio carrier frequency, wherein the received signal has, for converting said first quadrature demodulating circuit an upper frequency of the frequency of the upper and lower two-wave output as a frequency input, a local frequency signal generating circuit for outputting a lower frequency as conversion frequency input of the second quadrature demodulating circuit, respectively quantizing the I and Q outputs of the first quadrature demodulating circuit first and second quantizing means, and the third and fourth quantizing means for quantizing, respectively it I and Q outputs of the second quadrature demodulating circuit, the first and third quantum means Common a first common wave extracting circuit for extracting a component present in common in the I output, to both the polarity inverted output of Q output of the said and the Q output of the second quantization means fourth quantizing means a first frequency offset circuits for removing a frequency offset component remaining in I outputs issued extracted in the second common wave extracting circuit, said first common wave extracting circuit for extracting a component present in, a second frequency offset circuit for removing a frequency offset component remaining in the Q output extracted by the second common wave extracting circuit, an unnecessary frequency component remaining in the output of the first frequency offset circuit It comprises a first filter for removing a second filter for removing an unnecessary frequency component remaining in an output of the second frequency offsets circuit. According to a preferred embodiment of the present invention, the receiving circuit is connected to the first and second quadrature demodulating circuits for receiving a received signal received by the antenna, the first and second orthogonal demodulation circuit thereby generating an intermediate frequency between a radio carrier frequency with the upper and lower Chiyane Le adjacent to the radio carrier frequency, wherein the received signal has the upper frequency of the upper and lower two waves frequency of the first quadrature demodulating circuit output as conversion frequency input, a local frequency signal generating circuit for outputting a lower frequency as conversion frequency input of the second quadrature demodulating circuit, the I and Q outputs of the first quadrature demodulating circuit, respectively first and second quantizing means you quantization, third and fourth quantizing means for their respective quantizing the I and Q outputs of the second quadrature demodulating circuit, wherein each quantization out Q and I output of the means A first common wave extracting circuit for extracting a frequency offset circuit for removing a frequency offset component, a component present in common in the I outputs of the frequency offset circuit remaining, Q of the frequency offset circuit the removed and the second common wave extracting circuit for extracting a component that exists in common to both 梗性 inverted outputs of the Q output, an unnecessary frequency component remaining in an output of said first common wave extracting circuit It comprises a first filter and a second filter for removing an unnecessary frequency component remaining in an output of the second common wave extracting circuits.

Further according to the invention, in the receiving circuit, a correlator for calculating a cross-correlation instead of the common wave extracting circuit is used.

In the receiving circuit of the present invention, a frequency conversion circuit for inputting the received signal and only the first frequency converting circuit, after the frequency conversion by the first frequency converting circuit, the other frequency conversion circuit, said first to obtain a frequency-converted output of a side who has failed to perform the frequency conversion by the frequency conversion circuit, that to ensure the two frequency-converted output required to the common wave extraction.

Further, in the receiving circuit according to the present invention, only one of the quantization means of the first and second quantizing means with a frequency conversion circuit for inputting the received signal and only the first frequency converting circuit is used after the quantization by said quantization means, digital by frequency converting circuit to obtain a frequency-converted output of the first side has failed to perform the frequency conversion by the frequency conversion circuit, two frequency conversions necessary common wave extraction it is intended to ensure a digital output.

In the receiving circuit according to the present invention, it uses only one of the orthogonal demodulation circuit of said first contact and second quadrature demodulating circuits for inputting a received signal, two outputs of said quadrature demodulating circuits that the by performing frequency conversion by the frequency conversion circuit, respectively, to obtain a frequency-converted output of the side it was not straight 交復 tone, characterized by securing the 2 Tsunojika 交復 tone power required common wave extraction it is.

In the receiving circuit according to the present invention, the quantizing means with using only one of the orthogonal demodulation circuit quadrature demodulation circuit for inputting the received signal is also only the second and third quantization hand stage, the quantization after quantization by means by performing frequency conversion by their respective digital frequency converting circuit two outputs of the quantizing means, to obtain a frequency converted output was not the quadrature demodulation side, the common wave extraction it is characterized in that to secure the two orthogonal demodulation output required.

Furthermore, according to a preferred embodiment of the present invention, the receiving circuit is adjacent to the first and second frequency converting circuit which receives the reception signal received by the antenna, the non-linear carrier frequency the received signal has thereby generating a frequency intermediate between the radio carrier frequency having the upper and lower channels, and outputs the upper frequency of the frequency of the upper and lower two waves as conversion frequency input of the first frequency converting circuit, the lower frequency a local frequency signal generating circuit for outputting a conversion frequency input of the second frequency converting circuits, a low pass. filter for receiving through said first frequency conversion circuit and the second respective input line the output of the frequency conversion circuit first integrating circuit and the second integrating circuit which also serves as a first buffer amplifier for receiving the outputs of said first integrating circuit and the second integrating circuit and A second buffer amplifier, said first buffer amplifier and a second respective output of the buffer amplifier phase equal structure carrying on one end of the primary Koiru first transformer and a second transformer, said first the other end of the transformer and a second transformer primary Koiru the exchanges to grounded to both the secondary Koiru both when connected in parallel together polarity to the polarity of the primary Koiru, output end equal to the polarity of the primary coil and terminal is grounded and the other end, to remove a third buffer amplifier for receiving the output of the first transformer and the second transformer, a frequency offset circuit component remaining in an output of said third buffer amplifier and frequency offsets circuit, in which a filter for removing an unnecessary frequency component remaining in an output of the frequency offset circuit.

According to a preferred embodiment of the present invention, the receiving circuit is adjacent to the first and second frequency converting circuit which receives the reception signal received by the antenna, a radio carrier wave frequency, wherein the received signal has thereby generating an intermediate frequency between a radio carrier frequency with the upper and lower channels, and outputs the upper frequency of the frequency of the upper and lower two waves as conversion frequency input of the first frequency converting circuit, wherein the lower frequency a local frequency signal generating circuit for outputting a conversion frequency input of the second frequency converting circuit, first and second differential receiving through the first frequency conversion circuit and the second respective input line the output of the frequency conversion circuit and dynamic amplifier, the first and second integrated circuits which also serves as a low pass. filter receiving corresponding respective outputs of said first and second differential amplifiers, pre First and second buffer amplifier for supplying an output of the first and second integrated circuits, and means for applying feedback to each of the output side to the negative input side of the first and second buffer amplifiers, At least the AC first and second transformers phases equal structure which receives the respective outputs to one end of the primary Koi Le, the other end of said first and second transformer primary coil of said first and second buffer amplifiers to ground, with the secondary coil is connected in parallel together polarity to the polarity of the primary co-I le, and outputs one end equal to the polarity of the primary coil is grounded and the other end at least alternating manner, said first a third buffer amplifier for receiving the output of the first and second transformer, and the average of the outputs of the second frequency conversion circuit of the third output and said first frequency converting circuit of the buffer amplifier first frequency conversion times compared Between the output and means for applying a correction to the output of the second frequency converting circuit, and an output output output and a second frequency conversion circuitry of said first frequency conversion circuit of the third buffer amplifier means for feeding back to the output side of the output or the second frequency converting circuit of the first frequency converting circuit to correct for differences occurring, a frequency offset remaining in an output of said third slow opposition amplifier a frequency offset circuits for removing a preparative circuit component, those having Ficoll Le evening and for removing an unnecessary frequency component remaining in an output of the frequency offset circuit.

Further, in the receiving circuit according to the present invention, instead of connecting the one end of the secondary Koiru equal to the polarity of the primary Koiru the third buffer amplifier, one end of the different secondary co I le to the polarity of the primary coil third it is characterized in that connected to the buffer amplifier.

In the receiving circuit according to the present invention, the secondary Koiru equal to the polarity of the primary Koiru - instead of connecting the end to the third buffer amplifier, one end of the different secondary coils and the polarity of the primary coil 3 buffer it is characterized in that it has connected to the amplifier.

Receiving circuit of the present invention further includes a first frequency signal source is equal to the carrier frequency of the desired reception signal, the phase of the ττ Ζ 2 at the frequency of this signal receives a signal from the first frequency signal source first means, and 1 2 of the second frequency signal sources have equal to the value of the frequency channel spacing, the second in the frequency response to a signal from the frequency signal source to phase-shift; r Zeta 2 phases to second means Sosuru transfer amount, a multiplier which receives the two signals from the first and second frequency signal source, the two signals from the two kinds of phase shifting means and the input a quadrature modulator comprising a multiplier, and has the two local frequency onset generating means is constituted by from the two groups multiplier and the quadrature modulator comprising receiving a phase shifting means one of the frequency signal .

Receiving circuit of the present invention further includes a first frequency signal source is equal to the carrier frequency of the desired reception signal, the phase of the [pi / 2 at the frequency of this signal receives a signal from the first frequency signal source first means for phase shifting, frequency channel and 1 / have equal to a value of two second frequency signal source interval, the second signal receiving at this frequency from the frequency signal source; of r 2 phases second means for Sosuru transfer amount, a multiplier which receives the two signals from the first and second frequency signal source, the output of only one of the multipliers of the 2 groups was reversed polarity those having a local frequency generating means which is constituted by a means for adding the output of the other multiplier.

The receiving circuit of the present invention, further, a frequency signal source is equal to the carrier frequency of the desired reception signal, at the frequency of this signal receives this signal;: and means to phase shift the phase of the Bruno 2, wherein the frequency signal a quadrature modulator comprising two groups of multipliers receiving from the phase means, local frequency constitutes the output of only one of the multipliers of the 2 groups and means for adding the output of the polarity inversion to the other multiplier, from and it has a generation means.

In the receiving circuit according to the present invention, means for each AZ D converts the first received signal and second received signal obtained by the frequency converting circuit or the quadrature demodulating circuit, first and second receiving the digital outputs and 2 of the full one Rye converters, each correlator for receiving an output for each frequency component of the Fourier transformer, and the weighting function unit for receiving a correlation output obtained, the weighting value multiplier for receiving the output of the weighting function device vessel and said a first Fourier transform output and the adder second undergo Fourier transformation output, the means for inputting the pressurized calculated 桔果 to the multiplier, the inverse Fourier transform for receiving an output of said weighting value multiplier and a vessel, is intended to result desired wave extraction with an inverse Fourier transform output.

According to a preferred embodiment of the present invention, the receiving circuit comprises a receiving input unit Ru receiving a received signal from the antenna, and a row Nau quadrature demodulator frequency conversion processing on the received signal from the reception input means, orthogonal first and second AZD converter for converting an analog signal into a Digitally Le signal inputs an output signal from the demodulator, 2 times or more the frequency corresponding to the bandwidth possessed by the received signals to these AZD transducers and San Bring clock generator for generating a clock, and a circuit for adding a delayed pulse train to a pulse train from the sampling clock generator, a delay pulse train and the AZ D converter pulse train from the sampling clock generator It means for providing a sampling pulse, the hand of extracting quadrature components of the received channel signal desired from the digital output data of the AZ D converter Those having a stage. According to preferred ^ embodiment of the present invention, the receiving circuit includes a reception input means for receiving a received signal from the antenna, and a straight 交復 adjuster that performs frequency conversion processing on the received signal from the receiving input unit, quadrature demodulation first and second AZD converter for converting an analog signal into a digital signal by an output signal from the vessel, generating a clock frequency of at least equivalent to the lifting one bandwidth of the received signals to these AZD transducers a sampling clock generator which, with circuitry for adding a delayed pulse train to a pulse train from the San bling clock generator, a sampling pulse of the pulse train from the sampling click-locking generator and the delayed pulse train the AZ D converter and means for providing, and means for extracting a quadrature component of the received channel signal desired from the digital output data of said AZD converter as, A pulse train from the sampling clock generator, a delay and a delay pulse train from the pulse train adding circuit, desired frequency of the channel signal; delayed pulse train to the delay time of the outside phase Sa以 the corresponding one or more in Γ According to der invention that so as to generate, in the receiving circuit, the sampling clock pulse train from the generator, and a 遝延 pulse train from the circuit for adding a delayed pulse train, r Z of the frequency of the desired channel signal it is to the delay time of the phase difference corresponding to 2.

According to a preferred embodiment of the present invention, the receiving circuit includes a reception input means for receiving a received signal from the antenna, a first AZD converter for performing A / D conversion to input the received signal, a second AZ D a converter, a sampling clock generator for generating a corresponding frequency or clocks 带域 width possessed by the received signals to these AZD converter, a circuit for adding a delayed pulse train to a pulse train from the sampling clock generator , one having a means for providing a pulse train and the delayed pulse train from the sampling clock generator as sampling Nguparusu the AZD transducer, and means for extracting a received channel signal desired from the digital output data of said AZD transducer is there.

According to the present invention, occurs in the receiving circuit, the pulse train from the sampling clock generator, the delayed pulse train to a phase difference time corresponding the circuit for adding a delayed pulse train to a 2 [pi Zeta frequency of the desired channel signal it is intended to.

Further according to the invention, in the receiving circuit, the sampling clock pulse train from the generator, the delayed pulse train and the phase difference time corresponding to 2 [pi Zeta frequency of the desired channel signal from the circuit for adding a delayed pulse multiple train generator it is intended to be.

According to a preferred embodiment of the present invention, the receiving circuit includes a reception input means for receiving a received signal from the antenna, and a single AZ D converter for performing A / D conversion to input the received signal, the AZD transducer a circuit for adding the sampling click-locking generators that occur over a clock frequency corresponding to a bandwidth possessed by the received signal, a delayed pulse train to a pulse train from the sampling click-locking generators, this those having means for providing a pulse train and the delayed pulse train from the sampling clock generator as the sampling pulses of the AZD transducer, and means for extracting received Chiyane Le signal desired from the digital output data of said AZD transducer .

According to a preferred embodiment of the present invention, the receiving circuit comprises a receiving input circuit Ru receiving the received signals from a plurality of antenna, the first and second frequency conversion means for receiving the received signal, the first and second a local oscillator for providing an output to the desired wave carrier frequency second frequency converting means at a frequency which has been subjected to 1 Z 2 frequency offset number channel spacing frequency, before Symbol each of the first and second frequency converting means first and second AZ D converter to obtain a signal, a sampling clock generator for generating a higher clock frequency corresponding to a bandwidth possessed by the received signals to these AZD transducer from the Sanburinguku lock generator a circuit for adding a delayed pulse train to a pulse train, the pulse train from the sampling clock generator and the delayed pulse train of the a / D converter Samburu down Guparusu Means for providing to those having a means for extracting a received channel signal to hope from the digital output data of said A / D converter.

According to the present invention, in the receiving circuit, providing the local oscillator you supplied to the first and second frequency converting means independently of the Channel spacing frequencies around the desired wave carrier frequency of each local oscillator frequency 1/2 it is an feature that the frequency Ofuse' bets and frequency applied to the positive and negative.

According to the present invention, in the receiving circuit, the two received signals is characterized in that the supply to the first and second AZD converter without frequency conversion.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects and features of the invention will become more apparent depending on details described implementation with reference to the accompanying drawings.

Figure 1 is Ru Proc view showing a configuration of a receiving circuit in the first embodiment of the present invention.

Figure 2 is Ru Proc view showing a configuration of a receiving circuit in the second embodiment of the present invention.

Figure 3 is Ru Proc view showing a configuration of a receiving circuit in a third embodiment of the present invention o

Figure 4 is Ru Proc view showing a configuration of a receiving circuit in a fourth embodiment of the present invention.

5 proc view showing a configuration of a receiving circuit in the fifth embodiment of the present invention

Ό

Figure 6 is Ru Proc view showing a configuration of a receiving circuit in a sixth embodiment of the present invention.

Figure 7 is Ru Proc view showing a configuration of a receiving circuit in the seventh embodiment of the present invention.

Figure 8 is Ru block diagram showing a configuration of a receiving circuit in the eighth embodiment of the present invention o

Figure 9 is Ru Proc view showing a configuration of a receiving circuit according to a ninth embodiment of the present invention.

Figure 1 0 is a block diagram showing the configuration of a receiving circuit in the first 0 embodiment of the present invention.

Figure 1 1 is a block diagram showing the configuration of a receiving circuit in the first embodiment 1 of the present invention.

Figure 1 2 is a block diagram showing the configuration of a receiving circuit in the first and second embodiments of the present invention.

Figure 1 3 is a block diagram showing the configuration of a receiving circuit in the first to third embodiments of the present invention.

Figure 1 4 is a block diagram showing a configuration of a reception circuit in the embodiment of the first 4 of the present invention.

Figure 1 5 is a conceptual trans diagram in the first to fourth embodiments of the present invention.

Figure 1 6 is a block diagram showing the configuration of a receiving circuit in the first to fifth embodiments of the present invention.

Figure 1 7 is a block diagram showing a configuration of a first 5 receiving circuit that embodies I inhibit the embodiment of the present invention.

Figure 1 8 is a block diagram showing a configuration of a reception circuit in the embodiment of the first 6 of the present invention.

Figure 1 9 is a block diagram showing the configuration of a receiving circuit in the first to seventh embodiments of the present invention.

2 0 is a schematic diagram for explaining a local frequency setting method in the embodiments of the present invention.

Figure 2 1 is a block diagram showing a configuration of a reception circuit in the embodiment of the first 8 of the present invention.

2 2 is a block diagram showing a configuration of a reception circuit in the embodiment of the first 9 of the present invention.

Figure 2 3 is a block diagram showing the configuration of a receiving circuit in the second 0 embodiment of the present invention.

Figure 2 4 is a block diagram showing the configuration of a receiving circuit in the second embodiment 1 of the present invention.

2 5 is a conceptual diagram of a transformer according to the second embodiment 2 of the present invention.

2 6 is a diagram for explaining a state where AZD converter results sampling was rows Eiriasu occurs in the second second embodiments of the present invention.

2 7 is a diagram showing a state of the reception Chiyane Le in a multi-channel communication system for use in the present invention.

2 8 is a diagram showing an AZD conversion output having a negative frequency region appearing in the second and second embodiments of the present invention.

2 9 is in the second second embodiments of the present invention; illustrates a method of decomposing a quadrature component signal Ingredient utilizing a phase difference of r / 2 by the cosine and sine 閱数. 3 0 is a diagram showing an example of a quadrature sampling operation in the case of AZD converting the two signals to be orthogonal to the second embodiment 2 of the present invention.

3 1 is a diagram in consideration of the offset in the quadrature sampling illustration of FIG. 3 0.

3 2 is a diagram showing an example of FIG. 3 0, another quadrature sampling operation different from the 3 1 in the case of AZD converting the two signals to be orthogonal to the second embodiment 2 of the present invention.

Figure 3 3 is a diagram illustrating a sampling pulse obtained when performing quadrature sampling operation shown in FIG. 3 2 in the second second embodiments of the present invention.

3 4 is a block diagram showing the configuration of a receiving circuit in the second and third embodiments of the present invention. 3 5 is a diagram showing an example of a quadrature sampling operation in which the second 3 two orthogonal signals AZ D conversion in the embodiment of the present invention.

3 6 is a proc diagram showing the configuration of a receiving circuit in the second to fourth embodiments of the present invention.

3 7 is a diagram showing an example of a quadrature sampling operation in the case of AZD converting the two signals to be orthogonal to the second to fourth embodiments of the present invention.

Figure 3 8 is a block diagram showing the configuration of a receiving circuit in the second to fifth embodiments of the present invention.

3 9 is a simplified block diagram for explaining an operation of the sampling signal generating source portion in the embodiment of the second 5 of the present invention.

4 0 is a proc diagram simplified for explaining another operation of the San bling signal source portion in the embodiment of the second 5 of the present invention.

4 1 is a simplified block diagram for explaining another operation of these sampling signal generating source portion in the embodiment of the second 5 of the present invention.

4 2 is a frequency K 置概 view diagram of Japanese standard digital type automobile telephone system used for description of the embodiments of the second 6 of the present invention.

4 3 is a channel arrangement schematic view of the Japanese standard digital type automobile telephone system shown in FIG 2.

Figure 4 4 ​​is a proc diagram showing a configuration of a reception circuit in the embodiment of the second 6 of the present invention.

4 5 is a proc diagram showing a configuration of a reception circuit in the embodiment of the second 7 of the present invention.

4 6 is a block diagram showing a configuration of a reception circuit in the embodiment of the second 8 of the present invention.

Figure 4-7 is a block diagram showing the configuration of a receiver circuit embodying the embodiments of the second 9 of the present invention.

Figure 48 is a proc diagram showing the configuration of a receiving circuit in the thirtieth embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter will be described an embodiment of the present invention, prior to be described rationale of the present invention. First, description subject binary PSK i.e. BPSK is often used in the current digital modulation schemes.

BPSK signal S B at base frequency or base band can be expressed as follows.

S B = Acos (0 k) However, A is拫幅, 0 k in the phase representing the BP SK information,

k = 0, π

The modulated output S c obtained by modulating the baseband signal at a carrier angular frequency can be expressed as follows.

S C = S BX a cos ω ct + S B (Θ k- ^ r- π) xa cos (ωο 1 --- π)

A. c = a A, Θ k = 0, π = A c cos (ω ct + ίί ( E) receives the modulated signal, the frequency conversion by the frequency conversion local frequency "C, frequency converted output S R It is expressed as follows.

^. = I X b cos ω ct

= Α ς 'b [cos (2o c I + 9k) + cos {f> k) 1

2

AC

Put the AR

A R (cos I2wc I + Θ k} + cos (Θ kl.... (2) removing high frequency components 2 w c through the frequency converted output S R to the low-pass filter result, the output S RF is becomes as follows, binary PSK i.e. BPSK signal can be demodulated.

S «p = A R cos ( 0 \ O -O, ττ

.... (3) However, because of performing the local oscillation frequency at a carrier frequency the same o c in the frequency conversion of the received, from the receiver radiated this local oscillation frequency signal into the air, the other receivers of the near to give the interference.

The present invention is, to set the local Kiwamufu frequency as follows in order to solve such problems. Figure 20 illustrates a method of setting the local oscillation frequency of the present invention. In Fig. 20, A shows the band of a desired channel, the carrier frequency. It is. B represents a带域of 1¾ contact channels of the upper side, the carrier frequency is Wcu. C represents the带域of the lower adjacent Channel, the carrier frequency is WCL. Spacing between the carrier of each channel is about four times the distance between the base frequency Wb of BPS K.

带域of each channel becomes ± 2 o b around the carrier frequency. Therefore, position away i of base frequency 2 Wb from each carrier frequency is in the valley between the channels, also interfere less for锒Supeku torr of any interference wave be present channel in this position. That is, the present invention focuses on this point, the setting the local oscillation frequency of the receiver intermediate the adjacent channel carrier frequency and the main way for the problem solution.

Then, in the case of setting the local oscillation frequency of the receiver Thus, as obtained in the same manner demodulation conventional, that how to build circuits subsequent, using equations for the other one of Bointo of the present invention It described Te. It receives the modulated signal, as described above the local oscillator frequency for performing frequency conversion of the receiver ω ε + ω. When set, the frequency-converted output S R is as follows.

S = o X b cos (ω + ω β) t

5 Λ Γ · b,

= - cos {ω c I + Θ k) CDS (ω c + α> o)

2

A c. B

: ~ = A R and B ECTS

= A R (COS {2 ω C + · ω O) t + 6 k) + ~ et, S C-αι ot + Θ k)] 0.... (4) Robasu this frequency-converted output S R If you remove the high-frequency component 2 w c through the filter, its output is

S RF = A R i cos ( -ωο t + 9 k)} «k = 0, n

Five

.... (5), and the frequency omega 0 only binary PS took the offset kappa i.e. BPS kappa signal is generated.

Then ω from the carrier frequency w c of the desired channel the local oscillator frequency. Only the low-les-ω c - set to ω o 20. Frequency-converted output S L in this case is as follows.

SJ = S> eight b COS, ω C- ω o) t

A r - b,, ", ,, A

= ~~ COS {cue t + Θ COS l ως-ω 0 t

A c · b

"-" = A R and B ECTS

One fc = A R [cos (2ωο -ωο + Θ k} + C0S {ω I + Θ) I.... (6) to remove the high-frequency component 2 omega c through the frequency-converted output SL in the low-pass filter With that, the output of which,

S LF = A R cos (ωο t + Θ k) Θ k = 0. π

.... (7) and, BPSK signal phase is also equal to the occur. Meanwhile, since the local oscillation frequency of the reception are equidistant from the adjacent channels, the signal demodulation is also mixed-generating component of the adjacent channel. Signal of the upper ^ contact channel, expressed a carrier frequency at ω α, ω ^ -α ^ + 2 ω. Since it is, the frequency conversion of the reception side described above is as follows.

First, receiving the modulated signal, shaken Ri omega described above the local oscillator frequency for performing frequency conversion of the receiver epsilon + omega. When set, the frequency converted output is as follows.

o Rh = 0 h X b cos ωι; + ωο) t A rh · b

= ~ ^ [Cos {we t + 2ωο t + 0 hi Ji us (OJC + wo) t]

2

A rh · b

^ ~ = And A Rh and匱Ku

= A Rh (cos ((2 uc + 3a) o) T + 5 h) + cos I u »ot + θ i ]

.... (8) removing Then a high-frequency component 2 through the frequency converter output 5 omega low pass filter whose output, S RFh = A Rh C0S ot + ")

0h = O, Ji

.... (9) and, BPSK signal present in the same 带域 and desired channels. On the other hand, the signal of the adjacent channel of the lower, the carrier frequency W C | Expressed in, £ ^, = 0 ^ one 2 omega. Since it is, the frequency conversion of the reception side described above is as follows.

First, the local oscillation frequency of the receiver is set to a c + 0 as described above, the frequency converted output S R, is as follows.

S j¾ | = o QJ X b cos (ω c + ω o) t

= ~ £ i ~ - cos ί (w -ΐω ο) t + θ \\ cos (ω c + ω ο) t)

2

A C) · b

Ku and Β | A R

2

A R, [COS (2 cue t-ω ot + Θ l) - + - COS (-3 ω 0 t preparative theta I)]

0h = O, π

.... (1 0) this frequency-converted output S R, removing Then high frequency components 2 omega c through a low pass filter, whose output is

S RFI = ARI LCOS (3 ωο t - Θ l) ]

.... (1 1) and, 3 ω than the desired channel. BP SK signal is generated in the frequency away. Then, the local oscillation number of ^ one w. To examine the condition being frequency converted adjacent channel when it is. Signal of the upper adjacent channel, expressed a carrier frequency in Wch, ^^ ten 2 omega. Since it is, the local oscillation frequency is Te omega c one omega Q "frequency conversion of W if is as follows.

First, receiving the modulated signal, as described above the local oscillator frequency for performing frequency conversion of the receiver ω c - ω. When set, the frequency-converted output S u is as follows.

_ A _Cb [O s {ω ct -2ω ot - + Θ h) Ji OS (ωο-ω ο) t ]

A Ch. B

- put the 1 ~ = A Rh

= A (cos f (2o) c + o) o) t + Θ l>} + cos {3ωο t 4 · Θ h) 3

Rh

.... (1 2) this frequency-converted output S u high frequency through a low-pass filter component 2 (Removal Then, the output is as follows.

S LF h = A Rh (cos (3ωο t + ί> h) ]

Θ h = 0. Π

... - (1 3) On the other hand, the signals of adjacent channels of the lower and represents the carrier frequency in ω α, ω α = ω £ : one 2 omega. Since it is, the frequency conversion of the reception side described above is as follows.

First, the local oscillation frequency of the receiver w c as previously described - Set to omega 0, frequency conversion output S u is as follows.

S and | =: 3 ci X b cos (ω c- uo) t A Ji, · b

<= - ^ (cos f (ωο-2ωυ) 1 + f / I) cos (ωο-ω o) t]

D 2

Ac to b Λ.

"~; = R | and put and

= A L, Ccos ί (2ωο -3ωυ) t ^ ί> lj) + COS (-ω ot + θ l)] 0

.... (1 4) removing high frequency components 2 o c through the frequency converted output S u low pass filter result, the output of which

SLA R | cos ωο ΐ - 9 U

Five

..., (1 5) and, BPS kappa signal is generated in the same frequency as the desired channel.

In summary from the above, w the local frequency on the upper side. Output in the case where the shift only is the three following. 0

SR F = A R cos (-ωο t + ilk) the desired channel

S RFh = A Rh cos (ωοΐ + «h) the upper channel

S R F1 = A R, cos .... (3o »ot - ii i) T -side channel 5 (1 6) ω a local frequency to the lower. The output of the case shifted by are the following three types.

S LF = A R cos (ωο t + Θ k) the desired channel

S LFh = A Rh cos (3 oot + Oh) t -side channel

S and Fl - A R | cos (ωο 1 - θ \) lower channel

.... (1 7) common component in this two groups are present only on the desired channel. Accordingly, if supplied to the adder both as two inputs, it will be taken out only the desired channel to its output. In addition, the output is, ω. Frequency offset is applied only, but this can be removed by a simple frequency Ofuse' bets circuit.

The present invention has been achieved by the embodiment shown this principle below. Shape of the chamber i 1

Figure 1 shows a configuration of a receiving circuit of the first embodiment of the present invention. In Fig 1, 1 is antenna receiving the reception signal, the first contact and the second frequency converting circuit 2 and 3 and inputs the received signal, 4 is lower on an adjacent radio carrier frequency received signals have thereby generating an intermediate frequency between the carrier frequency with the channel, the upper frequency of the frequency of the upper and lower two waves as the first conversion frequency input of the frequency conversion circuit 2 outputs a lower frequency second the local frequency signal generating circuit for outputting a conversion frequency input of the frequency converter 3, 5 a component present in common in both the outputs of the first frequency converting circuit 2 and the output of the second frequency converting circuit 3 common wave extracting circuit for extracting a frequency offsets circuit for removing a frequency offset component remaining in an output of the common wave extracting circuit 5 6, 7 offset by performing a minute frequency conversion! : Offset frequency generating circuit for supplying to the frequency offset circuit 6, 8 is a filter for removing an unnecessary frequency component remaining in the output of the frequency offset circuit 6.

Next the operation of the receiving circuit of the first embodiment. According to equation described above, the received signal obtained from the antenna 1 is supplied to the first frequency converting circuit 2 and the second frequency converting circuit 3, two different frequencies from the local frequency signal generating circuit 4, i.e. between the channels by the upper and lower frequencies comparable to the median of the separately supplied to the first frequency converting circuit 2 and the second frequency converting circuit 3, respectively, for the three signals of the desired channel and Ue惻 channel and lower channel 2 One of the output signal is produced. According to Equation deployment signal component present in common in the first frequency converting circuit 2 and the second frequency converting circuit 3 is only signal of the desired channel, the common wave extracting circuit 5 for extracting a balanced Ingredient by supplying, equilibrium components consisting mainly of the desired wave is obtained. The output of the common wave extracting circuit 5, ω. Since the frequency offset is left performs a minute frequency conversion in the offset frequency generating circuit 7, to remove the offsets amount in the frequency offset circuit 6. Further after removal of the unnecessary frequency component generated in this process by the filter 8, (not shown) to the baseband signal processing section as a baseband signal and supplies.

Form of Gai施 ^ 2

Figure 2 shows a configuration of a reception circuit of the second embodiment of the present invention. And have you in FIG. 2, 1 antenna for receiving a received signal, first and second frequency converting circuits 2 and 3 for receiving the reception signal, 4 is a vertical adjacent to the radio carrier frequency received signals have thereby generating an intermediate frequency between a radio carrier frequency with the channel, the upper frequency of the frequency of the upper and lower two waves as the first conversion frequency input of the frequency conversion circuit 2 outputs a lower frequency second the local frequency signal generating circuit you output as conversion frequency input of the frequency converting circuit 3, 6 Alpha first frequency offset to eliminate the frequency offset component contained in the output of the first frequency converting circuit 2 circuit, 6 B and the second frequency offsets circuit, 7 a each frequency offset amount by performing a minute frequency conversion to remove the frequency offset contained in the output of the second frequency converting circuit 3 offset Offset frequency Mizunotosei circuit for supplying a preparative circuit 6A, 6 B, 5A extraction a component present in common in both the outputs of the first frequency offsets circuit 6 A and the second frequency offset circuit 6 B common wave extracting circuit for, 8 a is a filter for removing an unnecessary frequency component remaining in an output of the common wave extracting circuit 5 a.

Next, the operation of the receiving circuit of the second embodiment. This embodiment is different from the first embodiment have been replaced and the step of performing a process and frequency offsets to perform common wave extraction. That is, by the preceding row of cormorants process the frequency offset, signal of the desired channel as it is the base band signal, can be expected more stable extraction operations.

The following describes validity when preceded frequency offset process. ω a local frequency on the upper side. In the case of frequency offset with respect to only shift the signal group, ω. , Which makes it shifts only remove, output is less than three.

° RF = A R cos (2ωο t - Θ k) the desired channel s R Fh = A R |, cos (Θ) h -side channel

S R F1 = A R, cos (4OJ O t-θ i) lower Chiyanenore

... · (1 8) Further, in the case of frequency offset relative to shifted signal group omega 0 to lower the local frequency, omega. , Which makes it shift to only remove, output is less than three.S LF = A COS (2 ω ot + «k)

The desired channel S LFh = A Rh cos (4ω "t +« li) t -side channel S LFl = R, cos (θ I) f -side channel

.... (1 9) common component in this both groups still present only in the desired channel. Te the month, if supplied to the adder both as two inputs, the retrieve the BP SK signal only the desired channel to its output.

Form of 宥施 ^ 3

Figure 3 shows the configuration of a reception circuit of the third embodiment of the present invention. And have your 3, 1 antenna for receiving a received signal, first and second frequency converting circuits 2 and 3 for receiving the reception signal, 4 is a vertical adjacent to the radio carrier frequency received signals have with the channel ^! with generating an intermediate frequency between the carrier frequency, the upper frequency of the frequency of the upper and lower two waves as the first conversion frequency input of the frequency conversion circuit 2 outputs, the lower frequency local frequency signal generating circuit you output as conversion frequency input of the second frequency converting circuit 3, 9 a first bandpass filter for waveform-shaping the output of the first frequency converting circuit 2, 10 a first first AZD converter for converting the output of the band pass filter 9 a to di di Yuru signal, 9 B is a second bandpass filter for waveform-shaping the output of the second frequency converting circuit 3, the 108 second di Bruno, * the output of the command-pass filter 9 B Second AZD converter for converting the barrel signal, 5 B is extracted common wave extracting a component present in common in both the outputs of the first AZD variant interchangers 10 A and second A / D converter 10B circuit, 6 C frequency offset circuit for removing a frequency offsets fraction remaining in the output of the common wave extracting circuit 5 B, 7 B is subjected to minute frequency conversion O Fuse' preparative i the frequency offset circuit 6 C offset frequency generating circuit for supplying a, 8 B is a filter for removing an unnecessary frequency component remaining in an output of the frequency Ofuse' preparative circuit 6 C.

Next the operation of the receiving circuit of the third embodiment. This embodiment, the output of the first as in the embodiment of two frequency converting circuits 2, 3 and quantized by their respective AZD converter 1 0A, 1 0B, first using a digital operation action embodiment equivalent to, that is, to perform common wave extraction and the frequency offset and filtering. Common wave extraction and filtering, using a digital filter technique, the frequency offset is less made possible by using a digital quadrature modulation, the principle of the present embodiment, the orthogonal PSK that have been widely used in the digital modulation type that is described intended for QP SK or 4 value Q AM.

QPSK signal S B at base frequency or base band can be expressed as follows.

S 8 = Acos (Θ k) + j Asin (θ 0 , however, j is imaginary unit representing the imaginary axis orthogonal to the real axis, A is the amplitude, 0k is 0k = (± phase representing the Q PSKffi report

¾ AK

~ Sat "

.... (20) modulated output S c which modulates the pace band signal at a carrier angular frequency can be expressed as follows.

S "= S ^ a vcos (shed ct + J sin ω ct

= A ς · I cos ( « c 4- β k) + j sin (wct + 0lt) 1 However, A c = ax 2 A flk « soil -. ^ "

~ (Cos {ω ct ten "} 3 -I ^ = · fj sin (<« ct + 8 k)).... (2 1) where, in general real axis component I-axis signal, a 虛軸 component It referred to as a Q-axis signal. receiving the modulated signal, when the orthogonal demodulation in the frequency conversion local frequency w c, quadrature demodulation I-axis output S K is expressed as follows.

S 1 R = S c X b cos ω ct A c · b

= - ^ Ccos {ω ct + Θ k) cos ω c I]

2X2

A c. B

Put = and A

- A R [eos (2ω ct + Θ ic} --cos {Θ kl

.... (2 2) removing Then, its output a high-frequency component 2 omega through the quadrature demodulation I-axis output S K to the low pass filter It is,

S 1 R rt

.... (2 3) and, I-axis signal of the quadrature PSK i.e. QPSK signal can be demodulated. And power, and, as in the description, this case is also the same omega c and frequency local oscillation frequency feed transportable in quadrature demodulation, from the receiver the local oscillation frequency signal is emitted into the air, the proximity disturb the other receivers. Therefore, by setting the local oscillation frequency of the receiver to the description as well as w c + omega 0, orthogonal I-axis output S kappa demodulation becomes as follows. SIR = S Ji X b cos (ω c + ω o) 1 A, · b

= ^ [Cos {ω ct + Θ k) cos (ωθ + ω o) t J

2

AC

A

2 It rather

= A n [cos ((2a / c + ω) r + Θ kl ten cos (uot -.) - Θ k) 3

.... (24) removing Then a high-frequency component 2 omega through the quadrature demodulation I-axis output S K to the low pass filter, whose output is

SJ r, p = A R [ cos (ω ot + Θ it) ]

.... (25) becomes, I-axis output of the quadrature P SK i.e. Q PS K signal is obtained.

Then local oscillation frequency hope only omega 0 from the carrier frequency of the channel lower w c - omega is set to 0. Frequency conversion output St of this case is as follows.

° IL = SX b cos (ω c- ω o)

A • hb

Ccos (we t + Θ V) cos (ωο-ω o) t]

2

A c 'b

2 * = put the A R ]

.. ... (2 6) removing Then a high-frequency component 2 w c through the quadrature demodulation I-axis output S L to the low-pass filter, the output S Nj3 is, S j L ρ = A R COS (- ω ot + Θ

9k = ~ (ten _4, π

, Sat two 4

. ... the (2 7). Obtaining an output and removing high frequency components 2 omega zeta through the quadrature demodulation I轴出force S to the low-pass filter.

Meanwhile, the signal to be demodulated of adjacent channels in an equal 距雌 from the reception local oscillation frequency is as follows. That is, the signal of the upper adjacent channel, expressed in the carrier frequency, Wch = w c + 2 ω . Since it is, the local oscillation frequency w c + o. For the orthogonal demodulation I-axis output is as follows.

SIR h = ^ hb COS (ω c + α »o) t - A C h · b

= 2 Ccos (we t + 2ωο 1 + 0 h) cos (ωο + ω o) t]

AC h

A R h and ECTS

S IR h = A R h [ cos {(2ως + 3ωο) 1 + Θ I + COS I ωο I + Θ h I ]

.... (28) If you remove the high frequency components 2 omega through the quadrature demodulation I-axis output to a low pass filter, the output S IRFh is, IRF h = A R h [ COS (ω o I + Θ h)]

(± ~, soil [pi. ... (29), and the orthogonal P SK i.e. QP SK signal present in the same带域and desired channels.

On the other hand, the signal of the lower K contact channel, to represent the carrier frequency at ω α, Wa = o / c one 2 omega. Since it is, as the local oscillation frequency of the aforementioned w c + W. If set to the reception side quadrature demodulation I-axis output S m is as follows.

S j R J = S 1 X b cos (ω c + ω oJ t

A · b

= ~ ^ [Cos {(ως-2ωο) + 0 1 I COS (ωθ + ω o) t]

2

A c, · b

- = A K, and H ECTS

- A R, [cos (2ω Ji t -ωο t + 0 \) + CS (-ωο I + θ 1) ]

.... (30) When divided frequency component 2 c c through the quadrature demodulation I-axis output S mouth one-pass filter, whose output is

SJ R pj = A R, ( .COS (-ωα t + 9 I) J

Θ 1 = (± 4-, ± - ~) K

4 4

- ... (3 1), and that occur orthogonal PSK i.e. QF SK signal to the same frequency as the desired channel is o

Then the local oscillation frequency of the receiver as described above w c + omega. And, the phase; Delaying 2 only, orthogonal condensate axis output S QR is obtained as follows.

b

[Cos (ω ct 4- S k) sin (ω + ω o) t]

AC

AR and 匱Ku

2

= A R Csin [(2UJ C + ωο) t + β kl - sin (-uo t + Θ k)]

.... (32) removing Then a high-frequency component 2 omega zeta through the quadrature demodulation Q-axis output S QR low pass filter, the output S QRF is

S p R p = A R sin (-ω ot + ί> k)

• ... (33) next, Q-axis output of the quadrature PSK i.e. QPSK signal.

Then lower by ω 0 the local oscillation frequency from the carrier frequency of the desired channel w c - ω. Consider the case of delayed RZ2; phases of setting to. Quadrature demodulating the Q-axis output S QL in this case is as follows. Q τ = a ^ X b sin (ω c- ω o) t = ^ £ [cos (ωο I + 0 kl sin (wc-ωο) t]

2

A r · b

- 2 - "" = A R and g ECTS S QL = A R (sin ( (2ωο + ωο)) + ^ ^ + Sin (ω ot + Θ k) ]

.... (34) removing Then a high-frequency component 2 w c through the quadrature demodulation Q-axis output S QL low pass filter, the output S QLF is

Θ k = (:, ± 4 → K

. (35), and the different orthogonal PSK signal Q-axis output of棰性is obtained from the S QPP,

Then analyzed with respect to adjacent channels for quadrature demodulating the Q-axis output. Signals of adjacent Channel upper, expressed a carrier frequency in omega alpha, because it is ωαι = ^ + 2 ω 0, the local oscillation frequency o c + w. If set, the quadrature demodulation Q-axis output S QRH upper channel is as follows. ORh = S ch x bsin, oc ten ωο) tb

(Comp) OS {u> ct + 2uio t ten 0 h | sin (ω c + cu o)

AC h

A Rh and S ECTS

= A R h [sin I ( 2ωο + 3ωο) t + 6 h I tens sin I ω nt + h} J

• ... (3 6) removing high frequency components 2 omega c through the frequency converted output S QRH low-pass filter result, the output S QU ^ is

S QR F h = A R h Csin (ot ]

Theta h = (Sat +, ± ~ 4 ~ ^ π .... (3 7) , and the quadrature PSK i.e. QP SK signal Q-axis output present in the same band and desired channels.

Similar processing is performed for the signal of the lower Fuse' channel. The carrier frequency ω α, o a = w c - 2 ω. Since it is, the local oscillation frequency w c + w. Quadrature demodulation Q-axis output s QR1 in is as follows.

SQ R 1 = S one X bsin ω c + a> o ) I

A b

[Cos {(ω c-2 ω υ) l + 8 I) sin (ω c + cu o) t]

2

AC 1

A R, and fi ECTS

= A R! Csin (2ωο t -ωο t + non-I) + sin (-3ωο t + Θ 1)]

.... (3 8) when divided high frequency components 2 w c through the quadrature demodulation Q-axis output S QRI low-pass filter, the output S QRH is

S QR pj = A p, Csin (-3ωο t + θ I)] ίΜ = (± ten, ± -j ~)

• ... (3 9) next, 3 ω than the desired channel. Quadrature PSK i.e. QPSK signal frequency away Q-axis output is generated. Next, the local oscillation frequency o c -!? Ω 0 death and the case was !! contact channel quadrature demodulation Q-axis output of

S QR is as follows. That is, the carrier frequency of the signal of the upper K contact channels, ω α = ω 0 + 2 ω. Since it is, the local oscillation frequency o c - quadrature demodulation Q-axis output S QRH in omega 0 is as follows,

Ar h - b, t,

= [Cos i ω ct + 2 ω ot + 0 h} sin (ω c- ω o) t J

A Ch, b Λ

- = and A R h "ECTS

SQ R h = A R [sin I (2ωο + ωο) t + Θ h) ten sin (3ωο t + 0 h) J

.... (4 0) when divided high frequency components 2 w c through the quadrature demodulation Q-axis output S QRH low-pass filter, the output S QRFh is

κ

.... (4: 1) and, 3 ω than the desired channel. Orthogonal PS kappa i.e. QPSK signal Q-axis output is generated exists at a distant 带域.

Similar processing is performed for the signal of the lower adjacent channel. The carrier frequency ω α, w a = w c - 2 ω. It is. The local oscillation frequency of the receiver w c - ω. , And the quadrature demodulation Q-axis output S QW is as follows. S QR 1 S] xb sin (ω c-ω o)

A

[Cos {(ω c-2 ω υ) t + θ \} sin <oc-ω o) I]

2

A c, · b

- A R 1 and »ECTS

= A R] [sin {(2 ω c- 3 ω o) t + Θ I} ten si "{-ω ot + 0! }

.... (42) When divided high frequency components 2 w c through the quadrature demodulation Q-axis output S QR1 low-pass filter, the output S QRFI is

SD RF] = AD I [sin (-ωο t + β 1) ]

a one (4-

θ 1 = (^ 4- ,, ± _ ~ 44 ~) π

... - (43), and orthogonal [rho SK i.e. QP SK signal Q-axis output is generated in the same frequency as the desired channel.

In summary, as follows.

Output for the quadrature demodulated output upper local frequency of the I axis

. Ί the desired channel

S [n F = A R (cos ( -ωοί + 0k) J

. The upper channel S IR Fh = A K h [ cos (w + 0 h) J

. F side Cha ^ S IRF 1 = A R, [cos (-3ω 1) in the case of the lower station Metropolitan frequency output

SA R [cos (ωο t + O k) the desired channel human side channel

SILF h = AR h [cos (3ωο t + 9 h))

F-side channel

S = AS (- (ou t 9 I)]

LF 1 R 1 (CO

(4 4)

Q sleeves orthogonal recovery W output of

Output in the case of the upper local frequency

S QRF = eight R [sin (-ωυ t + β k) J desired channel

S QRF h = A Rh [sin (ωο 1 + β h)) upper channels

S QLFh = A R h [sin (-3 ω <, 1 + S h) ] mountain force when the lower channel lower local frequency

s QLF ~ a R Csin (wo t ten 0k)) the desired channel

S QRF I = AKI [sin ( 3 ω "1 + 0 1» ] upper channel

S QLF = A R! [Sin (-ω. I -I- Θ J)} lower channel

- ... from (4 5) the formula, as described above, I-axis side is seen that desired Channel to the quadrature demodulation circuit outputs of the two are included in common. Also, Q-axis side it can be seen that the desired channel in antiphase to the two orthogonal demodulation circuit outputs are included in common. Third embodiment of the present invention is realized on the basis of this principle.

Katachikuma of 赛施 4

Figure 4 shows the structure of a fourth embodiment of the present invention. 4, 1 is antenna receiving the reception signal, the 2 and 3 the first and second frequency converting circuit for receiving the reception signal, 4 has the upper and lower switch Yaneru adjacent to the radio carrier frequency received signals have thereby generating an intermediate frequency between a radio carrier frequency, the upper and lower upper frequency of the frequency of two waves as the first conversion frequency input of the frequency conversion circuit 2 outputs a lower frequency second frequency conversion local frequency signal generating circuit for outputting a conversion frequency input of the circuit 3, 9 a first bandpass filter for waveform-shaping the output of the first frequency converting circuit 2, 1 0 a first band-pass filter 9 the first a / D converter for converting the output of the a to the digital signal, 9 B is a second bandpass filter for waveform-shaping the output of the second frequency converting circuit 3, 1 0 B is the second band-pass de the output of the filter 9 B Second AZD converter for converting the Ijitaru signal, 6 D the first frequency offset circuit for removing a frequency offset component contained in the output of the first AZD converter 1 OA, 6 E second second frequency offset circuit, 7 C each frequency offset circuit the offset amount by performing fine frequency converter 6 D to remove the frequency offset contained in the output of AZD converter 1 0 B , offset frequency generating circuit you supplied to 6 E, 5 C common wave extracting a component present in common in both the outputs of the first frequency offset circuit 6 D and the second frequency offset circuit 6 E extraction circuit, 8 C is the filter you remove unnecessary frequency component remaining in an output of the common wave extracting circuit 5 C.

Next the operation of the receiving circuit of the fourth embodiment. This embodiment - as compared to the third embodiment, and the steps of performing a process and the frequency offset to perform the common wave extraction is interchanged. That is, by preceding the step of performing a frequency offset, a signal of the desired channel as it is the base signal can be expected to more stable extraction operations. Further, by digitizing the quadrature demodulation function becomes high accuracy, suitable for integration, leading to reduction in power consumption.

Or 5 of

Figure 5 shows a configuration of a reception circuit of the fifth embodiment of the present invention. And has it 5, 1 antenna for receiving a received signal, 1 1 and 1 2 are first and second quadrature demodulating circuits for receiving a received signal, 4 A is vertically adjacent to the radio carrier frequency received signals have along with generating an intermediate frequency between a radio carrier frequency with the channel, and outputs the upper frequency of the frequency of two waves above under the first orthogonal transformation for frequency input of the demodulation circuit 1 1, the lower frequency local frequency signal generating circuit for force out a second orthogonal transformation for frequency input of the demodulation circuit 1 2, 5 D first quadrature demodulating circuit 1 1 I output and the second quadrature demodulating circuit 1 2 I output a first common wave extracting circuit, 5 E is both polarity inversion output Q output of the first quadrature demodulating circuit 1 1 Q outputs and the second quadrature demodulating circuit 1 2 for extracting a component present in common in both second common wave extracting circuit for extracting a component present in common in, 6 F first First frequency offset circuit for removing a frequency O Fuse' preparative fraction remaining in I side output extracted with passing wave extracting circuit 5 D, 6 G is Q side output extracted in the second common wave extracting circuits 5 E removing frequency Ofuse' preparative fraction remaining in the second frequency offset circuit, 7 D are offset amount offset frequency generating supplied to the frequency offset circuit 6 F, 6 G performs a minute frequency conversion circuit, 8 0 the first filter for removing an unnecessary frequency component remaining in the output of the first frequency Ofuse' preparative circuit 6 F, 8 E is unnecessary frequency remaining in the output of the second frequency offset circuit 6 G a second filter for removing components.

Next the operation of the receiving circuit of the above fifth embodiment. This embodiment, also the in which embodying the present invention with respect to 4-value PSK i.e. QPSK in the digital modulation. According to the description by the aforementioned equation, the received signal obtained from the antenna 1 is supplied to the first quadrature demodulating circuit 1 1 and the second quadrature demodulating circuit 1 2, the local frequency signal generating circuit 4 A 2 one different, i.e. by separately supplying the upper and lower frequencies comparable to the median to the first quadrature demodulating circuit 1 1 and the second quadrature demodulating circuit 1 2 between the channels, the desired channel and the upper channel and the lower channel respectively, for the three signals produced four output signals. According to Equation deployment signal component present in common in the first straight 交復 regulating circuit 1 1 and the second quadrature demodulating circuit 1 2 is only signals of hope channel, I-axis side as a balanced component, Q axis side can be extracted as a differential component. Therefore, the equilibrium components of the I-axis side in a common wave extracting circuit 5 D, also by supplying a differential component of the Q axis side to the common wave extracting circuit 5 E, I axis of hope channel, Q-axis signal obtained It is. The output of the common wave extracting circuit 5 D, 5 E, ω. Since the frequency offset is left performs Oite minute frequency conversion to offset frequency generating circuit 7 D, the offset amount is removed in the frequency offset circuit 6 F, 6 G. Further supplies an unnecessary frequency component generated in this process was filtered out 8 D, 8 E, to the baseband signal processing section as a baseband signal. Between 6

6 shows the structure of a sixth embodiment of the present invention. 6, antenna 1 for receiving a reception signal, 1 1 and 1 2 are first and second quadrature demodulating circuits for receiving a received signal, 4 A and below the channel adjacent the radio carrier frequency received signals have the addition to produce an intermediate frequency between the radio carrier frequency having, upper and lower and upper frequency of the frequency of two waves output as the first conversion frequency input of the orthogonal demodulation circuit 1 1, the lower frequency second local frequency signal generating circuit for outputting a conversion frequency input of the orthogonal demodulation circuit 1 2, 6 H and 6 I are frequency offset contained in common in I outputs and Q outputs of the orthogonal demodulation circuit 1 1 and 1 2 first and second frequency offset circuits for removing minute, 7 E is offset amount offset frequency generating circuit that provides to each frequency offset circuit 6 H, 6 I performed a minute frequency conversion, 5 F is the first of A first common wave extracting circuit for extracting a component present in common in both the I outputs of the wave number offset circuit 6 H of I output and the second frequency offset circuit 6 I, 5 G is first frequency offset second common wave extracting circuit for extracting a component present in common in both the inversion output Q output of the circuit 6 H Q outputs and the second frequency offset circuit 6 I, 8 F and 8 G are each common a first and second filter for removing an unnecessary frequency component you remaining in the output of the wave extracting circuit 5 F and 5 G.

It will now be described receiving circuit operation of the embodiment of the sixth. This embodiment includes a step of performing a process and frequency Ofuse' you wish to common wave extraction as compared with the embodiment of the fifth are interchanged. That is, by preceding the step of performing a frequency offset, a signal of the desired channel as it is the base signal can be expected to more stable extraction operations.

Form of 卖掄 7

Figure 7 shows a configuration of a receiving circuit according to a seventh embodiment of the present invention. And have your 7, 1 antenna for receiving a received signal, 1 1 and 1 2 are first and second quadrature demodulating circuits for receiving a received signal, 4 A is vertically adjacent to the radio carrier frequency received signals have thereby generating an intermediate frequency between a radio carrier frequency with the the channel, and Kyoawase the upper frequency of the frequency of two waves above under the first orthogonal transformation for frequency input of the demodulation circuit 1 1, the lower frequency a local frequency signal generating circuit for test sheet as the second orthogonal transformation for frequency input of the demodulation circuit 1 2, 9 C and 9 D are respectively waveform shaping first quadrature demodulating circuit 1 1 I output and Q output first and second bandpass filter, 1 0 C and 1 0 D first and second AZ D converter for converting the output of the first and second band-pass filter 9 C, 9 D to Digitally Le signal vessels, 9 E and 9 F are the I output of the second orthogonal demodulation circuit 1 2 The third and fourth bandpass filters for each waveform shaping Q output, 1 0 E and 1 OF the third and converts the output of the third and fourth band-pass filter 9 E, 9 F into a digital signal 4 of AZD transducers, 5 H the first common wave extracting circuit for extracting a component present in common in the I outputs of the first contact and the third AZD converter 1 0 C and 1 0 E, 5 I Part second common wave extracting circuit you extracting a component present in common in both the polarity inverted output of Q output AZD converter 1 of 2 0 D Q output of the fourth AZD converter 1 0 E, 6 J Q is extracted with a first frequency offset circuit, 6 K second common wave extracting circuit 5 I to remove the frequency offset component remaining in I side output extracted by the first common wave extracting circuit 5 H second frequency offset circuit you remove frequency offset component remaining in the side output, 7 F is subjected to minute frequency conversion offsets Supplying Tsu preparative amounts to each frequency offset circuit 6 J, 6 K offset frequency generating circuit, 8 H first filter for removing an unnecessary frequency component remaining in the output of the first frequency offset circuit 6 J , 8 1 is a second filter for removing an unnecessary frequency component remaining in an output of the second frequency offset circuit 6 K.

Next the operation of the receiving circuit of the embodiment of the seventh. This embodiment, the fifth orthogonal demodulation circuit 1 1 Also the two as in the embodiment of, 1 2 of the output AZD transducer 1 0 (: quantized by ~ 1 OF, the using digital calculation action in the form equivalent to the implementation of 5, that is, to perform common wave extraction and the frequency offset and filter-ring. common wave extraction and filtering, using a digital filter technique, the frequency offset is used digital quadrature modulation It made possible.

Mano

Figure 8 shows a configuration of a receiving circuit of the eighth embodiment of the present invention. And has it 8, 1 antenna for receiving a received signal, 1 1 and 1 2 are first and second quadrature demodulating circuits for receiving a received signal, 4 A is vertically adjacent to the radio carrier frequency received signals have along with generating an intermediate frequency between a radio carrier frequency with the channel, and supplies the upper frequency of the frequency of two waves above under the first orthogonal transformation for frequency input of the demodulation circuit 1 1, the lower frequency local frequency signal generating circuit for test sheet as the second orthogonal transformation for frequency input of the demodulation circuit 1 2, 9 C and 9 D are first respectively waveform shaping first quadrature demodulating circuit 1 1 I output and Q output 1 and the second the bandpass filter, 1 0 C and 1 0 D the first and second a ZD conversion for converting the output of the first and second bands pass filters 9 C, 9 D to Digitally Le signal vessels, 9 E and 9 F are second orthogonal demodulation circuit 1 2 I output Third and fourth van Dobasu filter for each waveform shaping Q output, 1 0 E and 1 0 F third and converts the output of the third and fourth band-pass filter 9 E, 9 F into a digital signal fourth AZD converter, 6 L each AZD converter 1 0 Celsius to 1 oF frequency offset circuit for their respective remove frequency offset component remaining in I and Q outputs of, 7 G is very small offset frequency generating circuit for supplying offsets weight to each frequency offset circuit 6 L by performing frequency conversion, 5 J the first for extracting a component present in common in the I outputs of the frequency offset circuit 6 L common wave extracting circuit, 5 K second common wave extracting circuit for extracting a component present in common in both the inversion output Q and Q outputs of the frequency offset circuit 6 L, 8 J is first unnecessary frequency component remaining in the extracted I output Common wave extracting circuit 5 J of A first filter for removing, 8 K is a second filter for removing an unnecessary frequency component remaining in the Q output of the second common wave extracting circuit 5 K.

Next the operation of the receiving circuit of the embodiment of the eighth. This embodiment, as compared with the seventh embodiment, the steps of performing a process and the frequency offset to perform the common wave extraction is interchangeable. That is, by preceding the step of performing a frequency offset, a signal of the desired channel as it is the base signal, yo Ri stable extraction operations can be expected. Further, by digitizing the quadrature demodulation function becomes high accuracy, suitable for integration, leading to reduction in power consumption.

Between 9

Figure 9 shows a configuration of a receiving circuit of the ninth embodiment of the present invention. This embodiment, in place of the common wave extracting circuit 5 B of the third embodiment shown in FIG. 3, but using a correlator 1 3 for calculating a cross-correlation.

It was according to While connexion present embodiment, by using a correlator 1 3 Since Nau line by the digital filter technique common wave extraction, even if the polarity of the components contained in common have One Do different, the correlation coefficient only the amplitude polarity is reversed with the advantages ensured. Incidentally feature of this embodiment can be a fourth, equally applicable also to the seventh and eighth embodiment.

Or ¾ of 1 0

Figure 1 0 shows a configuration of a receiving circuit of the first 0 embodiment of the present invention. Embodiments of the present implementation, the frequency conversion circuit to enter the received signal of the antenna 1 or 3 in the first embodiment the first and only the frequency converting circuit 2 shown in FIG. 1, the first frequency conversion after the frequency conversion by the circuit 2, between channels from the local frequency signal generating circuit 4 B frequency 2 omega. The second frequency conversion circuit 1 5 supplied the corresponding frequency to obtain a frequency-converted output of the first frequency converting circuit 2 by the side who has failed to perform the frequency conversion, according to the Common wave extracting circuit 5 L it is obtained by the so that to ensure the two frequency-converted output required to the desired channel extraction.

Therefore, according to this embodiment, the first frequency conversion circuit 2 outputs the second frequency conversion circuitry 1 5, first and second frequency converting circuits 2 and 3 in the first embodiment to match the two outputs of the can processing carrier frequencies can be dispensed with only the pair of the high-frequency circuit, also reduce the power consumption not only space required for circuit.

Incidentally feature of this embodiment can be similarly applied to the second embodiment. Between 淪 1 1

Figure 1 1 shows a configuration of a receiving circuit of the first embodiment 1 of the present invention. Embodiments of the present implementation, the first frequency may quantizing means with a third frequency converter for inputting the received signal compared to the embodiment of the only the first frequency converting circuit 2 shown in FIG. 3 only the band pass filter 9 C and AZ D converter 1 0 C receives the output of the converter circuit 2, after AZ D conversion by the AZD converter 1 0 C, corresponding to the channel between the frequency 2 omega theta from a digital frequency generating circuit 1 7 by performing digital frequency conversion by the digital frequency converting circuit 1 6 which is supplied with frequency, with the frequency-converted output of the first side was not performed frequency conversion by the frequency conversion circuit 2, the common wave extracting circuits 5 it is obtained so as to ensure the two frequency conversion digital output required desired channel extraction by Micromax.

Therefore, according to this embodiment, the output of the first AZ D converter 1 0 output and digital frequency converting circuit and AZD converted by C 1 6 of the frequency converter circuit 2, first in the third implementation of the embodiment 1 and second to match the two outputs of the frequency converting circuit 2 and 3, the process of carrier frequency of the high frequency circuit can be dispensed with only one set, also reduce the power consumption not only space required circuit be able to.

Incidentally feature of the present embodiment, c ■ 1 2 can be applied similarly to the fourth embodiment

Figure 1 2 shows a configuration of a receiving circuit of the first and second embodiments of the present invention. Features of the embodiment of the present implementation, as compared with the fifth embodiment shown in FIG. 5, the quadrature demodulating means to enter the received signal and only one of the orthogonal demodulation circuit 1 1, the orthogonal demodulation circuit 1 1 of the two outputs, between channels from the local frequency signal generating circuit 4 B frequency 2 omega. By performing frequency conversion by the frequency conversion circuit 1 5 A supplied the corresponding frequency, the obtained frequency conversion output was not the quadrature demodulation side, first and second common wave extracting circuits 5 by N and 5 P is obtained so as to ensure two quadrature-demodulated outputs necessary for the desired channel extraction.

Therefore, according to the present embodiment, the orthogonal output of the demodulation circuit 1 1 and the frequency converter circuit 1 5 A, the two orthogonal fifth orthogonal demodulation circuit 1 1 and 1 2 first and second in the embodiment of to match the demodulated output, a high frequency circuit intended for the carrier frequency can be dispensed with only one set, it is possible to reduce also the power consumption not only space required for circuit.

Note that this embodiment can be similarly applied to the sixth embodiment. Form of 宥旃 ^ ΐ 3

Figure 1 3 shows a configuration of a receiving circuit of the first to third embodiments of the present invention. Features of the embodiment of the present implementation, the quantization means also of one as well as the seventh quadrature demodulating means for inputting a received signal as compared to the embodiment with only one quadrature demodulating circuit 1 1 shown in FIG. 7 Band-pass filter 9 D, 9 E and a / D converter 1 0 D, 1 0 £ and only after AZD conversion by the 80 transducers 1 0 D, 1 0 E, digital frequency generator 1 7 a or al The inter-channel frequency 2 ω. The corresponding frequency by performing a digital frequency conversion by the supplied digital frequency conversion circuits 1 6 Alpha was to obtain a frequency converted output has failed performed by Ri quadrature demodulation in quadrature demodulation circuit 1 first side, the first and it is obtained by the so that to ensure the two orthogonal demodulated output of the required desired channel extraction by a second common wave extracting circuit 5 Q, 5 R.

Therefore, according to this embodiment, the output of the orthogonal demodulation circuit 1 1 of the output AZ D converter 1 0 D, 1 0 E by AZD converted output and the digital frequency converting circuit 1 6 A is performed in the seventh in for matching the first and second quadrature demodulating circuits 1 1 and 1 2 of the two outputs of the form, the high-frequency circuit for processing the carrier frequency can be dispensed with only one set, only the space necessary for the circuit it is also possible to reduce the power consumption without. Note that this embodiment can be applied similarly to the eighth embodiment.

Of 掄 1

Figure 1 4 shows the configuration of a receiving circuit of the first to fourth embodiments of the present invention. This embodiment, in which about the improvement of the common wave extracting circuit in the first embodiment shown in FIG. 1 4, 1 antenna, 2 a first frequency converting circuit, a second frequency converting circuit 3, the local frequency signal generating circuit 4, the 5 common wave extracting circuit, 8 is a filter, first the same configuration as in the embodiment.

2 0 receiving input unit, 2 1 is an input line the output of the first frequency converting circuit 2 passes, 2 2 is an input line the output of the second frequency converting circuit 3 receives, 2 3 and 2 4 is an integration circuit which also serves as a respective input line 2 1, 2 2 through the first and second frequency converting circuit 3, 4-neck one bus' filter which receives the output of. 2 5 and 2 6 are first and second buffer amplifiers receive the output of, respectively it integrating circuit 2 3 Oyo partial circuit 2 4. 2 7 and 2 8 are first and second transformer receives the one end of the primary Koiru the respective outputs of the first and second buffer amplifiers 2 5 and 2 6. The other end of the primary coil of the first and second transformer 2 7, 2 8 AC-grounded to both the secondary coil is configured to connect the same polarity to each other in parallel, equal primary coil and lever of and it outputs a connection point 2 9 of one ends, the other end is grounded. 3 0 is a third Yuru衢 amplifiers connected to connection point 2 9 to the input, the output 3 1, is supplied to the subsequent frequency offset circuit 6 as the output of the common wave extracting circuit 5 .

Next, the operation of the common wave extracting circuit 5 in the embodiment of the first 4. From the first frequency converting circuit 2 and the second frequency converting circuit 3, a common wave e D of the desired wave signal component and adjacent channel wave signal component eu is obtained. Is Kemishi the adjacent channel wave signal component, component obtained from the first component and the second frequency conversion circuitry 3 obtained from the frequency converting circuit 2, since the center frequency different from the first frequency converting circuit 2 the components obtained from the e ui, a component obtained from the second frequency converting circuit 3 is expressed as e U2. That is, the first signal obtained from the frequency converting circuit 2 is a signal obtained from the e D + e ui a and the second frequency converting circuit 3 is e D + e U2.

The output of the first frequency converting circuit 2 and the second frequency converting circuit 3, may contain unwanted components having a frequency higher than these signals, these high frequency components mouth one path. the integration circuit 2 3 Oyo partial circuit 2 4 which also serves as a filter Ru is reduced. A signal e D + e ui the first obtained from the frequency converting circuit 2 which has passed through the integrator circuit 2 3 and integrator circuit 2 4, the signal e D + e U2 obtained from the second frequency converting circuit 3, their respective supplied to the corresponding buffer amplifier 2 5 and 2 6. Buffer amplifier 2 5 and 2 6, are to lower the output impedance. First signal e D + e ui obtained from frequency conversion circuit 2 through the buffer amplifier 2 5 and 2 6, the signal e D + e U2 obtained from the second frequency converting circuit 3, the transformer respectively It is supplied to the primary coil 2 7 and 2 8. Winding ratio of the secondary coil to the primary coil of the transformer 2 7 and 2 8 to 1. Thus, the secondary coil of the transformer 2 7 and 2 8, and the signal e D + e obtained from the first frequency converting circuits 2, respectively, the second frequency converting circuit 3 forces et resulting signal e D + e U2 is generated in response.

Here, the secondary coil of the transformer 2 7 and 2 8, since the terminal of the primary coil and the polarity to suit are connected in parallel, is obtained first frequency converting circuit 2 or we generated in the secondary coil a signal e D + e has, with respect to the common components i.e. the desired wave signal component e D of the respective components of the signal e D + e U2 obtained from the second frequency converting circuit 3, the secondary Koi Le output between There is no problem such as a collision, the signal is obtained at a terminal.

On the other hand, the first and component e obtained from the frequency converting circuit 2, a second frequency converting circuit 3 components obtained from e generated in the secondary coil of the transformer 2 8 generated in the secondary coil of the transformer 2 7 since the frequency to component is different from U2, mutually flows to the other side of the secondary coil. In this case, the input impedance of the transformer seen from the secondary coil is becomes equal to the output impedance of the signal source connected thereto respectively primary coils, the buffer amplifier 2 5 a each source as before mentioned, 2 6, since the output impedance is set too low, the component e m obtained from the first frequency converting circuit 2 for generating the components other than the common wave component, that the transformer 2 7 of the secondary coil, the transformer 2 resulting from component e U2 from the second frequency converting circuit 3 for generating the 8 secondary Koiru is reduced by the low-in pin one dance. - in general, Aya衝 amplifier can at implemented using emitter-follower by the transistor, when this is used, the output impedance of the buffer amplifier according 桔線 shown in FIG. 1 4 is less than several ohms. This principle will be described with reference to FIG 5. 1 5, transformer Yes constitutes from 2 winding L have L 2, a coil L 2 and the coil and the primary coil and the secondary coil.

Voltage and 鼋流 in each coil terminal is set as follows. That is, the voltage generated 2 1 1 I secondary蕙流the primary current, the罨圧generated between the primary coil L, the terminal between the terminal V ,, secondary coil L 2 and V 2. Further, the primary coil and the secondary co I Le L, and mutual Indakutansu between the M. In this case to connect the load Z to the secondary coil L 2, the input impedance Zin viewed from the primary coil L, the terminal is expressed by the following equation. ω is the angular frequency, it is assumed that the L, is L 2 M 2 holds.

Ζιη = Vi., (ΩΜ) 2 _

And, j cu and 2 + Z

.... (46) Here, when the load z is short-circuited, that is, when the z = o, the input impedance Zin becomes zero as follows. 〇

.... (4 7) then when the load Z in an open state, that is, when the Z = ∞, the input impedance Zin is, Zin = niv> L,

"Jw + Z Roh - tooth '

.... (48), and simply the impedance due to the inductance of only the primary coil.

Thus, the transformer 2 7, 28 - input impedance of the next coil is governed by the load of the secondary coil.

Returning to FIG. 1 4, Applying the principle according to FIG. 1 5, the transformer 2 7, each primary coil of 2 8, buffer amplifiers 25, 26 loads are shorted, the transformer 2 7, 28 of the secondary coil each input impedance will act in a state of zero (a short circuit state), 〖signal current in FIG. 1 4 U2 therefore, does not induce a voltage between the terminals of the secondary coil.

Normally, when driving transformer is intended to cover in signal flow for transformer, it generates magnetic flux proportional to the product of Indakutansu of the current and the primary coil in the magnetic core of transformer, time of the magnetic flux depending on the rate of change (derivative), in which voltage is induced in the secondary coil. Now, putting the potential induced in the secondary coil L 2 terminals and e 2, can be defined as follows. e, = M-.... (49) That is, in this case, the signal source driving the transformer than a 鼋流 source, its output impedance is ∞, so when viewed from the secondary coil side as described above, the those determined by Inpidansu by Indakutansu only the secondary coil. One feature of the shape of this embodiment anger, unlike the conventional method is that the mutual drive the transformer voltage source.

Next, briefly described integrator 2 3, 2 4 which also serves as a Robasu 'filter in Fig 4. Integrators 2 3, 2 4 becomes 1 / C or min proportionality factor when the Minorubun'yo i and C. However, if the input signal can be represented by a sine wave, the integral proportional coefficient to the angular frequency and ω exhibit l Z w C next frequency characteristics. This frequency characteristic is manifested differential proportionality coefficient in the differential output when the differential action i.e. inductance possessed transformer 2 7, 2 8 is L, the desired trans 2 7, 2 8 to offset the child frequency characteristic one in which was Awasemota. That is, to flatten the overall frequency characteristic up common wave extraction output from the first frequency converting circuit 2 and the second frequency converting circuit 3. When the frequency characteristic in the frequency range of the signal of interest to other circuit elements is flat Then, comprehensive frequency characteristic H from the first frequency converting circuit 2 and the second frequency converting circuit 3 to the common wave extraction output is is expressed by the following equation, is no longer frequency variable ω, that Do and flat.

Tooth

Η = X ω L =

Omega_〇 C

.... (5 0) As described above, according to this embodiment, in which is one common wave extracting circuit components of the receiving circuit, the prior art had a current source a signal source for driving the transformer rollers and voltage source and, Furthermore, the on to the parallel connection of the secondary coil between the transformer, the lever of the connection of the transformer secondary coil, with respect to common-mode signal is common wave, or reverse-phase It can only increase the trans-impedance to signals, for the non-common wave, become a load effect of the impedance close to zero, in the conventional most 2: the common wave and the non-common wave that could not be only 1 disparities in the circuit (ratio), according to the present embodiment least also can be a conventional doubled over, as possible out to obtain a removal action unprecedented.

Form of Gai施 ^ 1

Figure 1 6 shows a configuration of a receiving circuit of the first to fifth embodiments of the present invention. Embodiments of the present implementation is a modification of the embodiment of the first 4 shown in FIG. 1 4, the same elements are denoted by like numerals. Differs from the embodiments of the first 4, the input line 2 2 receiving an output of the input line 2 1 and the second frequency converting circuit 3 which receives the output of the first frequency variable circuit 2, respectively first It is connected to the first and second non-common wave signal removing circuits 4 6, 4 7, 1 of the input, first and second non-common wave signal removing circuit 4 6, 4 7, common output wave extracting circuit for supplying to 5 n. The output of the first frequency converting circuit 2 receiving Keru the input line 2 1 is input line 2 2 receiving an output of the second frequency converting circuit 3 also balancing monitoring circuit 4 which receives the respective output as the comparison signal 3 is Se' to. Output 3 1 a co Tsuha signal extraction circuit 5 n is supplied as a third input of the balanced monitoring circuit 4 3 also when connected to the frequency offset circuit 6. Another output of the common wave signal extracting circuit 5 n are respectively fed subjected to first and second non-common wave signal detecting circuits 4 1, 4 2. First and second non-common wave signal detecting circuits 41, 42 2, the output of the first frequency converting circuit 2 via an input line 2 1, and the second input line to the output of the frequency conversion circuit 3 receiving as a second input via the 2 2, and supplies its output with the output of the balanced monitoring circuit 4 3 to the first and second combining circuit 4 4, 4 5, respectively. Each of the output of the second combining circuit 4 4, 4 5 and the first contact, as a second input of the first and second non-common wave signal removing circuit 4 6, 4 7. Description of other structures is omitted except that generalizes the place that the 5 common wave extracting circuit in Fig. 1 4 As 5 n, is the same as FIG 4. Next, the operation of the receiving circuit of the present embodiment. Similar to FIG. 1 4, from the first frequency converting circuit 2 signal e D + e is supplied, the signal e D + e U2 is obtained from the second frequency converting circuit 3. Each output of the first frequency converting circuit 2 and the second frequency converting circuit 3 is supplied to the first and second non-common wave signal removing circuit 4 6, 4 7, respectively. Here, subtracting the second input to be described later, it is provided supplying its output to the common wave extracting circuit 5 n. These inputs to the common wave extracting circuit 5 n are basically the other to the first and the signal e D + of the frequency converting circuits 2 side, the signal of the second frequency converting circuit 3 side e D + e U2 not a record,. Therefore, in the common wave extracting circuit 5 n, as has been specifically described as a first 4 Common wave extracting circuit 5 in the embodiment of shown in FIG. 1 4, to extract the common wave signal e D. And only in the common wave extracting circuit 5 n, as is clear from the examples shown in FIGS. 1-4, but not completely remove the non-co Tsuha signal. That is, if the transformer 2 7 and the primary coil and the coupling degree of the secondary coil of the 8 in the common wave extracting circuit 5 n is incomplete, or the output impedance of the amplifier 2 5 or 2 6 for driving the transformer if Kere sufficiently low, removal capacity of the non-common wave component becomes insufficient. In this embodiment, once extracted using the feedback of the common wave signal output 3 1 a, the signal of the first frequency converting circuit 2 side e D + e or signals of the second frequency converting circuit 3 side e D + compared with the e U2. The comparator before non-common wave signal detecting circuit 4 1 first and second predicate to be 4 2.

The result is output through the first and second combining circuit 4 4, 4 5, the input line 2 1 receiving an output of the first frequency converting circuit 2, Keru receive the output of the second frequency converting circuit 3 modifications to the input signal from the input line 2 2. Non-common wave signal removing circuit 4 6 circuit of said first and second adding this correction to be 4 7. On the other hand, with respect to the common wave signal e D, and the signal strength of the first frequency converting circuit 2 side signal strength of the second frequency converting circuit 3 side, the input line receiving an output of the first frequency converting circuit 2 2 1 and, when it tries throughout at a stage obtained from the input line 2 2 Metropolitan receiving an output of the second frequency converting circuit 3 or to the common wave extracting circuit 5 n,, is not guaranteed to be equal at any time. Therefore, if there is a significant difference in the signal intensity, the difference is treated as non-common NamiNaru fraction, not utilized effectively even with sufficient signal strength to one. Therefore compared with the midpoint between the common wave extracting circuit 5 non-common wave signal removing circuit output and first and second n 4 6, 4 7 outputs, the result is subjected to equal offset the entire circuit it is effective to positive Osamu. Parts for realizing this feature is a balanced monitoring circuit 4 3 its output via the first and second combining circuit 4 4, 4 5, the first and second non-common wave signal removing circuit 4 6 respectively 4 7 is a path to return to.

Figure 1 7 is the embodiment of the first 5 shown in FIG. 1 6, which has more concrete, the same elements are denoted by like numerals.

Similar to FIG. 1 6, a first output of the frequency converting circuit 2 and the second output of the frequency converter circuit 3 via the input line 2 1, 2 2, first to the respective first input and it is supplied to the second differential amplifier 4 6 a, 4 7 a, the output of the first and second integrated circuit 2 3 which also serves as a low-pass' filter are supplied to the integrating circuit 2 4. The first and second integrated circuit 2 3, the output of the integrating circuit 2 4, supplied to the first and second buffer amplifier 2 5, 2 6. First and second buffer amplifier 2 5, 2 6 multiplied by feedback from the output to the negative input side. First and second buffer amplifier 2 5, 2 6, their respective supplies its output to one end of the primary coil of the transformer 2 7 and 2 8. The other end of the primary coil of the transformer 2 7 and 2 8 AC-grounded, the secondary coil is configured to connect the same polarity to each other in parallel, the connection point equal one ends of the primary Koiru and polarity 2 9 There serves as an output terminal, the other end is grounded, at least alternating basis. Connection point 2 9 of the secondary coil is connected to the third buffer amplifier 3 0, a third buffer amplifier 3 0 is multiplied by the feedback from the output to the negative input side. Output 3 1 a of the third buffer amplifier 3 0 is supplied to the frequency offset circuit 6, is connected to the positive input side of the third and fourth differential amplifier 4 1 a, 4 2 a , also connected to the positive input of the differential amplifier 5 0. The negative input of the third and fourth Sa觔 amplifier 4 1 a, 4 2 a includes an input line 2 1 receiving an output of the first frequency converting circuit 2, the output of the second frequency converting circuit 3 It is connected to the input line 2 2 undergo. Output of the fourth and fifth buffer amplifiers 4 8, 4 9, linked via two resistors R equal each 桔合 point is connected to the negative input terminal of the differential amplifier 5 0 8 that. The output of the third and fourth differential amplifier 4 1 a, 4 2 a is respectively connected to the positive input of the sixth and seventh differential amplifier 4 4 a, 4 5 a, Differential amplifier 4 4 a, 4 5 negative input of a is connected to the output of the differential amplifier 5 0 eighth. Sixth and the output of the seventh differential amplifier 4 4 a, 4 5 a is their respective respectively connected of the negative input terminal of the first and second differential amplifier 4 6 a, 4 7 a It is.

1 6 and corresponding Figure 1 7 is the non-common wave signal removing circuits 4 6 and 4 7, respectively first and second differential amplifier 4 6 a, 4 7 a, a common wave extracting circuit 5 n common wave extracting circuit 5 p, balancing monitoring circuit 4 3 fourth and fifth buffer amplifiers 4 8, 4 9 and the resistor R and a differential amplifier 5 0 balancing monitoring circuit 4 3 a, the non-common wave signal detecting circuit 4 1, 4 2 third and fourth differential amplifier 4 1 a, 4 2 a, combining circuit 4 4 and 4 5 pixels respectively sixth and seventh differential 增輻 unit 4 4 a It has become a and 4 5 a.

Next, the operation of the specific example of this embodiment. Similar to FIG. 1 6, from the first frequency converting circuit 2 signal e D + ew is supplied from the second frequency converting circuit 3 is a signal e D + e U2 is supplied. Each output of the first frequency converting circuit 2 and the second frequency converting circuit 3 is supplied to the positive input of the differential amplifier 4 6 a and 4 7 a for each non-common wave signal removing. Here, by subtracting the second input to be described later, and supplies its output to the common wave extracting circuit 5 p. In the common wave extracting circuit 5 p, lowpass • integrating circuit 2 3 or unwanted components of high frequency by the integrating circuit 2 4 which also serves as a filter is reduced, is supplied to the first and second buffer amplifier 2 5, 2 6 that. Buffer amplifier 2 5, 2 6 and the first signal e D + e ui frequency converting circuit 2 side, the transformer 2 7 supplied a signal e D + e U2 of the second frequency converting circuit 3 side and in 2 8, as described in the first 4 embodiment, removal residual simultaneously Hitomo Tsuha component when extracting the common wave signal e D is generated as shown in FIG 5. The secondary coil output of the transformer 2 7 and 2 8 containing residual of the non-common wave component is supplied to the positive input terminal of the differential amplifier 4 1 a and 4 2 a. Differential amplifier 4 1 a and 4 2 a is obtained via the input line 2 1, 2 2 the output of the output of the first frequency converting circuit 2 as a comparison signal and the second frequency converting circuit 3, substantially common wave the difference between the comparison signal and the common wave signal output 3 1 a, which is extracted as a component differential amplifier 4 4 a, 4 tell 5 a. On the other hand, the differential amplifier 4 4 a, 4 5 a signal of the first frequency converting circuit 2 side by feeding back the common wave extraction output 3 1 a to e D + e or the second frequency converting circuit 3 side signal, compared with the e D + e U2. The differential amplifier 4 1 a and 4 2 a is a circuit 4 1 and 4 2 out non-common wave signal detection described above. The comparison result is transmitted to the synthesizing circuit 4 4 and 4 5 a is a differential amplifier circuit 4 4 a, 4 5 positive input of a. On the other hand, a circuit gain to the common wave signal with respect to e D, the common wave signal output 3 1 a from the signal strength or the first frequency converting circuit 2 into the first frequency converting circuit 2 side output (2 1), the the circuit gain 2 from the output 2 2 of the signal intensity or the second frequency converting circuit 3 into the frequency converting circuit 3 side to the output 3 1 a is, in order to obtain high efficiency output if there is a difference, the after obtaining the first output of the frequency converter 2 (2 1) and the output of the second frequency converting circuit 3 a signal (2 2) in the buffer amplifier 4 8, 4 9, the common wave and the intermediate value by the resistor R an extraction output 3 1 a comparison Ri by the differential amplifier 5 0, the result in the first output of the frequency converter 2 (2 1) and the output of the second frequency converting circuit 3 (2 2) to add, convey to the differential amplifier circuit 4 4 a, 4 5 negative input of a a synthesizing circuit 4 4 or 4 5.

Differential amplifier 4 4 a, 4 5 the signals synthesized from a is supplied to the negative side input terminal of each differential amplifier circuit 4 6 a and 4 7 a, the first frequency converting circuit 2 output

(2 1) and the second correction output (2 2) of the frequency conversion circuit 3 is applied.

Thus, according to this embodiment, a function of removing non-common wave components remaining the common wave extraction output, with respect to the common wave signal e D, the signal strength or output entering the first frequency converting circuit 2 side the circuit gain from 2 1 to the output 3 1 a, between the circuit gain from the signal strength or output 2 2 enters the second frequency converting circuits 3 side to the output 3 1 a, in which case there is a difference it is possible to realize the function of removing the difference.

Or | ¾ of Ί fi

1 8 shows a configuration of a receiving circuit of the embodiment of the first 6 of the present invention. The communication method according to the present application of the subject is also QPSK, 1 4, 1 6, only one shown in FIG. 1 7 is in the form of c present embodiment that the phase can not only be extracted I-axis component in the same thing i.e. QPSK is obtained by so as to extract one 8 0 degree different signals to each other in phase, as shown in FIG. 1 8, takes 1 4 basically the same configuration, the 2 groups transformer secondary coil in which the polarity of connection to be opposite to each other. The structure omitted are the same as FIG. 1 4, except this. For action, the action that can be generated without phase signal with each other to interfere with the secondary side in FIG. 1. 4, the polarity of one secondary coil in FIG 8 is inverted, interference on reception Q signal is taken in the signal or QPSK with no reverse phase. Phase signal becomes opposite phase relationship to each other in the secondary coil side, become interfering mutually related, is attenuated.

Between 1 and 7

Figure 1 9 shows a configuration of a receiving circuit of the first to seventh embodiments of the present invention, the features of the phase-inverted signal shown in the first 6 of the embodiment, shown in FIGS. 1 6 and 1 7 and it is applied to a receiving circuit. Although improvement in equilibrium with removal of the non-common wave signal components of the phase signal is reduced in FIG. 1 7, in the present embodiment, the common wave signal is treated so as to obtain the effect of the same such as reverse phase signal .

Katachikuma of 卖旆 Ί 8

Figure 2 1 is a block diagram showing a configuration of a reception circuit in the embodiment of the first 8 of the present invention. In this embodiment, the system of the received adopts the same method and reception circuit according to a fifth embodiment of the present invention shown in FIG. Accordingly, the detailed description by referring to the reference numerals for the same components as Fig. 5 is omitted, and described below FIG 1 unique configuration. Local frequency signal generating circuit 4 A in the embodiment of the first 8, the desired wave carrier frequency signal generating source 3 2 to generate the desired wave carrier frequency signal, and the desired wave carrier frequency signal generating source 3 2 the offset frequency signal generating source 3 3 for generating the offset frequency signal are provided in parallel relationship, are hand stage phase-shifting the carrier frequency signal from the desired wave conveyed wave frequency signal generating source 3 2 (i.e. delay) the carrier frequency signal phase-shifting circuit 3 4, the offset frequency signal phase-shifting circuit 35 is a means for phase-shifting the offset frequency signal from the offset frequency signal generating source 3 3, the first quadrature modulator 3 6 and a, comprising a second quadrature modulator 3 6 b of. First quadrature modulator 3 6 a of the multiplication and O Fuse' preparative frequency signal generated by the desired wave carrier frequency signal generating source 3 desired wave carrier frequency signal generated by 2 and offset frequency signal generating source 3 3 a first multiplier 3 7 a to, after being phase-shifted processed by desired wave carrier frequency signal and the offset frequency signal phase-shifting circuit 35 after being phase-shifted processed by the carrier frequency signal phase-shifting circuits 3 4 second multiplier 3 8 a and the first multiplier 3 7 a multiplication result to the second multiplier 3 8 a multiplication result obtained by adding the negative offset side of multiplying the offset frequency signal and a local frequency (wc- ω ο) outputs a negative offset side station unit frequency output adder 5 1 Prefecture.

Second quadrature modulator 3 6 b of the offset after being phase-shifted processed by desired wave carrier frequency signal generating source 3 desired wave carrier frequency signal generated by 2 and offset frequency signal phase-shifting circuit 35 a third multiplier 3 7 b for multiplying the frequency signal, generated by the desired wave carrier frequency signal and the offset frequency signal generating source 3 3 after being phase-shifted processed by the carrier frequency signal phase-shifting circuit 3 4 a fourth multiplier 3 8 b for multiplying the offset frequency signal, a third multiplier 3 7 b of the multiplication result and the fourth multiplier 3 8 b multiplication result by adding the positive offset side local of and a frequency (wc + ω ο) outputs a positive offset side station unit frequency output adder 52. The output of the negative offset side local frequency outputting adder 5 1 whereas sent second orthogonal to the demodulation 1 2, the output of the positive offset side local frequency outputting adder 52 is first quadrature demodulator It has become a sending configurations to 1 1.

It will be described the operation principle and effect of the embodiment of the first 8. Desired wave carrier frequency signal omega c from the desired wave carrier wave frequency signal generating source 32 is supplied to the carrier frequency signal phase-shifting circuit 34; RZ2 only the phase is delayed. Offset frequency signal omega 0 from offset frequency signal onset Namagen 33 7τΖ2 only the phase is delayed is supplied to the offset frequency signal phase-shifting circuit 35. The first multiplier 3 7 a of the first quadrature modulator 36 multiplier 3 7 2 group constituting a a a, 38 a, desired wave carrier from the desired wave carrier frequency signal generating source 3 2 and offset frequency signal C 0 S ω 0 t from the frequency signal cos omega ct and offset frequency signal generating source 33 is input. Second multipliers 38 from the carrier frequency signal phase-shifting circuit 34 to a; ττΖ2 by a phase from the desired wave carrier frequency signal si nw ct and offset frequency signal phase-shifting circuit 35 whose phase is delayed by rZ2 is and offset frequency signal si η ω 0 t that has been delayed is input. As a result, the negative offset side local frequency outputting adder of the first quadrature modulator 36 a 5

As shown in the following formula in the first output, ω C- ω 0 becomes frequency appears.

coswct X coswot + s 1 η ω ct XS 1 n ω 0 t

= C 0 S (ω C- ω 0) t

The third multiplier 3 7 b of the second 2 groups constituting the quadrature modulator 36 b of the multiplier 3 7 b, 3 8 b, the desired wave carrier from the desired wave carrier frequency signal generating source 32 frequency signals C 0 S ω C t and at offset frequency signal phase-shifting circuit 35;: Bruno 2 and only offset phase is delayed frequency signal si eta 0 t is input. Fourth multipliers 38 b from the carrier frequency signal phase-shifting circuit 34 in; RZ2 only the desired wave carrier frequency signal sinwct phase is delayed and offset frequency signal phase-shifting circuit 3 from 5 [pi Bruno 2 phase by There delayed offset frequency signal C 0 S ω 0 c where t and is input as a result, the negative offset of up side local frequency outputting adder 5 2 output of the second quadrature modulator 3 6 b below as shown in equation, ω c + ω 0 becomes frequency.

COS w C t X s 1 Τϊ ω 0 t + S 1 η ω ct X c OS w O t

= Sin (ω c + ω o) t

Above As mentioned, it is clear that obtained as the output of the independent to generate complementary local oscillation frequency basic configuration of the present invention requires, according to the above embodiment.

Furthermore, it is not necessary to use a filter corresponding to each frequency, it is also clear that it is possible to cope without any problem be filed variable carrier frequency of the desired signal.

1 Q of

2 2 is a block diagram showing a configuration of a reception circuit in the embodiment of the first 9 of the present invention. This embodiment includes a phase shifter 2 group in order to obtain the fc + f 0 and fc one fo, to use the polarity inversion circuit 1 group quadrature modulator adder and 1 group 2 group of one in which the. It adopts the same method and reception circuit according to a fifth embodiment of the present invention shown in FIG. 5 as a method for the reception of this embodiment. Accordingly, the detailed description by referring to the reference numerals for the same components min and 5 will be omitted, and description 2 1 for own configuration below. Local frequency signal generating circuits 4 A in the embodiment of the first 9, parallel to the desired wave carrier frequency signal generating source 3 2 to generate the desired wave carrier frequency signal, and the desired wave carrier frequency signal generating source 3 2 the offset frequency signal generating source 3 3 for generating the offset frequency signal provided relationship, the carrier frequency signal phase-shifting circuit is a means for phase-shifting the carrier frequency signal from the desired wave carrier frequency signal generating source 3 2 3 4 and, offset frequency signal and the offset frequency signal phase-shifting circuit 35 of the offset frequency signal is a means for phase shift from the source 3 3, a quadrature modulator 3 6 a, polarity inverting circuit 5 3 When made and a positive offset side local frequency outputting adder 5 4. Quadrature modulator 3 6 a, the above in the embodiment of the first 8 has a first quadrature modulator with the same configuration, the desired wave carrier frequency generated by the desired wave carrier frequency signal generating source 3 2 desired after being phase-shifted processed by a first multiplier 3 7 a and the carrier frequency signal phase-shifting circuit 3 4 for multiplying the offset frequency signal generated by the signal and offset frequency signal generating source 3 3 a second multiplier 3 8 a for multiplying the offset frequency signal after being phase-shifted treated by wave carrier frequency signal and offset frequency signal phase-shifting circuit 35, multiplying the first multiplier 3 7 a and a result and a second multiplier 3 8 a multiplication result and adding a negative offset side local frequency (wc- ω ο) outputs a negative offset side local frequency outputting adder 5 1 Metropolitan . The polarity inverting circuit 3 to the polarity reversal process the output of the second multiplier 3 8 a. The positive offset side local frequency outputting adder 5 4 adds the polarity inversion output by the multiplication result output and the polarity inversion circuit 3 of the first multiplier 3 7 a, positive offset side local frequency (wc + and it outputs the ω ο). The output of the negative offset side local frequency outputting adder 5 1 whereas sent second quadrature to a demodulator 1 2, the output of the positive offset side local frequency outputting adder 5 4 orthogonal first and it has a configuration that is sent to the demodulation 1 1. It will be described the operation principle and effect of the embodiment of the first 9. Desired wave carrier frequency signal omega c from the desired wave carrier wave frequency signal generating source 3 2 is supplied to the carrier frequency signal phase-shifting circuit 3 4; r Z 2 only the phase is delayed. Offset frequency signal onset Namagen 3 offset frequency signal omega 0 from 3 is supplied to the offset frequency signal phase-shifting circuit 35 with 7Γ / 2 phase by the delay.

Quadrature modulator 3 6 multiplier 3 7 2 groups constituting the a a, 3 8 to the first multiplier 3 7 a of a, desired wave carrier frequency from the desired wave carrier frequency signal generating source 3 2 and the signal C 0 S ω ct and offset frequency signal generating source 3 offset frequency signal c 0 s ω 0 t from 3 inputted. Second multiplier 3 8 from the carrier frequency signal phase-shifting circuit 3 4 in a; rZ 2 only the desired wave carrier frequency signal sinwct phase is delayed and offset frequency signal phase-shifting circuit 3 only ττΖ2 from 5 phase There and offset frequency signal si η ω 0 t that has been delayed is input. As a result, as shown in the following equation for the negative off the output of the set side local frequency outputting adder 5 1 of the quadrature modulator 3 6 a, 0 / (; -0; 0 becomes the frequency obtained.

coswct X coswot + s 1 η ω ct XS 1 n> 0 t

- COS (ω C - ω O) t

Some of the output of the quadrature modulator 3 6 multiplier 3 7 2 groups constituting the a a, 3 8 a second multiplier 3 8 a of the output of which is supplied to the 梗性 inverting circuit 53, the inverted output is generated through a frequency at which represented by the following formulas and input to the first multiplier 3 7 a positive offset side local frequency outputting adder 5 4 together with the output of.

cosjct X sinwot -f (- 1) sinwct X cos ^ ot

= C 0 S (ω C + ω 0) t

Above mentioned manner, it is clear that obtained as output of the basic configuration generates a phase complementary type local oscillation frequency required independent accordance Invite present invention to the above embodiment. Furthermore, it is not necessary to use a filter corresponding to each frequency, also apparent der to be able to correspond without problems be variable carrier frequency of the desired signal

Ό o

Form of Gai施 ^ 2 0

Figure 2 3 is a block diagram showing the configuration of a receiving circuit in the second 0 embodiment of the present invention. This embodiment includes a phase shifter 2 group in order to obtain the fc + f 0 and fc one f 0,

1 group quadrature modulator and the 2 groups adders and those as adapted to use the polarity inversion circuit 1 group. It adopts the same method and reception circuit according to a fifth embodiment of the present invention shown in FIG. 5 in the form Shin method of this embodiment. Accordingly, the detailed description by referring to the figures For the same components as in FIG. 5 will be omitted, and description below with 2 3 unique configuration. The local frequency signal generating circuit 4 A in the embodiment of the second zero, the desired wave carrier frequency signal generating source 3 2 to generate the desired wave carrier frequency signal, in parallel with the desired wave carrier frequency signal generating source 3 2 the offset frequency signal generating source 3 3 for generating the offset frequency signal provided relationship, the carrier frequency signal phase-shifting circuit 3 4 is a means for phase-shifting the carrier frequency signal from the desired wave carrier frequency signal generating source 3 2 When a offset frequency signal phase-shifting circuit 35 is means for Ru phase shifted to offset frequency signal from the offset frequency signal generating source 3 3, a quadrature modulator 3 6 a, the polarity inversion circuit 5 3 becomes a positive offset side local frequency outputting adder 5 4. Quadrature modulator 3 6 a, the above in the embodiment of the first 8 has a first quadrature modulator with the same configuration, the desired wave carrier frequency generated by the desired wave carrier frequency signal generating source 3 2 desired after being phase-shifted processed by a first multiplier 3 7 a and the carrier frequency signal phase-shifting circuit 3 4 for multiplying the offset frequency signal generated by the signal and offset frequency signal generating source 3 3 a second multiplier 3 8 a for multiplying the offset frequency signal after being phase-shifted treated by wave carrier frequency signal and offset frequency signal phase-shifting circuit 35, multiplying the first multiplier 3 7 a and a result and a second multiplier 3 8 a multiplication result and adding a negative offset side local frequency (we- ω ο) outputs a negative offset side local frequency outputting adder 5 1 Metropolitan .

The polarity inverting circuit 3 to the polarity reversal process the output of the second multiplier 3 8 a. The positive offset side local frequency outputting adder 5 4 adds the polarity-inverted output of the first multiplier 3 7 multiplication result by a output and the polarity inversion circuit 3, the positive offset side local frequency

And it outputs the (wc + ω θ). Then, the contrast to the embodiment of the first 9, the output of the negative offsets side local frequency outputting adder 5 1 hand be sent first orthogonal to the demodulation 1 1, the positive offset side local frequency the output of the output adder 5 4 has a structure to be subjected sent to the second quadrature demodulating 1 2. It will be described the operation principle and effect of the embodiment of the second 0. Desired wave carrier frequency signal omega c from the desired wave carrier frequency signal generating source 32 is supplied to the carrier frequency signal phase-shifting circuit 3 4; ΓΖ2 only phase power, 'it is delayed. Offset frequency signal omega 0 from offset frequency signal generating source 33 is offset frequency signal phase-shifting circuits 3 are supplied to 5 ΤΓΖ2 only the phase is delayed.

Quadrature modulator 3 6 multiplier 3 7 2 groups constituting the a a, 38 to the first multiplier 3 7 a of a, desired wave carrier frequency signal c from the desired wave carrier frequency signal generating source 32 0 s and omega ct and offset frequency signal generating source from 33 offset frequency signal c 0 s ω 0 t is input. Second multiplier 38 a from the carrier frequency signal phase-shifting circuit 34 desired wave carrier frequency signal Tautauzeta 2 by a phase is delayed from the si eta omega ct and offset frequency signal phase-shifting circuit 35 in; RZ2 only phase There and offset frequency signals si ηω 0 t which is delayed is input. As a result, as shown in the following equation to output a negative off-set side local frequency outputting adder 5 1 of the quadrature modulator 3 6 a, - ω θ becomes frequency.

coswct X coswot + si nw ct X si nw ot

= C 0 S (ω C - ω θ) t

Some of the output of the quadrature modulator 3 6 multiplier 3 7 2 groups constituting the a a, 38 a second multiplier 3 8 a of the output of which is supplied to the polarity inverting circuit 53, the inverted output as shown in the following formula was input to the first multiplier 3 7 a output with the positive offset side local frequency outputting adder 54 of, for generating ω c + ω 0 becomes frequency.

coswct X sinwot + (- 1) sinwct X coswot

= C 0 S (ω C + ω 0) t

Above mentioned manner, it is clear that obtained as output of the basic configuration generates a phase complementary type local oscillation frequency required independent accordance Invite present invention to the above embodiment.

Furthermore, it is not necessary to use a filter corresponding to a respective frequency, c or of it is also clear that it is possible to cope without any problem be filed variable carrier frequency of the desired signal 1

Figure 2 4 is a block diagram showing the configuration of a receiving circuit in the second embodiment 1 of the present invention. This embodiment is intended primarily in a communication system of a digital modulation scheme having a plurality of channels, to reduce the power of the receiving system, achieving that simplifies the circuitry, reduces the power consumption. 2 4, reference numeral 6 1 first the first data input line to de one data is input the received signal, 6 2 the first data input line obtained by the frequency conversion circuitry or orthogonal demodulation circuit first Fourier transformer for performing a full one Fourier transform on the signal input from the 6 1, 6 3 denotes a first Fourier transform output obtained depending on the first Fourier transformer 6 2. The 6 4 second de one data input line data of the second received signal obtained by the frequency converting circuit or the quadrature demodulating circuit are input, 6 5 is inputted from the second data input line 6 4 second Fourier transformer for performing Fourier transform on signals, 6 6 represents a second Fourier transform output obtained by the second Fourier transformer 6 5.

6 7 correlator for calculating a correlation coefficient received for each frequency the output of the respective frequency components of the first and second Fourier transformer 6 2, 6 5, 6 8 the first and second Fourier transform vessel 6 2, 6 5 adder for adding outputs of, 6-9 output of the correlator 6 7, 7 0 the weighting function device for weighting receiving correlator output 6 9 obtained, 7 1 adder 6 8 of the adder output and the weighting function unit 7 0 and the output of the weighting value multipliers for multiplying, 7 2 post-processing circuit for performing a post-treatment of the multiplication operation by the weighting value multiplier 7 1, 7 3 weighting value multiplier vessel 71 output is the inverse Fourier transformer input produced is workup, 7 4 inverse Fourier transformer for performing inverse full one Rye conversion process receives the inverse full one Rye transducer input, 7 5 reverse is the Fourier transform output.

It will be described the operation principle and operation of the second 1 embodiment. In the first to the embodiment of the first 3 mentioned above, either provided with a first frequency converting circuit 2 and the second frequency converting circuit 3, the first quadrature demodulating circuit 1 1 and the second quadrature demodulator or comprising a circuit, or also has one of the basic configuration and an orthogonal modulator circuit of the frequency converter and 1 group 1 group. And a first received signal and second received signal obtained by the receiving circuit when receiving operation by this arrangement. In this embodiment, the first reception signal is represented by X (t), is input to the first data input line 6 1.

Second received signal is expressed by y (t), is input to the second data input line 6 4. First received signal X (t) is first Fourier transform output 6 3 are Fourier transform processing here enter first the Fourier transformer 6 2 are obtained we entered in the first data input line 6 1 . The second received signal y (t) is a second Fourier transform output 6 6 is Fourier transform processing where input to the second Fourier transformer 6 5 is obtained. These first contact and second Fourier transform processing in the Fourier transformer 6 2, 6 5, the data of the first and second received signals over the filled force is converted into frequency axis data from more hours axis information that.

First and second Fourier transform output 6 3, 6 5 is taken into the correlator 6 7, correlator 6 7 This Each frequency component of the first and second Fourier transform output 6 3, 6 6 the calculated correlation coefficients received for each frequency. On the other hand, the first and second full one Fourier transform output 6 3, 6 5, to being calculated a correlation coefficient by the correlator 6 7 are caused to enter separately from the adder 6 8, the adder 6 both Fourier-transformed output signals are added by 8. Moreover, the correlation coefficient output by the correlator 6 7, weighting processing here is input to only weighting function unit 7 0 is performed. Then, the weighting value multipliers 71 multiplies the amount output signal by receiving an output of the adder and output the weighting function unit 7 0 of the adder 6 8. Then performs a post-multiplication operation post-processing circuit 7 2 by the weighting value multiplier 71, an inverse Fourier transformer input 7 3 generated the post-processing is performed inverse Fourier transformer 7 4 received by by performing inverse Fourier transform processing, returns the processing data in the time axis information from the frequency axis information, results desired wave extraction as the inverse Fourier transform output 7 5.

Next will be described the theory of principles the desired wave is extracted. First, the management of the I & suppression action against non-desired wave of If you do not want to incoming desired wave. After the non-desired wave (existing temporally independent between the two signal system) were synchronously added, the amplitude component R times (R is the correlation coefficient) is. The 演箕 type of correlator is shown below.

X ten y

Addition

Correlation coefficient

fi Mizuke R> 0 in f (R) = R R <In the 0 + (R) = 0

.... (5 1) power P N of the non-desired wave in each averaging window for the correlation coefficient calculation. There When Ru constant value der, power P N of the process output is expressed by the following equation.

P N = (R 2 P N0 ) Z2

here,

P N. : Non-desired wave power

R: correlation coefficient

It is.

The correlation coefficient R is so is calculated using a finite averaging window, the statistical error Ji raw, do not match the values ​​of the true correlation coefficient. In Samburu number N independent Samburu performs calculation of R, From It should true correlation coefficient is 0, the distribution of R is expressed by the probability density function of the following equation. On the distribution of R

Probability density 88 »g (R): (IR 2)

(

The average power of the processing output from (52) above is represented by P N the following equation,

The average power PN two

.... (53) Here, the averaging window of the correlation coefficient calculated as a square window of length Tc, when the length of the hamming window in carrying out the Fourier Transformations and TF, averaging windows the number N of independent support tumble present in the becomes the following equation. N = (T c) / (TF)

Therefore, the processing output of the non-desired wave in a case where the number N is large can be expressed by the following equation.

PN = l nim Pn. o TF

∞ 4ίΝ- |) 4N T c

- ... (54) i.e., proportional to 1 Zn.

Next, we describe inhibitory effect on non-desired wave if you may have been reached the desired wave or * ¾!. When subjected to带域divided into signal components, can be further divided into desired signal power? Not exist with existing segment interval. The amplitude of the k-th 带域 component containing the desired wave component is outputted by multiplying the R (k) correlation coefficient for that band. R (k) can be expressed by the following equation. Containing a rare a wave component

In 挤城 of k 餮目

Phase "coefficient R (k> = p (k % p (k) ~

SO No

IJ o (k): of the desired signal component) th power p (k in the mean time W of the frequency component of): HiNozomi power at 1 Hitoshiji IW內of use wavenumber components of the eye of the ¾ wave component ^. ... (55) and閱to k, P so (k), P NO (k) a constant value P so, P N. When, the suppression effect of the undesired wave can be obtained by the following equation. Dilute a¾ Bruno HiNozomi a wave ratio Bruno 丄 output signal - p SOT O) rare Sl wave input Shinhaha / ft desired wave ratio 2 4 (N> 1) Pso However, F3 «(contains the desired signal component挤城 number are) Bruno (all 挤城 number)

. ... (56) by this formula, the desired signal component force? The fewer the number of bands that contains, it can be seen that a large improvement in the desired wave Roh undesired wave ratio. Therefore, according to this embodiment, by using a statistical error of the correlation coefficient calculated by the finite averaging window or mean time, the undesired wave is the first received signal and second received signal there temporally independent between the two signal system, utilizing the nature that can be handled as an unbalanced signal, it is possible to realize the suppression function for the non-desired wave.

Or 2?. FIGS. 25 to 33 are views for explaining the construction and operating principle of the receiving circuit in the twenty-second embodiment of the present invention. The Katachi憨 of each embodiment described so far is a method corresponding to multiplexing digital modulation scheme such as the quadrature modulated signal. In this method, the orthogonal demodulator is required 2 groups can not be said the best is to simplify 髦Ka reduction and apparatus. In the form of the implementation in which advanced improvements in this regard. Therefore, in the present embodiment to 1 group quadrature demodulator. Therefore, to prevent aliasing of the frequency axis by performing a second sampling in AZD converter, to generate a de-digital signal processing originally required missing side of the complementary local oscillation frequency by quadrature demodulated output by the AZD conversion output We are in the configuration, such as.

2 5 Ru block diagram showing a configuration of a receiving circuit according to the second second embodiments. 2 5, 1 antenna for receiving a received signal, 9 6 receive band filter is a bandpass filter for waveform-shaping a received signal at a predetermined frequency band (van Dobasufi filter), 1 1 and inputs the received signal quadrature demodulator 4 local frequency signal generating circuit, 8 the first low-pass filter 6 to Katsu Bok a high-frequency band of one output signal from the quadrature demodulator 1 1, 8 7 from the quadrature demodulator 1 1 second low-pass filter to cut high-frequency band of the other output signal, 9 0 first AZD converter 9 1 second low-pass filter 8 7 to AZD converts the output of the first low-pass filter 8 6 second AZD converter for converting the output of AZD, 9 2 the ability to generate a frequency above the clock that corresponds to the bandwidth with the first and second AZ D converter 9 0, 9 1 in the received signal and, delay pulse train to a sampling clock pulse train A function of adding, sampling signal generating source having a function of providing a delayed pulse train as Sanburinguku locking pulse train as said first and second AZD converter 9 0, 9 1 of the sampling pulse, 9 3 the first and a second AZD converter 9 0, 9 calculator for extracting a received channel signal desired from the first digital output data.

In this embodiment, the quadrature demodulator 1 1 includes first and second multipliers 7 8, 7 9 enter the received signal from the reception bandpass filter 9 6 performs frequency conversion, the local frequency signal generating and a frequency offset circuit 9 8 for inputting a local oscillation frequency signal from the circuit 4 to the second multiplier 7 9 by offset, Nau frequency conversion processing on the received signal.

It will be described the operation principle and operation of the second second embodiments. In Fig. 2 5, the received signal received by the antenna 1 after becoming 带域 the signal group shall be the subject through the receiving 带域 filter 96, I-axis component and the Q-axis component by the quadrature demodulator 1 1 door is extracted. This signal is input high after an unnecessary frequency component of the band has been removed, the first and second in AZD converter 90, 9 1 in the first and second mouth one pass filters 86, 87.

In the A / D conversion operation in AZD converter 90, 91, performs the Sambu ring operation sampling signal from sampling signal generating source 20 is supplied to the AZD converter 90, 9 1. Then, digital data obtained through this sampling operation is a digital signal processing is performed is sent to the arithmetic unit 93, the baseband output. Here, A / D converter 90, 91 the normal sampling line sparse in, generates an alias by sampling, becomes impossible then scheduled to have digital frequency conversion.

Figure 26 is a view for explaining the manner in which results was performed sampling alias or * occur in AZD converter 90, 91. First the signal is supplied as shown in FIG. 26 (A), becomes a signal high frequency component is removed as shown in FIG. 26 (B) When passing the signal into the mouth one pass filters. The Alias ​​As shown in AZD converted output of FIG 26 (C) is sampled the signal is Kiwamusei. Therefore, in this embodiment, provided with means for preventing wrapping on the frequency axis and summer and Moto generating the E Iriasu. It will be described below in the formula.

Now, by placing the carrier frequency fc, the QPSK sub-carrier frequency and ί o, QP SK radio signal, fRP-Aft) cos (2xifc + -fo) -t + Pml

= A (f) cos {2 «(fc4fo) t + 0a (t) l + Art) sin l2xffc + f) -t + Θίί +) Ι

(57) and it can be expressed.

Here, the phase signal (t) is,

Θ (t) = 0, ±; r 2, π

It is. Consider the situation in a multi-channel communication system, such as P DC. Figure 27 is a diagram illustrating a modeled situation (arrangement state) of the reception channel in a multi-channel communication system. Now, as shown in Figure 27, each channel is assumed to on the frequency axis, are arranged at equal intervals. Further, the channel spacing frequency and ί b. When it is assumed that N channels enters through the input filter of the receiver, the input signal and f w,

fiN »JL> A iit) cos l2re (fc + i b + fo) t + Paid) I + £ 'Aid) sin" ffc + iXflHfo) t + 9 ai (f) \

■ s0

(58) In this case, if each channel is in contact,

2 f 0 = fb

Since the,

fiN-Σ Aitt) cos (2 «ifc- [2 ^ 1 J fo) t + Θ ai (t))

i = 0

+ £ Aid) sin (2 t (c + I2i + |] f) † + ββϊ (1) Ι

.. It can be described as (59), subjected to frequency conversion as direct conversion to the signal group. When the frequency of the signal obtained by performing general frequency conversion to lower only the frequency is f De, this f TC can be expressed by the following equation. DC- l XfUO

= Ai (t) cos l2 «(fc-fto + (2i ^ U fo) + +

■ + ^ Aift) sin (2n (fc-fLO + [2i + l] fu) t + 0aift)) + £ Ai (†) cos {2n (fc + fL0 + i + i} fo) t + ί ai (t) )

Σ Ai (t) sin (2rr (fc + fLO + (2i4l) fo) t + β aift)}

Isfl

In ... (60) where two terms in the second half the frequency is increased to twice the RF frequency, usually easily pass ajh the frequency characteristics of the circuit. Therefore, the frequency f De after being frequency converted no problem expressed by the following equation.

foc = fmXfLO

A i (t) cos (27i (fc - fljO + i2i4l) o) t + fla t))

+ £ Ai (t) sin (27iffc-fLO + f2i + U fo) + + e aift))

... - (61) where, in the channel may what f ci ^ is negative. It is to say the frequency becomes negative, this is that the Q-axis of the polarity of the phase rotating plane of the QPSK signal you inversion, which i.e. means that the rotation of the QP SK signal is reversed not only are you. Therefore, it does not mean that the polarity of the frequency signal disappears just because a negative.

Then fed to AZD converter 90, 9 1 in order to digitize the signal.

AZD converter 90, 91, in this case, its output is equivalent to sampling becomes what is discretized. Discretization process, signals before and after treatment is not necessarily one-to-one correspondence. Alias ​​occurs when many. Therefore, the force suppressing the A / D conversion signal so as not to generate an alias lower than 1 2 of AZD conversion frequency or the A / D conversion a plurality of the converted signal sequence, (higher order sampling).

Here, consider the physical meaning of the negative frequency, thereby opening the developing using a negative area of ​​the frequency axis. The following equation is obtained by the carrier of the QP SK to negative frequencies. A negative signal to move the mathematically location, time, are arranged expressions instead come 誊 to 閲数 value. Incidentally, in the formula, the uppermost portion represents a negative frequency, part of the second stage represents a negative time axis, the bottom portion represents a negative function.f RF = A (†) cos I2ni-fc) t + 0a (1)} + A (l) sin 12 π (-fc) t + β a (t) l

= A (-t) cos I2 ^ fc (-t) + fl «(- t) l + A (-f) si" I2n c <-t> + 5a (-t))

= Art) cos (lnfct + flatt)} -A (t) sin (2 «* ct 4- 0 a (t) l.... (62) 28 A / D converter with a negative frequency domain it is a diagram representing the output. physical meaning of the negative region of the frequency is not different from the behavior of the positive frequency domain as long as seen from the above equation. However, it is expressed as one fc has dealt with fc as positive means that the direction of the traveling direction or Mi鑲 on the frequency axis is positive ^. that means that the rotation on the frequency circumference is reversed direction, the circumference that frequency zero may be seen in a state of jammed or above the throat this. since the position 0 a QPSK operation behaves of (t) is carried out, indicated by the spectrum will exhibit a bandwidth of QPSK information. for example If, RF signal and the first and second multipliers 9 4, 9 5 added mouth - rotation direction at the respective frequency circles in the frequency conversion from the local signal Fight for is considered to have been made. In the frequency lowered in accordance with each of which conflict with attempts to give the rotation of Gyakukata direction. Frequency approaches zero with one another, rotation sp e one de fell, finally rotation is stopped. further forward and reverse rotation speed of the local signal side overcomes the rotational direction is reversed.

From the above, in the theoretical development here, a signal spectrum that results due frequency conversion is negative frequency region, generally in the positive region as expressed Orikaeshi representation Wasezu, the frequency axis and it is expressed as continuous in the positive and negative directions. Its purpose is to possible representation of having the information signal itself, such as QPSK signal composed of a plurality of axes. Conventionally representation limit the frequency domain into positive region, it will be thus narrowing the frequency space by folding the spectrum, and summer to lose one degree of freedom of the expression.

On the other hand, it is necessary to decompose to a form that can be identified by orthogonal space that forms the phase space as a function of the signal itself time or phase. 2 9; shows a method for decomposing a r Z 2 of utilizing cosine signal components by function a phase difference (c 0 s function) and the spot 交成 partial sine function (sin function). In this figure, (t) is positive and negative control of the frequency domain because it is expressed by cos function number (a number even function) not receiving. i Q (t) is frequency because it is expressed by sin function codes of the function value is inverted in the negative region (an odd function).

By using two approaches described above, generally it emerged from conventional scan Bae-vector arranged that in the crease of the conversion frequency (or sampling frequency) fs in the A / D converter fold back the high frequency side below the conversion frequency fs, convert It will be represented as it is the Ime Jisupeku torr or more frequency fs.

Next, AZD converts the two signals to be orthogonal. Frequency domain of the two orthogonal signals is near base one spanned, conversion rate may be at least twice the target signal by sampling theorem Shannon. 3 0 is a diagram showing an example of the orthogonal Sambu ring in the case of AZD converting the two signals to be orthogonal, among the configuration the configuration shown in FIG. 3 0 shown in FIG. 2 5, receive band-pass filter 9 6 below the first and second AZD converter 9 0, up to 9 1 configuration is a representation while revealed signals flowing at each site. In Figure 3 0, T s represents a sampling period. In this AZD converting operation, the sampling frequency omega S is

ω S≥Wo

In (t), to form a pair of sample columns of f Q (t). Signal f In this way

(T) is because it is sampled as a point on the IQ plane can be ensured information such as the rotation direction of the signal can be digitized.

Here, considering the frequency offset is a gist of the present embodiment, the configuration of FIG. 3 0 is as shown in FIG 1. In other words, the local frequency from ω C ω C - and omega 0, is omega 0 becomes offset frequency on the output signal so as to remain. AZD converter 9 0, 9 1 to supply the signal f, and the frequency omega 0 and the frequency offset omega 0 is the transmission rate of the (alpha> 0 t) and (omega 0 t) and the baseband signal because it contains, it appears to have a frequency 带域 width of 3 omega 0 around the carrier frequency for the roll-off factor 0.5 less baseband transmission. Therefore, the frequency of the sampling clock is necessary and sufficient long 6 omega 0 or more, the signal f (t) since the service Nburingu secured information such as the rotation direction of the signal as a point on the IQ quadrature plane, and it digitized sign continuity is preserved in the frequency axis.

Therefore, it is possible to also positive or negative frequency-converted digital signal output of the receiving circuit by the digital signal processing. That is, the signal by performing digital甩波number Hen换minus 2 omega theta and (cot) f Q (ω θ t) from the signal f, (~ ω Ο t) and f Q - obtaining the (ω θ t) it becomes possible. This 桔果, according to the above how, orthogonal condensate 購器 the by complementary of local onset wave number, will be need in only one, vanishing ¾ «force can Miss hydride in a high frequency circuit of about 1/2 also 鞋滅It is. Figure 32 is a diagram illustrating another sampling operation different from the quadrature sampling in the case of performing AZD varying 换動 operation described above (FIG. 30, 3 1). This is an application of the sampling is referred to as secondary sampling Shannon. In this sampling method, as shown in FIG. 32, connecting signals down a high-frequency input signal f (t) to pace band frequency conversion fb (t) to two systems of the A / D converter. When employing the configuration such as this, an equal sampling pulse time between ffi as shown in Figure 33 as a variable 换用 pulse (sampling pulse), the delay time is obtained as a pulse train of two systems r. As a result, the sampled signal as shown in FIG. 33 will be sampled at double pulse. Sun Bring frequency is a value above a frequency bandwidth of the signal. That is, in the case of the Since the transmission speed of the baseband signal fb (t) is omega theta, frequency 带域 width in the case of roll-off rate is 0.5 or less is about 3 omega 0. The go-between, as long as the sampling frequency is also a 3 ω 0. Such support Nburingu, phase space at the frequency of the sampled signal it is possible to also extract components other than the real axis, the information obtained is become continuous in the direction of the positive and negative frequency 轴上. However, when the value corresponding to the Un'nobe amount, since only becomes real axis component, the phase shift other than r! : It must be chosen. With this method the frequency offset type application is shown in Figure 33.

Or 9. j

34 and 35 are views for explaining the first 23 configuration and operation principle of the receiving circuit in the embodiment of the present invention. In this twenty-third embodiment of a we'll achieve the quadrature condensate W unit number to be reduced to 1 group force reduction and instrumentation simplify in those based on the 22 same idea as in the form 憨 exemplary it is intended to. Therefore, to prevent aliasing of the frequency axis by performing a second sampling in the A ZD converter, generating a frequency-converted output due to the complementary stations Hatsushu wavenumber of originally required missing side by digital signal processing from AZD varying 换出 force You have to like to configure.

3 4 is a block diagram showing the configuration of a receiving circuit according to the form virtual implementation of the second 3. 3 4, 1 aerial 锒 receiving the reception signal, 9 6 receives 带域 filter is Emperor pass filter for waveform-shaping a received signal at a predetermined frequency 带域, 1 1 orthogonal to the received signal and the input Fukuiki, the local frequency signal generating circuit 4, 8 6 from the quadrature demodulator 1 1 - the first low-pass filter for cutting the high-frequency 带域 the square of the output signal (I), 8 7 the quadrature demodulator second low-pass filter for Katsuhito RF 带域 of said one output signal from 1 1 (I), 9 0 the first a / D converter for AZD Hen换 the output of the first low-pass filter 8 6 , 9 1 band having the second AZD transducer 9 2 these first and second a / D converter 9 0, 9 1 in the received signal to convert AZD the output of the second low-pass filter 8 7 sampling signal having the function of providing a sampling pulse to generate a clock frequency of at least corresponding to the width Namagen, 9 7 is a delay circuit for supplying second to AZD converter 9 1 by offsetting the sampling clock signal from the sampling signal onset Namagen 9 2. The other output signal Q of the quadrature condensate called unit 1 1, the filter 8 6, 8 7, AZD converter 9 0, 9 1, the sampling signal generating source 9 2, constituted by delay circuit 9 7 I et given to the Q axis side circuit section of the shaft-side circuit portion and the same arrangements. Elements of the Q-axis side circuit section indicate corresponding are designated by the dash reference numbers I axis side. 9 3 first and second AZD converter 9 both I side and the Q axis side 0, 9 0, 9 1, 9 1 computing unit to extract a received channel signal desired from the digital output data of the ' is there.

Instead of providing the two low-pass filters 8 6, 8 7, vector be shared single low-pass filter (e.g., low-pass filter 8 6) two to AZD converter 9 0, 9 1, the output of the low pass filter it can be connected to the input of the a / D converter 9 0, 9 1. Further, the sampling signal generating source 9 2, 9 2 'and the delay circuit 9 7, 9 7' can also be shared between the I-axis side circuit section and Q-axis side circuit section.

It will now be described the operation principle and effects of the shape virtual implementation of the second 3. 3 4 Oite, after the received signal received by the aerial bran 1 became 带域 the signal group shall be the subject through the receiving 带域 filter 9 6, the quadrature demodulator 1 1 I-axis component and Q and axial components are extracted. After the signal of the I-axis component is removed the unwanted frequency components in the high frequency regions in the first and second low-pass filter 8 6, 8 7, first and second AZD converter 9 0, 9 enter the 1 It is a force. In the AZD conversion operation in AZD converter 9 0, 9 1, the sampling signal from Sambu ring signal source 9 2 is fed while the first AZD converter 9 0 Ewaso and second AZD conversion is to vessels 9 1 is supplied from the reception frequency offset processing by the circuit 9 7 performs the sampling operation. Sampling of 冋 樣 is also performed for the Q 轴成 minutes. The four digital data obtained through this sampling operation is a digital signal processing is performed is sent to the arithmetic unit 9 3, based spanned output power * obtained.

3 5, in Katachiso embodiment of the second 3 is a diagram illustrating an example of a quadrature sampling in the case of AZD converting the two signals to be orthogonal, the configuration shown in FIG. 35 is received as shown in FIG. 3 4带域 Fuiruku 9 6 below I 轴側 first and second AZD converter 9 of the circuit portion 0, the configuration of up to 9 1, which expressed while revealing a signal flowing in each part, Q-axis side circuit It is shown omitted. In FIG. 3 5, T s 1 is to display the sampling period.

In this embodiment, the frequency conversion is offset remaining omega 0 Power 1 ^ resident in the output signal because it includes the offset frequency omega 0. As this Joso described can have you to form virtual implementation of the second 2, the transmission Myukappaomega theta offset 屈波 number omega theta and carrier can signal 带域 of Motsusupe vector. That this time, the secondary San bling theorem Shannon has a sampling frequency above the signal 带 zone width, can be sampled without exception information i with a more original signal to be added that the pulse train subjected to Un'nobe r it is intended. Thus, sampling wavenumber because if the roll-off factor 0.5 or less frequency 带域 width of the signal fb (t) is about 3 omega 0 is Ru may be a 3 omega 0.邋延 time r, as described above, the phase of the signal fb (t); may be a value other than r. In particular, Tosureba output can form IQ orthogonal planes.

From the above, the signal (t) is because it is sampled as a point on the IQ orthogonal planes can information force holding such as a rotating direction of the signal, and can be de-di- evening Le of positive and negative RenMitsurusei is saved in the frequency axis. Therefore, mosquito it is also positive or negative frequency Hen换 by the digital signal processing digital signal output of the receiver circuit ^: the ability. That is, the signal by performing digital甩波number Hen换of minus 2 ω 0 (to 0 t) and f Q (ω 0 t) signal Π from (- [omega] o t) and i Q - obtaining a (wot) It is a child and force capability. As a result, according to the above method, Konburimentari a local oscillation frequency converter ¾f by frequency, will be need in only one high frequency circuit is vanishing 费電 force can be simplified to about 1 2 are also 輊 dark. Needless to say, the sampling pulse and 1 group of the A / D converter is also equivalent that supplies integrated. That is, in the example of FIG. 2 5, the first AZ D converter 9 0 a second AZD varying exchanger 9 1 and the 1 group AZD converter, the first sampling pulse AZ D converter 9 0 When the second to receive AZD converter 9 1 逢延 pulse common sampling input section or found to have the a / D converter 1 group sampling pulses that by the column, providing the digital output data output section 2 systems, receiving circuit which is adapted to provide by separating the output of the digital output data by sampling pulses which are not cast luck by the output and the delayed sampling pulse of the digital output data can also be configured. Or 4 of

3 6 and 3 7 is a view for explaining the configure and U¾J operation principle of a receiving circuit in Katachiso the second fourth embodiment of the present invention. Also in the second 4 forms JK exemplary, power reduction Ya in likeness flashes in 1 group the number of orthogonal recovery 澜器 with those based on the same idea as in the form virtual embodiment of the first 8 and second 3 simplification of the apparatus is intended to 逮成. However, a plurality (more than 2 groups) AZD converter provided to prevent aliasing of the frequency 轴上 by performing secondary Sambu ring in these A / D converters, by daisy evening Le signal processing from the A / D conversion output and a configuration such as to produce a frequency-converted output due to the complementary local oscillation frequency of the originally required missing side.

3 6 is a proc diagram showing a configuration of a receiving circuit according to the form virtual second fourth embodiment of the present invention. 3 6, 1 antenna for receiving a received signal, 9 receiving 带域 filter is 带域 filter for waveform-shaping the received signal at a predetermined frequency 带域, 1 1 orthogonal recovery of the received signal and the input辋器, the local frequency signal generating circuit 4, 8 the first low-pass filter 6 to cut the high-frequency 带域 one output signal from the quadrature backward transliteration unit 1 1 (I), 8 7 a - 8 7 m Katsuhito to vector the high frequency 带域 of said one output signal from the quadrature demodulator 1 1 (I), second and subsequent low-pass provided plurality in accordance with the second and subsequent number of AZD transducer below filter, 9 0 first AZD converter for AD Hen换 the output of the first low-pass filter 8 6, 9 1 a - 9 1 m is the output of the second and subsequent low-pass filter 8 7 a ~ 8 7 m the second and subsequent AZD converter provided with a plurality IB order to AZD conversion respectively, 9 2 these first Oyopi second and subsequent a / D converter 9 0, 9 1 a Sampling signal generating source ~ 9 1 m to generates a frequency above the clock that corresponds to 带域 width possessed by the received signal has a function of providing a sampling pulse, 9 7 a - 9 7 m sampling signal generating source 9 2 a delay circuit provided more Tsukuda to supply to each of the sampling clock signal and the offset second and subsequent AZD varying exchanger 9 1 a ~ 9 lm from. In the structure of FIG. 36, the one output (I) is I 轴側 circuit portion 34 similarly to the orthogonal condensate called unit 1 1, the other output signal (Q) is, I-axis side circuit of the above configuration It is supplied to the Q 轴側 circuit portion 105 of the part and 间橡. 93 is a 谀算 荐 which to extract a received channel signal desired from the digital output data of said first and second subsequent AZD transducers 90, 91 a-9 lm. In the form ffi this embodiment, the number of the second and subsequent A / D converter 91 A through 9 lm is the MLB. Other Mouth one-pass filter 87, is the same with the 连延 circuit 97. Incidentally, that the sampling signal generating source and m¾ circuit can be shared between I 轴側 circuit section and the Q-axis side circuit section is in the form virtual same 棣 exemplary 23.

It will now be described the operation principle and effects of the shape virtual implementation of the first 24. In Fig. 36, the received signal received by the antenna 1 after becoming 带域 the signal group shall be the subject through the receiving 带域 filter 96, the quadrature recovery W 11 and I 轴成 component and Q 轴成 min It is out of power. After the signal of the I-axis component is removed the unwanted frequency components in the high frequency regions in the first and second and subsequent low-pass filter 86, 87 a -87 m, the first Oyopi second and subsequent AZD transducers 90, 91 It is input to a ~ 9 lm. In the AZD converter 90, AZD Hen换 operation in 91 a ~ 9 1 m, the sampling signal from the sampling signal generating source 92, is to first AZD converter 90 is supplied as it is, also kicked 祓数 pieces 敉and the the second and subsequent AZD converter 91 a-91 m is supplied from the receiving frequency offset processing by each corresponding 遂廷 circuit 97 A~97m perform sampling operation. Sampling 两棣 is performed for Q-axis component. Then, the plurality of digital data through the sampling operation was I axis side obtained and the Q-axis side is sent to the arithmetic unit 93, de-digital signal processing is performed, the baseband output.

Figure 37, in this 24th embodiment, the two orthogonal signals are views for explaining an example of a quadrature sampling when converting A / D, 受倌 structure configuration shown in FIG. 37 is shown in FIG. 36 those 带域 first and second subsequent AZ D converter 9 of the filter 96 below I Nagae side circuit section 0, the configuration of up to 9 1 a ~ 9 lm, expressed while revealed signals flowing at each site is there. In FIG. 3 7, T s 1 represents a sampling period.

In this embodiment, having different delay time (m + 1) Ri by the number of A Roh D converter (m + 1) next sampling is performed. Therefore, it is possible to ffil ^ f arsenide frequency circuit for a signal when transmitting digital variable rebelled multiplexed turned into to.

As a result, according to the above method, complicated dual frequency converter according to the complementary of the local oscillation frequency with respect to the multiplexed digital modulation signal, will be able to cope only with one high frequency circuit is approximately 1 Z 2 consumption »power can be simplified to also be light flashing. Na us, it goes without saying sampling pulses and 1 group of AZD transducer is also equivalent to supply to 铳合.

Or 5 of

Figure 3 8 is a block diagram showing the configuration of a receiving circuit in Katachiso exemplary 笫 2 5 of the present invention. 3 8, reference numeral 1 denotes the antenna, 81 a receiving input circuit for receiving a reception signal received from the antenna 1, 8 8 gain control for gain 1H integer the received signal (AGC: Auto Gain Control) circuit, 9 0 the first a / D converter, 9 1 gain control circuit 8 from 8 outputs signals to the first a / D converter 9 for AZD converting an output signal from the gain control circuit 8 8 0 second AZD converter for a / D cONVERSION the signal received as another system of the signal and, 9 2 带域 width possessed by the first and second AZD converter 9 0, 9 1 in the received signal a function of generating a use wavenumber or more clock corresponding to the sampling clock pulses and a function of adding a delay pulse train to train, the sampling clock pulse train and Un'nobe BALS columns and the first and second AZD converter 9 0, 9 Samburu and a function of providing a 1 San bling pulse Grayed signal source, 9 3 is a calculator for extracting the received channel signal to hope from the first and second A / D converter 9 0, 9 1 of the digital output data. Receiving input unit 81 includes a 坩幅 circuit 9 4, and a 带域 filter (reception 带域) 9 6. Further, in the gain control circuit 8 8 and second AZD converter 9 1 phase shifter 9 9 is kicked crotch.

It will be described the operation principle and effect of the embodiment of the second 5. Signal group received from antenna 1 becomes a signal of only the communication channel 带域 by receiving input circuit 81 including the reception 带域 filter 9 6. This signal is gain adjusted by the gain control circuit 8 8 becomes a predetermined level signal is supplied to a first AZD converter 9 0. Here, n times the frequency of the frequency omega o from the sampling signal generating source 9 2 (n is an integer) as a pulse group, a Sanburin Guparusu by combined pulse groups of the pulse groups of the same frequency which has been subjected to Un'nobe. Thus, the received signal is converted into data centering on the desired channel signal by the first AZD converter 9 0 received two Tsugisa Nburingu action is supplied to the calculator 9 3.

The gain control circuit 8 second while receiving the phase processing action through a signal 鑲 by phase shifter 9 9 given the level received signal gain "3 integer to signal another system gun by 8 AZD converter 9 1 It is supplied. Here, n times the frequency of the frequency omega o from the sampling signal generating source 9 2 (n is an integer) as a pulse group, the sampling pulse by combined pulse groups of the pulse groups冋first frequency subjected to S¾. Thus, the received signal is converted into data centering on the desired channel signal by the second A / D converter 9 1 received the secondary sampling action, it is supplied to the calculator 9 3. In calculator 9 3 performs correlation calculation with generating information when the frequency conversion by the frequency o> c- "0 than evening both data were line summer, to extract the desired signal as a common wave.

3 9 is the operation of the sampling signal generating source 9 2 in the form ¾ embodiment of the second 5 - a structure represented in FIG. 3 8 for explaining an example one of AZD converters (for example, 9 0), it is a schematic proc diagram showing the portions other than the sampling signal generating source 9 2 and calculator 9 3 in a simplified I arsenide. Figure 3 In the 9 examples (the eta integer) eta multiple of the frequency of the frequency omega o from the sampling signal generating source 9 2 is yielding a pulse group, also Tsunobekai path extending in r times for omega 0 added to the pulse train from the sampling clock generator performs a 搡作.

4 0 0 sampling signal generating source 9 to describe another example of the second operating configuration represented in FIG. 3 8 first A / D converter 9 in Katachiso embodiment of the second 5 is a schematic plot click view showing the portion other than the Sambu ring signal source 9 2 and calculator 9 3 in a simplified I spoon. 4 0 (n is an integer) n times the frequency of the frequency omega 0 is the sampling signal generating source 9 2 in the example is yielding a pulse group, also delay circuit omega. Tautau Zeta performs 31 extending operation of 2 hours, the sampling pulse train from the clock producing unit, delayed pulse train from the circuit for adding a delayed pulse train, a phase difference time, particularly corresponding to JT Z 2 of the frequency of the desired channel signal to the to generate a Un'nobe pulse that has been cast luck.

4 1 sampling signal generating source 9 to describe another example of the second operating configuration represented in FIG. 3 8 first AZD converter 9 0 in Katachiso embodiment of the second 5, Sambu it is a schematic plot click view showing the portion other than the ring signal source 9 2 and calculator 9 3 W Ryakuka. Figure 4 (the η integer) frequency η times the frequency omega 0 is the sampling signal generating source 9 2 1 example is yielding a pulse group, also Un'nobe circuit omega. Against performed multiple times Un'nobe 搡作 of JT Z 2 hours, and the pulse train from the sampling clock generator, Un'nobe pulse train from the circuit for adding iS extended pulse train, especially [pi 2 of the frequency of the desired channel signal that it has allowed a plurality of rows generate the corresponding Un'nobe pulses delayed phase difference time

Rather than conveying 两波 number of accordance when the reception 侰号 the form ¾8 of this embodiment from the above, the 带埭 width frequency that is based by a sampling clock frequency of AZD converter, if the sampling frequency component leaks in the air never cause interference on the communication even if it is possible to prevent easily leak at the receiving 带域 filter 9 6 incorporated in the received signal input circuit 8 1. Further, the sampling frequency is much lower than the conveying ^ wavenumber, it is apparent that requires only a low frequency that dominates the power consumption of the circuit "also present at all the frequency conversion circuit of the analog system to the receiving circuit does not, active elements and filter elements is no need involved in this. AZD converter 9 0, 9 1 and subsequent digital signal processing circuit can integrated circuit all, low dark effect of consumption 费電 force distribution the procedure is associated with that requires only very small inside Integrated Circuit on which can be miniaturized There Ru Oh at large. From the above, the present embodiment without having to generate a communication disturbance due to leakage of the local oscillator frequency to reduce the power of the receiving system, and nodes iodinated reception circuit can vanishing 费電 force low flashing this and force * .

Katachi裤 2 fi of ¾ 掄

Next will be described embodiments of the second 6 of the present invention. So far improvement for the receiving circuit of the mobile communication instrumentation fi is to reduce the consumption »S force reduces the high-frequency circuit portion have been variety, it does not reach the both decisive improvement. Here, the frequency distribution S schematic view of the Japanese standard digital type automobile ¾¾S system as FIG 2. In Fig 4 2, for example, in Japan the standard which is an example PDC of 8 1 0 MH z~8 2 6 MH z 6 4 0 waves are included. That is, the one 2 0 0 channel arranged at 2 5 KH z. Directly to it is very wasteful to the San bling for this frequency 带. If Na ze, 带域 width of the channel transmission information is accommodated as narrow as 2 3 KH z, information 惫 is not low. Therefore, if the sampling directly the carrier frequency is 带域 8 0 O MH z to the other party a 带 tt signal received, is a calculation sampling number GH z (Ruth to giga) is required, the amount of information will be the only 2 5 KH z, most Sambu ring data becomes redundant.

Receiving apparatus of this embodiment is to realize a method for applying the received signal directly to the AD converter is obtained by allowing the removal of the frequency converter.

The sampling theorem Shannon, when considering the case of a uniform specimen of the maximum value of the time interval of the sample required to define any number of hours f (t), is expressed by the following equation, which is well known the over-sampling of the theorem.

Here, use wavenumber W is the wavenumber components for IBM number f (t) contains time limit, i.e. in this case indicates the 826MHz. Therefore, sampling at least twice the 826MHz, becomes several giga szs. Here, think about «If the scan Bae spectrum is IS constant from f 1 to f 2. This * equation using the secondary sampling theorem of Shannon in case becomes the following equation., Ηη + thousand)

And l uT) »n (/ T ) (ηΤ) iinn {| + f 2) (+ _ ηΤ))

■ f Hit): the "te * B of the -f digits) of ten all of the scan Bae-vector>» 2

Which was shifted only

.... (64) This equation, specimen ra

T = l / (f 2 - f 1)

Each in: f if sampling the value of (t) and fq (t) the original signal f (t) is shown to be able to fully express. Therefore,

f 2- f 1-W (Hz)

When the, time sampling at 1 / W, may be sampled f and (t) fq (t) to alternately. That is, the bandwidth of the filter provided in 受侰 input circuit can be dealt with 25 kHz sampling ¾E if 25 k Hz. ! Real ^ in including all the 敉Ke was filter contact channel to a receiving input circuit 88: Since the needle, the 帚域 width, 8 2 6 (MH z) - 8 1 0 (MH z) - 1 6 ( MH z)

Becomes the 1 6 MH z width, the sampling rate will be 1 5 MSZ s. Indicating the arrangement state of the received signal in Fig 3. FIG. 4 3 is a channel 置概 view diagram of the Japanese standard digital system automobile «talk system.

Figure 4 4 ​​is a block diagram showing the configuration of a receiving circuit in Katachiso exemplary second 6 of the present invention. 4 4, reference numeral 1 is air 锒, 8 1 receives an input circuit for receiving a received signal received from the aerial 锒 1, the gain control circuit 8 8 performing gain US integer for the received signal, 9 0 gain control circuit 8 AZD converter output signal from the 8 AZD conversion, 9 2 sampling clock generator 9 2 for generating a frequency above the clock that corresponds to 带域 width possessed by the received signal to the a / D converter 9 0 a and a Un'nobe pulse adding unit 9 2 b of adding Un'nobe pulse train to a sampling black Kkuparusu column pulses to provide a sampling clock BALS columns and Un'nobe BALS column as a sampling pulse of the AZD converter 9 0 sampling signal generating source having an addition unit 9 2 c, 9 3 is a calculator for extracting a received channel signal desired from the digital output data of said AZD transducer 9 0. Receiving input unit 81 includes a ¾ width circuit 9 4, and a receiving 带域 filter 9 6.

It will now be described the operation principle and effects of the shape virtual implementation of the second 6. Signal group received from the air 躲 1 is a signal of only the communication channel band by receiving input circuit 81 including the reception 带域 filter 9 6. This signal is gain KoboshiSei becomes a predetermined level of the signal by the gain control circuit 8 8, is supplied to AZD converter 9 0. Here, 11 times the frequency of the frequency f 0 from the sampling signal generating source 9 2 (n is an integer) as a pulse group, the Sambu ring pulse by pulse combined pulse group of a group of the same frequency which has been subjected to S® . Thus, the received signal is converted into data centering on the desired channel signal to obtain a secondary Sambu ring action of A / D converter 9 0, is supplied to 潢算 9 3. In calculator 9 3 This data division in the frequency I c one f 0 6/17441

92

Performs phase 閱浪 calculation generates the information in the case of performing the wavenumber transform to extract the desired signal BPSK signal as a common wave.

From the above, according to the form virtual of the present embodiment, in a mainly to a communication system having a digital variable scheme of BPSK method having a plurality of channels, it is possible to receive the desired wave channel Izu use a frequency converter, power low dark, it is possible to realize a receiving circuit which enables simplification of the circuit. Incidentally, the Te second 6 form of implementation of) beta smell has a configuration for performing AZD conversion process using 1 group of AZD converter 9 0, 2 types of parallel arranged AZD converter 2 group yo les, by method supplied Separating sampling pulse train, is synthesized after obtaining the digital signal output.

Or 9. 7

4 5 is a block diagram showing a configuration of a reception circuit in the embodiment of the second 7 of the present invention. 4 5, reference numeral 1 denotes the antenna, 81 a receiving input circuit for receiving a reception signal received from the aerial 孃 1, gain control circuitry 8 8 performing gain W integer for the received signal, 9 0 gain control first AZD converter for AZD converting an output signal from the circuit 8 8, 9 1 as the signal of the second system different from the AZD converter 9 0 output signal the first of the gain control circuit 8 8 second AZD converter for receiving AZD converts this signal, the 9 2 Yoko these first and second AZD converter 9 0, 9 clocks greater than the frequency corresponding to 带域 width possessed by the received signal to 1 a sampling clock generator Ichiro 9 2 a to Mizunoto production, the sampling clock pulse train and Tsunobe pulse adding unit 9 2 b of adding Un'nobe pulse train, the sampling clock pulse train and g extending pulse train and said first and second pulse pressure to provide a sampling pulse of the a / D converter 9 0, 9 1 Part 9 Sa Nburingu signal source and a 2 c, 9 3 are calculator for extracting a received channel signal desired from the A / D converter 9 0, 9 1 of the digital output data, 9 9 the gain control It performs phase processing by receiving the output of the circuit 8 8, a phase shifter to send a 倌号 obtained Te cowpea to the second a / D converter 9 2. Receiving input unit 81 includes a 增幅 circuit 9, and a reception 带域 filter 9 6.

It will be described the operation principle and effect of the embodiment of the second 7. Signal group received from the air 锒 1 is a signal of only the communication channel 带域 by receiving input circuit 81 including the reception 带域 filter 9 6. This signal is gain ISei a predetermined level of the signal by the gain control circuit 8 8. The output of the gain control circuit 8 8 is distributed into two systems.

Output of one line is input to the first AZD converter 9 0, pulse group of frequencies or clock pulse train corresponding to the bandwidth possessed by the received signal, i.e. n times the frequency of the frequency f 0 (n is an integer) When receives the sampling pulse by combined pulse groups of the pulse groups Question over frequency having been subjected to delay from the sampling signal generator 9 2, is sampled controlled. First AZD converter 9 0 produces exactly the same digital signal output AZD varying exchanger in Katachiso embodiment of the second 6, and supplies this to the calculator 9 3. On the other hand, the output of the gain control circuit 8 8 is divided E to another system (second system). Second system is SeMMitsuru to the phase shifter 9 9, the received signal in the phase shifter 9 9 is given a phase change of 9 0 degrees. Signal the phase shift processing is input to the second A / D converter 9 1, second AZD converter 9 1 above frequency corresponding to 带域 width possessed by the received signal clock pulse train, i.e. and pulse groups n times the frequency of use wavenumber f 0 (n is an integer), it receives a sampling pulse from the sampling signal generator 9 2 by combined pulse groups of the pulse groups of the same frequency which has been subjected to 逢延, sampling control It is. Calculator Te 9 3 odor extracts the BPSK signal as a common wave desired signal subjected to phase calculation generates the information in the case of performing frequency conversion by the frequency fc one f 0. This 桔果, from a second digital output AZD converter 9 1, BPSK signal extracted by the arithmetic unit 9 3, information having a phase difference of the first AZD converter 9 0 side of the output and 9 0 degrees it is. Two This information forms a QPSK signal system. Therefore, indicating that it is restored W with respect to the signal of the QPSK system communication method from above.

From the above, according to this embodiment, it is possible to primarily in a communication system having a digital variable 瀾方 type QPSK system having a plurality of channels, receives a desired wave channel Izu use a frequency converter, S reduction of the force, it is possible to realize a receiving circuit which enables simplification of the circuit.

Form of Gai施 ^ 2 fi

4 6 is a block diagram showing the configuration of a receiving circuit in the form of implementation of the second 8 of the present invention. Form of this embodiment is incorporated into the local frequency complementary offset type direct frequency conversion scheme underlying the present invention, to realize a space diversity function by a receiving circuit which is based on a single direct quadrature detector. 4 6, reference numeral 1 consists of a first antenna 1 a and a plurality of antenna of the second aerial parent 1 b is aerial.

8 1 The first reception input circuit for receiving a first received signal received from the first antenna 1 a, 8 2 second receiving a second received signal received from the second aerial «1 b the receiving 侰入 power circuit, 8 3 first frequency converter for performing frequency Transformations enter the received signal from the first receiver input circuit 81, 82 4 from the second reception input circuit 82 enter the reception signal a second frequency converter for performing frequency conversion, 8 5 1 Z channel spacing frequency to the desired wave carrier frequency to each of the first and second frequency converters 83, 84 Tsubonero 拫器 to provide an output at a frequency which has been subjected to second frequency offset, 8 6 first low-pass filter for Katsuhito RF 带域 of the first output signal of the frequency converter 8 3, 8 7 second the second low-pass filter for the output signal of the frequency converter 8 4 Katsuhito RF 带 «of the 8 8 about the first received signal Te performs gain KoboshiSei first gain control (AGC: Auto Gain Control) circuit, 8 9 second gain control circuit for gain adjustment for the second reception signal, 9 0 first frequency converter 8 first AZD transducer output signal from the 3 AZD conversion, 9 1 second a Roh D converter for the output signal a / D conversion from the second frequency converter 8 4, 9 2 a function of generating first and second AZD converter 9 0, 9 1 frequency or more clock corresponding to 带域 width possessed by the received signal, the function of adding a delayed pulse train to a sampling clock pulse train , the sampling signal generating source having a function and that provide a sampling clock pulse train and ® rolled pulse train and the front Symbol first Oyopi second a / D converter 9 0, 9 1 of the sampling pulse, 9 3 the first Oyopi second AZD converter 9 0, 9 one of the digital output data A calculator for extracting the received channel signal to al desired. First and second receiver input section 81 is constituted by respectively 墦幅 circuit 9 4, 9 5, the reception 带域 filter (band-pass' filter) 9 6, 9 7.

It will be described the operation principle and effect of the embodiment of the second 8. The first air in the signal group received from 锒 1 a by receiving 带域 filter 9 6 becomes Mino signal communication channel 带域, the local oscillation frequency fc applied the offset by a first frequency converter 8 3 + is frequency-converted by fo. The local oscillation frequency is supplied from the local oscillator 8 5. As a result, the output of the frequency 2 ί c + i 0 and frequency one I 0 is the first low-pass filter 8 6 is supplied, a signal of a frequency one I 0 is Desa taken by the low-pass characteristics. This signal is the first gain control circuit 8 8 becomes a predetermined level signal is supplied to a first AZD converter 9 0. Here, eta multiple of the frequency of the frequency I 0 from the sampling signal generating source 9 2 (eta is an integer) as a pulse group, the sampling pulse by combined pulse groups of the pulse groups of the same frequency which has been subjected to Un'nobe.

Thus, the first AZD converter 9 0 is obtained secondary sampling action, into data centering on the desired channel signal of the input signal. Varying 换信 No. is supplied to the calculator 9 3.

Signal group received from a second antenna 1 b by receiving 带域 filter 9 7 becomes a signal of only the communication Channel 带域, the local oscillation frequency fc + fo made of offsets by the second frequency converter 8 4 in the frequency conversion. The local oscillation frequency is supplied from the local oscillator 8 5. This 枯果, but the second low-pass filter 8 7 the output of the frequency 2 fc + f 0 and the frequency one f 0 is supplied, the signal of a frequency one I 0 is taken out by Teiikidori S characteristics. This signal becomes signal of a predetermined level by the second gain control circuit 8 9, is a second Kyo耠 to AZD converter 9 1. Here, the sampling source

9 2 from the frequency f 0 of n times the frequency (n is an integer) as a pulse group, the sampling pulse by combined pulse groups of the pulse groups of the same frequency which has been subjected to the delay. More thereto, the second A / D converter 9 1 is converted into data centering on the desired channel signal to obtain a second sampling action, is fed to the 滇算 9 3. In calculator 9 3, frequency from both data fc - performs a correlation operation generates the information in the case of performing frequency conversion in fo, to extract the desired signal as a common wave. Figure 4-7 is a block diagram showing the configuration of a receiving circuit in the form of implementation of the second 9 of the present invention. Receiving circuit according to the form virtual to this embodiment, a detailed description by the arc designated by the same reference numerals for the same parts from having almost the same configuration as the receiving device according to the shape virtual embodiment of the second 8 omitted. In this Katachiso exemplary second 9, it is provided a station ¾ vibration isolation device is 2 group. One of the local oscillator 8 5 a are the same as the local oscillator 8 5 of an embodiment of the second 8, the local oscillator 8 5 a first is connected to the frequency converter 8 3 The frequency converter 8 and it supplies the local onset wavenumber fc + fo to 3. The local oscillator 8 5 b the other hand the local oscillation frequency fc to the frequency converter 8 4 are connected to the second frequency converter 8 4 - has a configuration for supplying fo.

It will be described the operation principle and effects of exemplary forms) K of the second 9. Signal group received from the first antenna 1 a by the reception Emperor pass filter 9 6 becomes a signal of a communication channel Emperor zone only, the first use wavenumber converter 8 station unit made of offset by 3 oscillation frequency fc + It is frequency-converted by fo. The local oscillation frequency is supplied from the local oscillator 8 5 a. As a result, the first low-pass filter 8 6 the output of the frequency 2 fc + fo and the frequency one f 0 is supplied, the signal of a frequency one f 0 is taken out by the low pass through even-characteristics. This signal is the first gain control circuit 8 8 becomes a predetermined level signal is supplied to a first A / D converter 9 0. Here, San bling 侰 No. source 9 2 n times the frequency f 0 and a pulse group frequency (n is an integer), the San bling pulse by combined pulse groups of the pulse groups of the same frequency which has been subjected to Un'nobe obtain. Thus, the first A / D converter 9 0 is converted into data centering on the desired channel signal to obtain a second sampling action, it is supplied to the calculator 9 3.

Signal group received from a second antenna 1 b by receiving 带域 filter 9 7 becomes a signal of only the communication Channel 带域, second offset by a frequency converter 8 4 of added et a local oscillation frequency fc is frequency converted in one f 0. This local oscillation frequency is supplied from the local oscillator 8 5 b. As a result, the second low-pass filter 8 7 the output of the frequency number 2 fc- f 0 and the frequency f 0 is supplied and venture out signal power of the frequency f 0 by the low-pass characteristics. This signal is the second gain control circuit 8 9 becomes a predetermined les pel signals are supplied to the second AD converter 9 1. Here, the pulse group of n times the frequency of the frequency f 0 from Sanburin grayed signal source 9 2 (n is an integer), the San bling Bal scan by combined pulse groups of the pulse groups of the same frequency which has been subjected to 涯 extension obtain. Thus, the second AZD converter 9 1 is converted into data centering on the desired channel signal to obtain a second sampling action, it is supplied to the calculator 9 3. In arithmetic unit 9 3 performs a correlation calculation generates the information in the case of frequency conversion was rows summer at the frequency fc one f 0 from both data, to extract the desired signal as a common wave.

Or ¾ of? 3 Ω

4 8 is a block diagram showing a configuration of a third 0 receiving circuit in the form S embodiment of the present invention. Receiving circuit according to the form virtual this embodiment has a reception instrumentation fi basically the same configuration according to the second 8 Oyopi embodiment of the second 9, in which further the structure is simplified. Thus the form virtual same parts as the above two embodiments are denoted by the same reference numerals, easy merely a description of the configuration. 4 8, reference numeral 1 is composed of a plurality of aerial Su first antenna 1 a and the second antenna 1 b is air 镍. 8 1 The first reception input circuit for receiving a first received signal received from the first aerial 鎵 1 a, 8 2 receives the second reception signal received from the second aerial bran 1 b second reception input circuit, 8 8 first gain control circuit will gain I »an integer row for the first received signal, 8 9 second gain control for gain 瘸整 for the second received signal circuit, 9 0 first AZD converter for AZD converting an output signal from the first gain control circuit 8 8, 9 1 second you AZD converting an output signal from the second gain control circuit 8 9 of the AD converter, 9 2 and function to supply a frequency above the clock that corresponds to the bandwidth with the first and second AZD converter 9 0, 9 1 in the received signal, the 遂 to Sambu ring clock pulse train extension pulse and function of adding columns, the sampling clock pulse train and Un'nobe pulse train and said first and second AZD converter 9 0, 9 1 of the sampling signal generating source having a function of providing a sampling pulse, 9 3 extracts the received channel signal to hope from the first and second AZD converter 9 0, 9 1 of the digital output data Sina it is an adder. Receiving input 8 of the first and second are each composed of a 增幅 circuit 9 4, 9 5, the reception 带 ¾ filter 9 6, 9 7.

It will now be described the operation principle and effects of the shape virtual implementation of the third 0. Signal group received from the first antenna 1 a by receiving 带域 filter 9 6 becomes a signal of a communication channel 带 zone only, the signal becomes a predetermined level of the signal by a first gain control circuit 8 8, the It is supplied to the first a / D converter 9 0. Here, n times the frequency of the frequency I 0 from the sampling source 9 2 (n is an integer) and a pulse group, the subjected to delay - get San bling pulse by combined pulse groups of the pulse groups of frequencies. Thus, the first A / D converter 9 0 is converted into data centering on the desired channel signal to obtain a second sampling action, it is supplied to the calculator 9 3.

Signal group received from the second aerial 锒 1 b by the reception bandpass filter 9 7 becomes a signal of only the communication Channel 带域, this signal is given Lepe Le signal by a second gain control circuit 8 9 it is fed to the second AZD converter 9 1. Here, the wave number use of n times the frequency f 0 from the sampling onset Namagen 9 2 (n is an integer) as a pulse group, the sampling BALS by combined pulse groups of the same 甩波 number of pulse groups subjected to Un'nobe. This ensures that the second AZD converter 9 1 is converted into data centering on the desired channel No. signal to obtain a second sampling action, is fed to the Sina adder 9 3. In calculator 9 3 performs phase M 谀算 generates the information in the case of performing a frequency conversion from both data at the frequency fc one f 0, to extract the desired signal as a common wave. This embodiment does not perform the frequency conversion in the preceding stage of AZD converter, to have its function AZD converter.

From the above, according to this embodiment, Ru can be realized space diversity function added to make station frequency complementary offset type 鬩波 Variable 换方 formula roots essence of the present invention.

The present invention, as is apparent from the shape »of each real, Chiya Ne included in the communication system

Utotomoni, it is possible to prevent the signal of the frequency offset Contact Yopi 55 contact channels generated on the output signal is mixed, to reduce the power of the reception system as a result, 简素 the circuit, to reduce the consumption 费電 force be able to.

All were above is limited to the preferred embodiment virtual like of the present invention, for the purpose of disclosure, an example of changes and modifications set forth herein and do not deviate from the spirit and scope of the invention it is intended to include.

Claims

The scope of the claims
1. A first and second frequency converting circuits for receiving the signal received by antenna, connected to said first and second frequency converting circuit, adjacent to the non-linear carrier frequency the received signal has thereby generating a frequency intermediate between the radio carrier frequency having the upper and lower channels, and outputs the upper frequency of the frequency of the upper and lower two waves as conversion frequency input of the first frequency converting circuit, the lower frequency and outputs as a conversion frequency input of the second frequency converting circuits local frequency signal generating circuit and an output and said second of said first and second connected to the frequency conversion circuit and the first frequency conversion circuit of the common wave extracting circuit for extracting a component present in common in both the outputs of the frequency converter, the frequency remains at the output of which is connected to the front Symbol common wave extracting circuit and the common wave extracting circuit offset Receiving circuit including a frequency offset circuit for removing a preparative amount, and a filter for removing an unnecessary frequency component remaining in an output of which is connected to said frequency offset circuit before Symbol frequency offset circuit.
2. A first and second frequency converting circuits for receiving the signal received by antenna, connected to said first and second frequency converting circuit is adjacent to the radio carrier frequencies with the received signal is the vertical thereby generating an intermediate frequency between a radio carrier frequency with the channel, the upper frequency of the frequency of the upper and lower two waves output as conversion frequency input of the first frequency conversion circuitry, the lower frequency a local frequency signal generating circuit for outputting a conversion frequency input of the second frequency conversion circuit, wherein the first first frequency offsets circuit for removing a frequency offset component contained in the output of the frequency conversion circuit When a second frequency offset circuit for removing the second frequency offset contained in the output of the frequency conversion circuit, said first frequency offset circuit Serial and common wave extracting circuit for extracting a component present in common in both the outputs of the second frequency offset circuit, receiving circuit and a filter for removing an unnecessary frequency component remaining in an output of the common wave extracting circuit .
3. A first and second frequency converting circuits for receiving the signal received by antenna, connected to said first and second frequency converting circuit is adjacent to the radio carrier frequencies with the received signal is the vertical thereby generating an intermediate frequency between a radio carrier frequency with the channel, the upper frequency of the frequency of the upper and lower two waves output as conversion frequency input of the first frequency conversion circuitry, the lower frequency a local frequency signal generating circuit for outputting a conversion frequency input of the second frequency converting circuit, a first quantization means for quantizing the output of said first frequency conversion circuit, said second frequency conversion circuit a second quantizing means for quantizing the output, the common wave extracting circuit for extracting a component present in common in both outputs of said first of said quantization means second quantization hand stage, the common wave extraction A frequency offset circuit for removing a frequency offset component remaining in an output of the detection circuit, receiving circuit and a filter for removing an unnecessary frequency component remaining in an output of said frequency Ofuse' preparative circuit.
4. The first and second frequency converting circuits for receiving the signal received by the antenna, connected to said first and second frequency converting circuit is adjacent to the radio carrier frequencies with the received signal is the vertical thereby generating an intermediate frequency between a radio carrier frequency with the channel, the upper frequency of the frequency of the upper and lower two waves output as conversion frequency input of the first frequency conversion circuitry, the lower frequency a local frequency signal generating circuit for outputting a conversion frequency input of the second frequency converting circuit, a first quantization means for quantizing the output of said first frequency conversion circuit, said second frequency conversion circuit a second quantizing means for quantizing the output, a first frequency offset circuit for removing a frequency offset component contained in the output of the first quantizing means, said second quantizing A second frequency offset circuits for removing a frequency offset contained in the output of the means, present in common in both outputs of the first frequency offset circuit and said second frequency offset circuit reception circuit having a common wave extracting circuit, and a filter for removing an unnecessary frequency component remaining in an output of the common wave extracting circuit for extracting a component.
5. The first and second quadrature demodulating circuits for receiving a received signal received by the antenna, which is connected to the first and second quadrature demodulating circuits adjacent to the radio transport wave frequency the received signal has the vertical thereby occur an intermediate frequency between a radio carrier frequency with the the channel, and outputs the upper frequency of the frequency of the upper and lower two waves as conversion frequency input of the first quadrature demodulating circuit, said lower frequency a local frequency signal generating circuit for outputting a conversion frequency input of the second quadrature demodulating circuit, the second perpendicular to the I outputs of the first and second orthogonal coupled to the demodulation circuit and the first quadrature demodulating circuit the first common wave extracting circuit, and a Q output of the being Se' to the first and second quadrature demodulating circuits said first quadrature demodulating circuit for extracting a component present in common in both the I outputs of the demodulation circuit said second orthogonal Second common wave extracting circuit, said first common wave frequency offset component remaining in the extracted I output extraction circuit for extracting a component present in common in both the inversion output Q output of the demodulation circuit a first frequency offset circuit for removing a second frequency O Fuse' preparative circuit for removing a frequency offset component remaining in the Q output extracted by the second common wave extraction detecting circuit, the first a first filter for removing an unnecessary frequency components remaining in the output of the frequency offset circuit, and a second filter for removing an unnecessary frequency component you remaining output of the second frequency offset circuit reception circuit.
6. The first and second quadrature demodulating circuits for receiving a received signal received by the antenna, connected to said first and second quadrature demodulating circuits adjacent to the radio transport wave frequencies with the received signal is the vertical thereby occur an intermediate frequency between a radio carrier frequency with the the channel, and outputs the upper frequency of the frequency of the upper and lower two waves as conversion frequency input of the first quadrature demodulating circuit, said lower frequency first and removes the local frequency signal generating circuit for outputting a conversion frequency input of the second quadrature demodulating circuit, a frequency offset component included in common in I outputs and Q outputs of the respective quadrature demodulating circuits a second frequency offset circuit, a first common for extracting the component present in common in both the I outputs of the first frequency offset and the second frequency offset circuit and the I output of the circuit An extraction circuit, a second common wave extracting circuit for extracting the Q output component present in common in both the inversion output of said first said second quadrature demodulating circuit and the Q output of the quadrature demodulation circuit, receiving circuit that includes a first and second filter for removing an unnecessary frequency component remaining in an output of the respective common wave extracting circuit.
7. The first and second quadrature demodulating circuits for receiving a received signal received by the antenna, connected to said first and second quadrature demodulating circuits adjacent to the radio transport wave frequencies with the received signal is the vertical thereby occur an intermediate frequency between a radio carrier frequency with the the channel, and outputs the upper frequency of the frequency of the upper and lower two waves as conversion frequency input of the first quadrature demodulating circuit, said lower frequency a local frequency signal generating circuit for outputting a conversion frequency input of the second quadrature demodulating circuit, first and second quantizing means for respectively quantizing the I and Q outputs of the first quadrature demodulating circuit, extraction and third and fourth quantization means for respectively quantizing the I and Q outputs of the second quadrature demodulating circuit, a component present in common in the I outputs of the first and third quantizing means the first co-be And wave extracting circuit, a second common wave extracting circuits for extracting a component present in common in both the inversion output Q output of the second said the Q output of the quantization means of the fourth quantizing means , frequency remaining in the first frequency offset circuit for removing a frequency offset component remaining in I output extracted by the first common wave extracting circuit, the Q output extracted by the second common wave extracting circuit a second frequency offset circuit for removing the offset component, a first filter for removing an unnecessary frequency component remaining in an output of the first frequency offset circuit, the output of the second frequency offset circuit receiver circuit and a second filter for removing an unnecessary frequency component remaining in the.
8. The first and second quadrature demodulating circuits for receiving a signal received by antenna, connected to said first and second quadrature demodulating circuits adjacent to the radio transport wave frequency the received signal has the vertical thereby occur an intermediate frequency between a radio carrier frequency with the the channel, and outputs the upper frequency of the frequency of the upper and lower two waves as conversion frequency input of the first quadrature demodulating circuit, said lower frequency a local frequency signal generating circuit for outputting a conversion frequency input of the second quadrature demodulating circuit, the first quadrature demodulating circuit
First and second quantizing means for respectively quantizing the I and Q outputs, and third and fourth quantization means for respectively quantizing the I and Q outputs of the second quadrature demodulating circuit, a first common wave extracting said frequency offset circuit for removing a frequency offset component remaining in I and Q outputs of the quantizing means, the Ingredient present in common in the I outputs of said frequency offset circuit an extraction circuit, a second common wave extracting circuit for extracting the Q output and Q output components present in common in both the inversion output of said frequency offset circuit, the output of said first common wave extracting circuit the removal of the first filter for removing an unnecessary frequency component remaining, unwanted frequency components remaining in outputs of said second common wave extracting circuit
Receiver circuit and a second filter.
9. Comprising a correlator for calculating a cross-correlation instead of the common wave extracting circuit, the correlator claims, characterized in that connected to the output of the quantization means or frequency offset circuit 3, 4, 7 receiving circuit according to any one of 8.
The 1 0. The frequency conversion circuit for inputting the received signal only the first frequency converting circuit, after the frequency conversion by the first frequency converting circuit, other frequency conversion circuit, said first
Obtained first by the frequency converter frequency conversion output on the side not subjected to frequency conversion, the reception of claim 1 or 2, wherein the ensuring two frequency-converted output required to the common wave extracting circuit.
1 1. Deijidaru frequency conversion circuit further comprising a only one quantization means of the first and second quantizing means with only to the first frequency converting circuit the frequency conversion circuits for inputting the received signal use, after quantization by said quantization means, said by di digital frequency converting circuit to obtain a frequency-converted output of the first side did I row frequency conversion by the frequency conversion circuit, required for the common wave extraction receiving circuit according to claim 3 or 4, wherein the securing of such two frequency conversion digital outputs.
1 2. Frequency converter further comprising a use only one of the orthogonal demodulation circuit of the first and second quadrature demodulating circuits for inputting the received signal, two respective frequencies the output of the quadrature demodulation circuit by performing frequency conversion by the conversion circuit to obtain a frequency converted output was not the quadrature demodulation side, claim 5 or 6, wherein the securing two orthogonal demodulated output of the required common wave extraction receiving circuit.
1 3. Digital frequency conversion circuit further comprising a quantization means with using only one of the orthogonal demodulation circuit of the first and second quadrature demodulating circuits for inputting the received signal also the second and third only the quantized means, after quantization by the quantization means, by performing frequency conversion by the respective digital frequency converting circuit two outputs of the quantizing means, the frequency conversion is not carried out quadrature demodulation side to obtain an output, the receiving circuit according to claim 7 or 8, wherein the securing two orthogonal demodulated output of the required common wave extraction.
1 4. The first and second frequency converting circuits for receiving the reception signals received by the antenna is connected to the first and second frequency converting circuit, adjacent to the non-linear carrier frequency the received signal has thereby generating a frequency intermediate between the radio carrier frequency having the upper and lower channels, and outputs the upper frequency of the frequency of the upper and lower two waves as conversion frequency input of the first frequency converting circuit, the lower frequency the a local frequency signal generating circuit for outputting the second as conversion frequency input of the frequency conversion circuits, said first frequency conversion circuit and a second mouth one path for receiving through each input line the output of the frequency conversion circuit . the first integrating circuit and the second integrating circuit which also serves as a filter, the first integrating circuit and a first buffer amplifier for receiving the second output of the integrating circuit, respectively, and the second And a buffer amplifier, said first buffer amplifier and a second respective output of the buffer amplifier phase equal structure carrying on one end of the primary Koiru first transformer and a second transformer, the first transformer and the the other end of the second transformer primary coil exchanges to grounded to both the secondary Koiru is when connected in parallel together polarity to the polarity of the primary Koiru both an output terminal of one end equal to the polarity of the primary coil, is grounded and the other end, a third buffer amplifier and said third frequency off to remove the frequency offset component remaining in an output of the buffer amplifier for receiving an output of said a further first transformer and second transformer reception circuit including a set circuit and a filter for removing an unnecessary frequency component remaining in an output of the frequency offset circuit.
1 5. A first and second frequency converting circuit which receives the reception signal received by the antenna, an intermediate frequency between a radio carrier frequency with the upper and lower channel adjacent the radio carrier frequency, wherein the received signal has as well as generate, the upper and lower two waves of frequency sac Chi upper frequency fed as conversion frequency input of the first frequency converting circuit, supplies the lower frequency as conversion frequency input of the second frequency conversion circuit a local frequency signal generating circuit for a first and second differential amplifier receiving via the first frequency conversion circuit and the second respective input line the output of the frequency conversion circuit, said first and second differential a first and second integrated circuit which also serves as a mouth one pass filters receiving respectively corresponding to the output of the amplifier, the first contact for supplying an output of said first and second integrated circuits Beauty and second buffer amplifiers, and means for applying feedback to each of the output side to the negative input side of the first and second buffer amplifiers, the first and second buffer each primary coil output of the amplifier phase equal first and second transformer structure carrying at one end, the other end of the pre-Symbol first and second transformer primary coil at least AC manner grounded secondary coil fit polarity to the polarity of the primary coil as well as connected in parallel Te, primary Koi and polarity equal one output terminal of Le, less the other end <are together AC grounded, a third buffer for receiving the output of the previous SL first and second transformers amplifier and the output and the second of the third first frequency conversion circuit by comparing the average and the outputs of the second frequency conversion circuit of the first frequency converting circuit and the output of the buffer amplifier and the output of the frequency conversion circuit Osamu Means for applying a positive, the output of the third buffer amplifier, said first to correct for differences occurring between the output of the first output and the second frequency conversion circuit of the frequency conversion circuits means for feeding back to the output side of the output or the second frequency converting circuit of the frequency conversion circuit, a frequency offset circuit you remove frequency offset component remaining in an output of the third buffer amplifier, said frequency receiver circuit and a filter for removing an unnecessary frequency component remaining in the output of the offset circuit.
1 6. One end of the secondary coil equal in polarity of the primary coil instead of connecting to the third buffer amplifier, and wherein the one end of which is connected to the different secondary coils and the polarity of the primary coil to the third buffer amplifier receiving circuit according to claim 1 4 wherein.
1 7 -. One end of the secondary coil equal in polarity of the next coil instead of connecting to the third buffer amplifier, characterized in that one end connected to the different secondary coils and the polarity of the primary coil to the third buffer amplifier receiving circuit according to claim 1 5, wherein the.
1 8. A first frequency signal source is equal to the carrier frequency of the desired reception signal, a first for phase shifting the phase of the r Z 2 at the frequency of this signal receives a signal from the first frequency signal source means and a second frequency signal source is equal to the value of 1 Z 2 frequency channel spacing, the second frequency signal source at this frequency response to a signal from; r Z 2 phase amount transfer Sosuru second the consists of means, a multiplier for receiving two signals from the and be that multiplier receives the second signal first and second phase shifting means from said first and second frequency signal source a first quadrature modulator, is composed of a said two second quadrature modulator only one of the frequency signal consists of 2 groups of multiplier Ru received from phase shifting means, connected to said frequency offset circuit of claim 1 乃 optimum 1 3, characterized by further comprising a local frequency generating means Receiving circuit according to any misalignment.
. The first to phase the phase of r / 2; 1 9 and the first frequency signal source is equal to the carrier frequency of the desired reception signal, at the frequency of this signal receives a signal from the first frequency signal source It means a frequency signal source equals Chapter 2 to a value of 1/2 frequency channel spacing, in the frequency response to this signal; second means Sosuru shifting the phase of the r Z 2, wherein the first and a multiplication unit that the two signals as an input from the second notification wavenumber 倌兮 source, and means for adding an output of only one polarity to the other 乘算 devices the outputs of the multipliers of the 2 groups, consist of, the receiving circuit according to any one of 猜求 claim 1 to 1 3, especially fine to have a station ffi frequency generating means SeMMitsuru to the frequency offset circuit.
2 0. Receiving the frequency signal source is equal to the carrier ho wave number of the desired reception signal, means for phase shifting the phase of the "r Z 2 in use wave number of the signal receiving this signal, the frequency signal from the shift party stage 2 group and orthogonal transform W unit consisting multiplier, the output of only one of the multipliers of the 2 groups and means for adding the output of ffi of inverted other multiplier, the frequency O offset circuit constituted from receiving circuit according to any one of claims 1 乃 optimum 1 3, characterized in that it has a connection to the local frequency generating means.
2 1. For wavenumber conversion circuit or orthogonal first received signal and the first and second Fourier transformer receiving means for each AZD converts the second received signal, the digital output respectively obtained by the recovery Λ circuit When a correlator which receives an output for each for wavenumber components of the Fourier variables exchangers, and the weighting function unit for receiving a correlation Yasushi output obtained, a weighter for receiving the output of the weighting with the function unit, the first comprising 1 Fourier transform output and the second Fourier transform output undergoes adder, means for inputting the addition result to the multiplier, and an inverse Fourier transformer for receiving an output of said weighting value multiplier, inverse Fu receiving circuit according to any one of claims 1 to 1 3, characterized in that the Rye desired wave extraction result with a strange 换出 force.
2 2. And receiving input means for receiving a 受倌 signals from antenna, performs frequency conversion processing on the received signal from the receiving input unit, a quadrature condensate W unit for obtaining two output signals having different phases, the orthogonal recovery first and second a / D converter for Hen换 an analog signal to a Digitally Le signal to input one of the output signal from the W unit, twice the frequency corresponding to 带域 width possessed by the received 侰号enter a sampling clock generator for generating the above clock, a delay circuit for generating a Un'nobe pulse train by 遂延 a pulse train from the sampling clock generator, the other output signal from the quadrature condensate W unit third and a fourth AZD converter, the sampling clock generator a pulse train from said Un'nobe pulse train said first to fourth a / D converter for converting the analyst port grayed signal to disable digital signal sump It means for providing as Nguparusu, receiving circuit and having a means for extracting orthogonal components of the first to receive channel signal desired from the digital output data of the fourth AZD converter.
2 3. A reception input means for receiving a received signal from the antenna, performs the frequency conversion processing on the reception signal from the receiving input unit, a quadrature recovery 澜器 obtaining two output signals having different phases, the orthogonal condensate " generating first and second AZD converter for converting the analyst port grayed signals to daisy evening Le signal to input one of the output signals from the vessel, the frequency over the clock corresponding to 带域 spokes with the received signal a sampling clock production unit for the Sambu ring clock and Un'nobekai path for generating s extended pulse train pulse train from the generator s by a @, analog signals enter the other output signal from the quadrature recovery 稱器third and fourth a / D converter for converting the digital signals, sampling of the San bling clock generator wherein the pulse train and the delayed pulse train from the first to fourth a Roh D converter It means for providing a pulse, the first to fourth 慷E and means for extracting a quadrature component of the received channel signal desired from Digi tal output data of AZD converter, luck length of time of each Un'nobe circuit , before ^ Nozomu channel signal receiving circuit, characterized in that the 51 length of time other than a phase difference corresponding to r in W engagement with frequency.
2 4. The S-extended time Un'nobe circuit, receiving circuit Kokyu claim 2 2, wherein the to 邋延 when 閱 phase difference corresponding to at engagement between the frequency of the desired channel signal.
2 5. A receiver input means for receiving a received signal from the aerial 艨, a first A / D converter for performing AZ D converter to input the received signal, and a second AZD converter, these AZD conversion a sampling clock generator for Kyo耠 the reach wavenumber or more clocks corresponding to 带域 width with the 受侰 侰号 the vessel, and a circuit for adding the delay pulse train to a pulse train from the sampling clock generator, the It means for providing said delayed pulse train and the pulse train from the sampling clock generator and the first and second San bling pulse AZD converter, a digital pre-IE first and second a / D converter reception times, characterized in that it comprises a means for extracting a received channel signal desired from the output data
2 6. Receiving circuit according to claim 2 5 Symbol mounting, characterized in that a phase difference time corresponding to the relationship between the frequency of the desired channel signal 遂延 time in the circuit for adding the delayed pulse train.
That was during the time delay other than the phase difference corresponding to r; 2 7. The Kaenobe pulses provided means for ¾ sequence generator, and engaged in between the frequency of the particular desired channel signal 遲延 time of the delay pulse receiving circuit according to claim 2 5, wherein.
A reception input means for receiving a received signal from the 2 8. Antenna, a single A / D converter for performing AZ D converter to input the received signal, corresponding to a bandwidth possessed by the received signal to the AZD transducer sampling click port for supplying clock frequencies above click generator, a circuit for adding the Tsunobe pulse train to a pulse train from the sampling clock generator, a pulse train from the previous SL sampling clock generator and the 遂延 BALS column receiver circuit and having means for providing a sampling pulse of the AZ D converter, and means for extracting a received channel signal desired from Digi evening Le output data of the AZD converter.
2 9. More and a plurality of receiving input circuit for receiving a received signal from each of the air 錄, first and second frequency Hen换 means, said first and second frequency conversion means for receiving these received signals the obtained a local oscillator to provide an output at a frequency which has been subjected to 1/2 of the frequency O offset of R8 inter-frequency channels to the desired wave carrier frequency, each of the signal from the first and second frequency Hen换 means a first and second a / D converter, said first and second a / D for supplying a clock over the frequency corresponding to the bandwidth possessed by the received signal to the transducer a sampling clock generator, the sampling a circuit for adding a delayed pulse train to a pulse train from the clock generator, Sanburingupa pulse train and the delayed pulse train and said first and second AZD transducers from the Saint-bling clock pulse production unit It means for providing each as scan, receiving circuit and having a means for extracting a received channel signal desired from the digital output data of the first Oyopi second AZD transducer.
3 0. providing a local oscillator for supplying independently to the first and second frequency converting means, a second frequency offset channel ra frequencies around the desired wave carrier frequency of each local oscillation frequency was applied to the positive and negative receiving circuit according to claim 2 9, wherein the the frequency.
3 1. Supplies two received signals in said plurality of received signals to said first and second AZD converter without frequency conversion, frequency conversion function to the first and second AZD transducer receiving circuit according to claim 2 9, wherein the that imparted.
3 2. And receiving input means for receiving a received signal from the antenna, performs frequency conversion processing on the received signal from the receiving input unit, a quadrature demodulator for obtaining two output signals having different phases, from the quadrature demodulator a first a / D converter for converting the analyst port grayed signal into a digital signal by entering one of the outputs of the conversion by entering the other output signal from the quadrature condensate cocoon device an analog signal into a digital signal second and a Roh D converter, the first and the sampling clock generator to supply feeding the above clock frequency corresponding to a bandwidth having a second received signal to AZD converter, the sampling clock generator for delays the pulse train from the Un'nobe circuit for generating a Un'nobe pulse train, the Sanburinguku port Tsu pulse train from the click generator of the Un'nobe pulse train and said first and second AZD transducer It means for providing both a pump ring pulse, the first and second A
Receiver circuit and having a means to extract the quadrature components of the received channel signal desired from the digital output data / D converter.
3 3. Aerial 錄 a reception input means for receiving a 受倌 signal, performs frequency conversion processing on the received signal from the receiving input unit, a quadrature condensate W unit for obtaining two output signals having different phases, the orthogonal converting one analog signal inputs an output of the backward! W unit and the first AD converter for converting a digital signal, an analog signal into a digital signal by entering the other output signal from the quadrature unit a sampling clock generator for supplying a second a Roh D converter and said first Oyopi clock or frequency corresponding to 带域 width possessed by the received signal to the second AZD converter, the sampling clock generator delays the pulse train from the delayed pulse and a delay circuit for generating a column, the sampling black Tsu the pulse train from the click generator Un'nobe pulse train said first and second Samburu of AZ D converter Means for providing together as Guparusu, and means that to extract an orthogonal component of the received channel signal desired from the digital output data of said first and second AZD converter luck length of time of said delay circuit, said receiving circuit is characterized in that the luck length of time other than a phase difference corresponding to π in relation to the frequency of the desired channel signal.
3 4. The delay time of the delay circuit, the reception circuit according to claim 3 2, wherein the to luck length of time of the phase difference phase to those in Paizeta 2 in engagement with the frequency of the desired channel signal.
PCT/JP1995/002448 1994-11-30 1995-11-30 Receiving circuit WO1996017441A1 (en)

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JP6/297180 1994-11-30
JP29718094 1994-11-30
JP6625395 1995-03-24
JP7/66253 1995-03-24
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JP7/278513 1995-10-26

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US6236688B1 (en) 2001-05-22 grant
CN1501590A (en) 2004-06-02 application
CN1139998A (en) 1997-01-08 application
US6516038B1 (en) 2003-02-04 grant
US5914986A (en) 1999-06-22 grant
EP0742647A1 (en) 1996-11-13 application
CN1154245C (en) 2004-06-16 grant
US6600795B1 (en) 2003-07-29 grant
EP0742647A4 (en) 1999-11-24 application

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