WO1996015519A1 - Ecran video et appareil et procede de commande - Google Patents

Ecran video et appareil et procede de commande Download PDF

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Publication number
WO1996015519A1
WO1996015519A1 PCT/US1995/014417 US9514417W WO9615519A1 WO 1996015519 A1 WO1996015519 A1 WO 1996015519A1 US 9514417 W US9514417 W US 9514417W WO 9615519 A1 WO9615519 A1 WO 9615519A1
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WO
WIPO (PCT)
Prior art keywords
display
signal
locations
propagation
location
Prior art date
Application number
PCT/US1995/014417
Other languages
English (en)
Inventor
Homer L. Webb
Robert J. Gold
Dan E. Jennings
Original Assignee
Off World Laboratories, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Off World Laboratories, Inc. filed Critical Off World Laboratories, Inc.
Priority to AU41476/96A priority Critical patent/AU4147696A/en
Publication of WO1996015519A1 publication Critical patent/WO1996015519A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant

Definitions

  • Cathode ray tube (CRT) displays have been the video display standard for many years. CRT displays create images by selectively firing a cathode ray or electron beam on a surface coated with illuminating substance; the surface illuminates in response to the electron beam. In order to properly control the electron beam and produce the desired image, however, a certain distance between the electron gun and the surface coated with illuminating material is required. In most cases, cathode rays fire substantially perpendicularly to the display screen. Therefore, displays using CRT technology typically require a significant distance between the viewing surface of the display screen and the electron gun behind the display screen. Further, this technology has been criticized for emitting potentially damaging amounts of radiation from the CRT display surface.
  • Lap top computers require thin video displays to create a computer package of minimal volume.
  • One way to create a thinner video display is to discharge cathode rays from directions that are not substantially perpendicular to the display screen. When cathode rays are fired from these positions, however, controlling the cathode rays is much more difficult and an inferior video image occurs.
  • a display screen has discrete pixels of illuminating material or other material with an alterable appearance.
  • a plurality of row conductors and a plurality of column conductors Arranged on the display screen are a plurality of row conductors and a plurality of column conductors, each row and column conductor extending across the screen only once.
  • row conductors are disposed perpendicularly to column conductors.
  • the pixels are arranged so that energizing a particular row conductor and a particular column conductor causes a specific pixel to illuminate. Therefore, each pixel on the display screen is uniquely addressed by energizing a certain row and column combination. This technology, however, requires a driver for each row and column conductor.
  • DRIVER SYSTEM The Driver System (Drivers) refers to the electronic components used to introduce electrical signals to any screen architecture.
  • SA Screen Architecture
  • SCREEN GEOMETRY The Screen Geometry (SG) is the physical layout of the electrical pattern (i.e. traces) on, behind or imbedded in, the screen.
  • PIXEL ARCHITECTURE The Pixel Architecture (PA) is the physical layout of the light emitting elements (i.e. Phosphor on an EL screen).
  • PIXEL GEOMETRY The Pixel Geometry (PG) is the shape of the pixel and the way it is connected to the transmission line.
  • ELECTRICAL CONFIGURATION The Electrical Configuration (EC) is the physical relationship of the light emitting elements and the signal trace elements (electrical pathways).
  • REINFORCEMENT is the coincidence of signals along a single transmission path at a specific location causing a multiplexing effect (or summing) of electrical potential. Two or more signals must arrive at a specific location at the same time to cause Reinforcement. Reinforcement is affected by various conditions of the signal and its manipulation by the Driver System.
  • SELECTIVE CONVERGENCE Selective Convergence (SC) is the coincidence of two or more signals, on two or more paths, at one or more locations at a given point in time. SC is the basic meeting of signals to create an on-off potential at that specific location. The SC is affected by various conditions of the Driver System and the Screen Geometry.
  • REFLECTION is the capacity of a signal to reflect (or bounce back) at the end of a transmission line, causing the signal to travel back in the opposite direction of its original travel. This allows for Reinforcement of the first signal (now reflected) with a second signal on one transmission line using only one Driver.
  • a video display driver and screen embodying the principles of the present invention include a two-dimensional display screen with a plurality of display locations, a delay structure, and a signal control means, the combination of which provides for the selective activation of the display locations on the screen.
  • the display screen may employ discrete pixels of illuminating material, uniformly distributed illuminating material, gas discharge illumination, liquid crystal display technology, or other means to produce a visual signal at a display location.
  • the display locations extend throughout the display screen and produce a visual signal upon receiving an activating signal at the selected display location.
  • the delay structure associated with the display area, provides at least one path extending through each of the display locations on the display screen.
  • the delay structure directs the propagation of a first electrical signal and a second electrical signal across the display screen so that the signals may converge to produce an activating signal at any display location on the display screen.
  • the signal control structure may selectively transmit first and second electrical signals along the delay structure so that peaks of the first and second electrical signals converge to produce an activating signal at a selected display location.
  • the propagation velocity of electrical signals along the delay structure is determined by the delay structure's physical construction. Thus, each of the signals propagates along its delay structure to a specific display location in a determinable time. Therefore, by selectively timing the peaks of the second electrical signal relative to the first electrical signal, the signal peaks may be controlled to converge at a desired display location.
  • a first electrical signal propagates along a first serpentine trace forming a plurality of substantially parallel rows and providing a continuous propagation path that extends through each of the display locations.
  • a second electrical signal propagates along a second serpentine trace forming a plurality of substantially parallel rows which are oriented substantially parallel to and intervolved with the substantially parallel rows formed by the first trace.
  • the first and second trace may be in the same plane or in separate planes, above or below a plane containing an illuminating material or cell, or in any combination thereof.
  • the second trace also provides a continuous propagation path that extends through each of the display locations.
  • the first and second traces are substantially electrically isolated from each other and facilitate the convergence of the first and second electrical signals at any display location in the display area.
  • the double serpentine delay line structure includes a signal propagation delay path connected between the signal control means and the first serpentine. This delay path provides a signal delay equal to that of the entirety of the second serpentine. Therefore, when the first and second signal peaks are transmitted from the signal control means with zero added delay, the signals converge, in Reinforcement, to produce an activating signal at a display location corresponding to the extreme first end of the first serpentine and the extreme second end of the second serpentine. By selectively delaying the transmission of the second electrical signal peaks, the convergence location of the electrical signals may precisely be controlled to create a visual signal at any desired display location. In this minimal configuration, only two drivers are needed, which lowers power consumption, software requirements, and hardware requirements.
  • a first electrical signal propagates from one end of a horizontal delay line connected to a plurality of column conductors.
  • a second electrical signal propagates from the other end of the horizontal delay line. As each signal travels along the delay line, it successively excites each column conductor. When two signals converge at a point on the delay line, the signals effect a Reinforcement on the conductor at that point.
  • a third electrical signal propagates from one end of a vertical delay line connected to a plurality of row conductors.
  • a fourth electrical signal propagates from the other end of the vertical delay line. The third and fourth signals converge on the vertical delay line and reinforce on the row conductor at that point in exactly the same manner as the first and second signals.
  • the column and row conductors are multiplexed to create a grid.
  • the reinforcement will exceed a threshold activation level and a visual signal will result at the crosspoint display location.
  • the convergence location of the electrical signals may be precisely controlled to create a visual signal at any display location.
  • the selective convergence of signals at the desired display location is a signal reinforcement technique that activates a display location at the point and time of convergence.
  • This convergence activation allows significant advantages by reducing the level required of each signal to activate a display element. If a particular type of display element requires an activation voltage Va, then a system with a four driver reinforcement convergence would require driver voltage levels of 1/4 Va on two signal lines and -1/4 Va on the other two lines.
  • advantages are obtained by a reduction in the activation signal rise times. It is easier to achieve appropriate signal rise and fall times with driver signals at a level of 1/4 Va than with a single signal at a level Va.
  • a display according to the invention may incorporate non-linear activation elements in order to match display element activation characteristics to the activation signal parameters.
  • a display area such as a pixel, must respond within the width of a pulse traveling along a delay line. If a liquid crystal display cell will be utilized as the display element, it will typically require a root-mean-square (RMS) voltage of two volts (RMS) for several milliseconds, which is usually created by a pulse of approximately thirty-five microseconds. To facilitate signal widths narrower than thirty-five microseconds activating a display location, nonlinear circuits can be placed on the delay lines to stretch a pulse traveling along the delay lines.
  • RMS root-mean-square
  • non-linear elements may be utilized to facilitate pixel activation using electrical signals having small peaks.
  • a delay structure may have another driver at the end of its conductors to vary the reference voltage of the conductors, which allows an electrical signal peak with a voltage less than the threshold voltage of a pixel element to combine with the reference voltage and activate a pixel.
  • a delay structure with conductors may be configured so that one driver and one delay line are attached to one end of the conductors while another driver and another delay are attached to the other end of the conductors. This allows the peaks of the electrical signals created by the drivers to have a voltage of only half of the threshold voltage required to activate a display element.
  • a delay structure may be equipped with selected voltage boost.
  • a generator attached to the delay structure may increase the reference voltage of the delay structure.
  • the converging signals combined with the voltage boost activates a display location element.
  • Various boost and signal peak voltages may be selected to activate a display location element.
  • the present invention does not suffer from the driver expense associated with prior display devices utilizing electrical signal convergence technology.
  • the display screen may be thinly formed and constructed in a one-piece sandwiched manner. Illuminating material may be uniformly positioned across the area of the display. With this construction, the width of the display location may be controlled by varying the peak width of the electrical signals.
  • the present invention provides for a variable resolution display screen. Further, because the invention does not use cathode ray technology, less radiation is produced by the screen, reducing adverse health effects. Additionally, because the apparatus of this invention may be formed in any shape, a video display created using the principles of this invention need not be substantially flat.
  • FIGURE 1a is a diagram of a video display embodying principles of the present invention using a double or parallel serpentine delay structure.
  • FIGURE 1b is a diagram of a first signal to be transmitted along the delay structure.
  • FIGURE 1c is a diagram of a second signal to be transmitted along the delay structure.
  • FIGURE 2 is a partial cross-section diagram of a display, showing how the first preferred embodiment of a double serpentine delay structure and the display screen interact.
  • FIGURE 3 shows a driver system
  • FIGURE 4 is a partial top- view diagram of a second embodiment of a display screen including discretely disposed illuminating display locations or pixels.
  • FIGURE 5 is a partial top-view diagram of a third embodiment of a display screen including discretely disposed liquid crystal display segments.
  • FIGURE 6 is a partial cross-section diagram of a fourth embodiment of a display using a gas discharge illuminating technique.
  • FIGURE 7 is a partial cross-section diagram of a fifth embodiment of a display screen including a viewing screen coated with an illuminating material selectively energized by bombarding electrons.
  • FIGURE 8 is a top-view diagram of a single serpentine open-ended delay structure.
  • FIGURE 9 is a partial cross-section diagram of a single serpentine open-ended delay structure.
  • FIGURE 10a is a top- view diagram of a single serpentine plus surface delay structure.
  • FIGURE 10b is a partial cross-section diagram of a single serpentine plus surface delay structure.
  • FIGURE 11 is a diagram of a second video display embodying the principles of the present invention, including a display screen, a parallel serpentine delay structure, and a signal control means.
  • FIGURE 12 is a diagram of a signal to be transmitted along the delay structure of the video display in FIGURE 10a.
  • FIGURE 13 is a partial cross-section diagram of an alternate embodiment of the present invention including display continuation means.
  • FIGURE 14 is a diagram of a dual perpendicular interlaced video display screen geometry with four drivers, including a display screen, a row and column conductor delay line structure, and signal control or driver system.
  • FIGURE 14a shows a control circuit configuration
  • FIGURE 14b shows a simplified delay structure
  • FIGURE 14c shows a timing diagram for a structure according to Figure 14b.
  • FIGURE 14d shows a more complex timing diagram for a three tap delay structure.
  • FIGURE 14e shows a simplified, two delay line multiplexing screen configuration with perpendicular interlaced tap and a three by three display location matrix.
  • FIGURE 14f shows a sample timing diagram for illuminating a display location in the embodiment of Figure 14e.
  • FIGURE 14g shows an edge bonded delay and tap structure.
  • FIGURE 14h shows a center bonded delay and tap structure.
  • FIGURE 14i shows a plane bonded delay and tap structure.
  • FIGURE 14j shows a serpentine delay with non-delayed taps.
  • FIGURE 14k shows a serpentine delay with alternating legs extending through four display element columns.
  • FIGURE 15 is a partial cross-section diagram of a display with a slab delay structure and row and column conductors.
  • FIGURE 16 shows a staggered delay structure
  • FIGURE 17 shows a three input boosting, time delayed structure.
  • FIGURE 18 shows a dual supply RMS driver configuration.
  • FIGURE 18a shows a four supply RMS driver configuration.
  • FIGURE 19 shows a multiple tap delay structure slab construction.
  • FIGURE 20 shows an equivalent circuit schematic for the construction of Figure 19.
  • FIGURE 21 shows a slab delay structure configuration with electrical taps and selective interconnects.
  • FIGURE 22 shows a slab delay structure with discrete interconnects.
  • FIGURE 23 is a diagram of a liquid crystal display segment with a nonlinear circuit.
  • FIGURE 24 shows an example of application of non-linear circuits to a passive matrix design.
  • FIGURE 25 shows a simplified display with back-to-back Zener diodes connected to each display element.
  • FIGURE 26 shows a cross-sectional view of a display element architecture.
  • FIGURE 27 shows a three dimensional perspective view of the display element architecture.
  • FIGURE 28 shows a screen architecture using thin film transistors.
  • FIGURE 29 shows a diode bias display element.
  • FIGURE 30 shows a three by three matrix with diode bias display elements.
  • FIGURE 31 shows an exploded view of a dual parallel serpentine delay structure architecture.
  • FIGURE 32 shows an exploded view of a propagation structure for a dual perpendicular interlaced display geometry for a gas discharge type display.
  • FIG. 1 A simplified video display with two drivers is shown in Figure la and includes a two-dimensional display 12, delay structure 14 and signal control means 16.
  • the display 12 is made up of a plurality of display locations across display area 18. A selected display location produces a visual signal on display 12 upon coincidence of activating signals at the display location at a determinable time.
  • a display panel may be composed of a plurality of display areas 18, each having its own associated control and driver structures.
  • Delay structure 14 is associated with display area 18 and provides a propagation path extending to each of the display locations on the display area.
  • Delay structure 14 directs the propagation of electrical signals across display area
  • the physical configuration and materials of the delay structure controls the propagation velocity of the signals.
  • Signal control block 16 selectively transmits electrical signals along delay line structure 14 so that the electrical signals converge and reinforce to produce an activating signal level at a selected display location at a determinable time.
  • the simplified embodiment of a double serpentine delay structure 14 includes first serpentine delay structure 20, second serpentine delay structure 22, and signal delay path 23.
  • the signal delay path 23 may be an active or passive discrete delay element with a predetermined propagation delay equal to the propagation delay time of a signal traversing the display area on one of the delay structures.
  • First delay structure 20 forms a plurality of substantially parallel rows and provides a continuous propagation path extending through each of the display locations in display area 18.
  • Second delay structure 22 forms a plurality of substantially parallel rows oriented substantially parallel to and intervolved with the substantially parallel rows of first delay structure 20.
  • Second delay structure 22 also provides a continuous propagation path that extends through each of the display locations in display area 18.
  • First and second delay structures 20, 22 are substantially electrically isolated from each other and converge at each of the display locations in display area 18.
  • signal control block 16 comprises first driver 34, second driver 36, signal delay generator 38, and control circuitry 40.
  • Control circuitry 40 selectively causes first driver 34 to produce first electrical signal 42 of selected voltage 44 and selected peak width 46 as shown in Figure 1b. First electrical signal 42 propagates along first delay structure 20.
  • Control circuitry 40 also causes second driver 36 to produce second electrical signal 48 of selected voltage 50 and selected peak width 52 as shown in Figure 1c.
  • Control circuitry 40 also causes signal delay generator 38 to delay the transmission of second electrical signal 48 from second driver 36 by a selected interval. In operation, neither first nor second electrical signal 42, 48 is of sufficient voltage to cause the conduction of electricity across illuminating material 24.
  • electrical signals 42, 48 produce an activating signal which activates the display material 24 at the selected display location. Because the signals only reinforce when they converge along delay structure 12, a display location is selected by variably delaying the transmission of second electrical signal 48 from second driver 36 relative to the transmission of first electrical signal 42 from first driver 34.
  • delay structure 14 includes signal delay path 23.
  • Signal delay path 23 introduces a propagation delay equal to the time that it takes for second electrical signal 48 to propagate along the entirety of the second delay structure 22.
  • first and second electrical signals 42, 48 converge to produce an activating signal at an extreme first end of first serpentine delay structure 20 and an extreme second end of second serpentine delay structure 22.
  • the convergence location corresponds to the extreme upper left portion of display area 18.
  • signal delay generator 38 delays second electrical signal 48 by a time period equal to twice the length of time that it takes for first electrical signal 42 to propagate along the entirety of the first delay structure 20, electrical signals 42, 48 converge to produce an activating signal at the extreme second end of first serpentine delay structure 20 and the extreme first end of second serpentine delay structure 22, such location corresponding to the extreme lower right portion of display area 18.
  • An activating signal may be produced at other display locations in display area 18 by causing signal delay generator 38 to delay transmission of second electrical signal 48 relative to the transmission of first electrical signal 42.
  • signal delay generator 38 may be controlled to delay transmission of second electrical signal 48 relative to the transmission of first electrical signal 42.
  • FIG. 1 shows a pixel architecture in partial cross-section of a possible construction of display area 18 of a double or parallel serpentine delay line structure.
  • the first preferred embodiment of display 12 may employ an illuminating material 24 that activates when electrified, a transparent protective cover 26, an insulating substrate layer 28, and grounded conducting layer 30. Illuminating material 24 is disposed substantially uniformly across the display area.
  • first and second delay structures 20, 22, as shown in this drawing, is a display location.
  • illuminating material 24 conducts electricity and is activated.
  • Grounded conducting layer 30 ensures the uniform propagation of electrical signals along first and second delay structures 20, 22.
  • Insulating substrate layer 28 prevents the conduction of electricity from first or second delay structures 20, 22 to grounded conducting layer 30.
  • FIG 3 is a simplified example of driver system 16 shown in Figure 1.
  • the propagation delay of the signals through the screen 14 may be designed to be the same as the typical scan rate of a video display.
  • the typical scan rate of the video data is approximately 54.25 nanoseconds per pixel.
  • the circuit 40 generates a trigger pulse 40a whenever the Video Data are VALID (pixel is to be lit).
  • the pulse 40a triggers a pulse generators 34.
  • the output of the pulse generator 34 is pulse 42 illustrated in Figure 1b, which travels down the transmission element 20.
  • Pulse 40a also triggers a delay circuit 38.
  • the output of the delay circuit pulse 38 is delayed by an amount appropriate to synchronize the arrival of activation signals at a selected display location. This will be explained below.
  • the output 38a from the delay circuit 38 triggers the pulse generator 36.
  • the pulse generator 36 generates pulse 48 illustrated in Figure 1c.
  • the pulse 42 is delayed by element 23 the same amount of delay that pulse 48 takes to traverse from the lower portion of screen 14 to a pixel location 1, located in the upper left hand corner of screen 14.
  • the pixel lights and absorbs both pulses 42 and 48.
  • the activation sequence for signal 40 will be 1,1,0,1 as illustrated in Figure 3.
  • the display has n display locations and the propagation time between adjacent display locations is equal to the period of the dot clock.
  • the delay imposed by th delay circuit 38 will be the dot clock period multiplied by 4*(n-1). The delay is required to synchronize the convergence of activation signals at the selected locations. If activation signals converge at a display location a at time t 1 activation signal 42 selected for location a+1 is at location a-1 and activation signal 48 selected for location a+1 is at location a+3.
  • the activation signals for location a will have been absorbed, activation signal 42 selected for location a+1 will have propagated to location a and activation signal 48 selected for location a+1 will have propagated to location a+2.
  • the activation signals 42 and 48 selected for location a+ 1 will converge and reinforce at that location.
  • the delay circuit 38 may be responsive to the Dot Clock signal and/or the SYNC signal in order to reduce the counting and timing structure to impart the appropriate delay. Accordingly, the sequential delay for the locations 1, 2 and 4 will be 0, 4 and 12 dot clock periods, respectively.
  • Figure 4 shows a second pixel architecture for a display 12.
  • Discretely disposed pixels 116 are located at each display location so that first and second signals 42, 48 can converge to produce an activating signal at a selected discrete display location.
  • Each illuminating pixel emits at its respective display location upon receipt of an activating signal.
  • Pixels are bounded by first delay structure 20, second delay structure 22, and electrically insulating boundaries 118, forming a discrete display location.
  • a transparent protective cover is not shown in this top view.
  • a color monitor may easily be constructed. Pixels of red, blue, and green illuminating material may be discretely disposed at the display locations so that signal control means 16 selectively illuminates colored pixels to create a color visual image.
  • Figure 5 shows a third pixel architecture and geometry for a display 12.
  • Discretely disposed liquid crystal diodes 120 are located at each display location so that first and second signals 42, 48 can converge to produce an activating signal at each display location.
  • Each liquid crystal changes visual appearance at its respective display location upon receipt of an activating signal.
  • the discretely disposed liquid crystal cells 120 are bounded by first and second delay structures 20, 22.
  • display 12 does not produce visual light, but instead, alters visual appearance at each display location where an activating signal is produced.
  • FIG. 6 shows a fourth pixel architecture and geometry for a display 12.
  • Gas discharge illumination means are located at each display location and emit light upon receipt of an activating signal at the selected display location.
  • Gas discharge illumination means includes gas filled cavity 122, the gas in the cavity producing ultraviolet radiation when electrical arc 124 conducts across it.
  • Arc 124 is produced when the first and second electrical signal 42, 48 converge at the selected display location to produce an activating signal.
  • the ultraviolet radiation causes illuminating pixel element 126 to produce visible light.
  • Transparent cover 128 protects the structure.
  • Non-conducting screen base 130 contains the gas within cavity 122 and allows first and second delay structures 20, 22 to be deposed.
  • Mounting substrate 132 preferably provides protection and rigidity to the structure. With this embodiment, a color monitor can easily be constructed. Illuminating pixel elements 126 of red, blue, and green colors can be discretely disposed at the display locations so that signal control means 16 can selectively illuminate colored pixels to create a color visual image.
  • Figure 7 shows a fifth pixel architecture and geometry for a display 12.
  • the Figure illustrates a partial cross-section diagram.
  • Viewing screen surface 162 is preferably coated with phosphor material 160, but it could be coated with another material that emits light when bombarded by electrons.
  • Viewing screen surface 162 serves as an anode.
  • First delay structure 20 includes low work function coating 164 that facilitates the escape of electrons from the delay structure.
  • First delay structure 20 is preferably nearer to viewing screen surface 162 than second delay structure 22.
  • the delay structures are separated by insulating layer 166, and the delay structures are supported by insulating substrate layer 28.
  • This embodiment of display 12 is selectively activated by the convergence of first signal 42 with negative polarity and second signal 48 with negative polarity.
  • first and second signals 42, 48 converge at a selected location, they reinforce and the combined voltage on first and second delay lines 20, 22 causes electrons to escape from first delay structure 20 at the selected location.
  • the electrons are attracted by viewing screen surface 162 which acts as an anode. Resultantly, the electrons collide with illuminating material 160 on viewing screen surface 162, causing the illuminating material to emit light.
  • this apparatus using an anode and a cathode to cause the selective emission and bombardment of a screen by electrons are possible.
  • Figure 8 is a top-view diagram and Figure 9 is a partial cross-section diagram of a third screen architecture designated as a single serpentine.
  • the delay structure 14 includes single serpentine delay structure 138 forming a plurality of substantially parallel rows and providing a continuous propagation path that extends through each of the display locations in display area 18.
  • delay structure or trace 138 is an open-circuit terminated so that a first signal propagating along the trace will fully reflect when it reaches the end of the delay structure.
  • a second signal is also transmitted over the delay structure 138.
  • the selective convergence of first and second electrical signals 42, 48, propagating and reflecting along delay line 138 produces an activating signal.
  • Figure 9 shows a pixel architecture for a single serpentine screen geometry where illuminating material 24 forms a path through which electricity may propagate from a location along delay structure 138 to either grounded propagation layer 140 or to another location along the delay structure depending upon the polarity of the signals propagating along delay structure 138.
  • This embodiment also preferably includes protective cover 26 and insulating substrate layer 28.
  • Grounded propagation layer 140 preferably in the form of a transparent conductor or alternatively a fine conductive grid which does not interfere with the display, in addition to providing a return path for the conducted electricity also enables the uniform propagation of first and second electric signals 42, 48 along delay line 138.
  • an activating signal may be produced in one of two ways using this single serpentine embodiment of a delay line structure. If both first and second electrical signals 42, 48 have a positive voltage, the signals converge at a single physical point along delay structure 138 and reinforce to produce a voltage of sufficient magnitude to cause conduction across illuminating material 24 to grounded propagation layer 140, causing illuminating material 24 to emit light. If first electrical signal 42 has a positive voltage and second electrical signal 48 has a negative voltage, the signals will produce a voltage potential and create an activating signal when they pass near each other, each signal at a different location along delay line 138. In this case, electricity conducts from one portion of delay structure 138 to another portion of the delay line through illuminating material 24 thereby producing an activating signal.
  • Figure 10a is a top view diagram and Figure 10b is a partial cross-section diagram of an alternative single serpentine screen architecture.
  • the delay structure 14 includes a serpentine delay line 138 forming a plurality of substantially parallel rows and providing a continuous propagation path that extends through each display location.
  • This embodiment also includes surface propagation means 141 substantially electrically isolated from and substantially coextensive with delay structure 138 across display area 18. Surface propagation means 141 enables second electrical signal 48 to propagate substantially uniformly across display area 18.
  • surface propagation means 141 preferably takes the form of a transparent conductor grid.
  • first electrical signal 42 propagates along delay line 138.
  • Second electrical signal 48 propagates along surface propagation means 141 so that the signals converge to produce an activating signal at a selected display location.
  • Illuminating material 24 forms a path through which electricity may conduct to surface propagation means 141 when an activating signal is produced at a display location.
  • This embodiment also includes protective cover 26 and insulating substrate layer 28.
  • Surface propagation means 141 in addition to directing second electrical signal 48, also enables the uniform propagation of first electric signal 42 along delay line 138.
  • Surface propagation means 141 may be constructed in such a manner so that second electric signal 48 propagates uniformly along one dimension of the screen thereby making the selective convergence of signals easier to control.
  • the propagation characteristics of the surface propagation layer 141 may be significantly different from the propagation characteristics of the delay line 138.
  • the delay line 138 may exhibit a propagation velocity which is significantly slower than the signal propagation velocity along the surface conductor 141.
  • the apparatus of the present invention also includes an alternate signal control block 16.
  • this signal control block 16 is described in combination with a parallel serpentine screen geometry of Figure 1.
  • the second signal is twice as long as second delay of delay structure 22, when the first signal reaches the extreme lower right portion of display area 18, it converges with the end of the second signal.
  • the width of the individual negative peaks and their location along the second signal train are selected so that selected display locations illuminate to produce a visual image.
  • Each display location on display area 18 may be updated at a rate that is dependent only upon the duration of the second signal. For example, suppose it takes 10 microseconds for the second signal train to propagate along the entirety of second delay structure 22. In that case, the trailing edge of the second signal propagates to second terminating resistor 112 approximately 20 microseconds after the leading edge of the second signal begins to propagate along second delay structure 22. Because both the first signal and the second signal must have exited display area 18 before more signals may be transmitted along the traces, the video display may be updated every 20 microseconds. A standard television screen updates approximately once every 33 milliseconds.
  • the first signal is advantageously a pulse train or a modulated train so that, as the leading pulses are dissipated by display location activation, there are additional following pulses that will coincide with the second signal pulses to activate other display locations on the propagation path. If the display elements which make up the display are non-dissipating elements, then the first signal may be a single pulse and the second signal may be a modulated video input signal.
  • a high frequency oscillator 142 produces a sine wave with a selected frequency of oscillation.
  • Oscillator 142 has a frequency that produces a sine wave with a narrow width.
  • the oscillator output connects into divider 144.
  • the output of divider 144 is a sine wave with a period equal to twice the propagation delay along second delay structure 22.
  • the divider output is then put into pulse generator 146, triggering the pulse generator on a negative to positive zero crossing.
  • pulse generator 146 produces a narrow pulse, the period equal to twice the propagation delay along second delay structure 22.
  • the output from pulse generator 146 is then put into first pulse transistor driver 80 which drives first delay structure 20.
  • the output from high frequency oscillator 142 is also put into second signal modulator 148 along with an input video modulation signal 147.
  • the output from second signal modulator 148 shown in Figure 12, is then put into second pulse transistor driver 110, the output from which drives second delay structure 22.
  • the signal driving second driver 110 potentially can produce an activating signal at any display location.
  • the selective disablement by modulation of individual portions of the second signal facilitates the selective enablement and partial enablement of each display location across the display area, thus creating a visual image.
  • the apparatus of the present invention may also include a display continuation means for enabling display screen 12 to produce continued display signals after receipt of activating signals at selected display locations.
  • Figure 13 shows a partial cross-section diagram of an embodiment of delay structure 16 including display continuation means.
  • two energized traces 150 are positioned opposite each delay line 138.
  • Energized traces 150 are energized at a voltage relative to the grounded conducting surface. The voltage on traces 150 is below the level of the activating signal but is large enough to cause the current through illuminating material 24 to continue to flow once an activating signal has initiated current flow through illuminating material 24.
  • Grounded propagation layer 149 allows current to flow from each energized trace through illuminating material 24 until a deactivating signal is applied across that particular display location.
  • the deactivating signal is a negative voltage signal applied to the particular display location, which causes the current flow through the illuminating material at that location to cease.
  • Figure 14 shows a diagram of a four-driver embodiment with display screen
  • the delay structure of the four-driver embodiment includes horizontal delay line 20 connected to a plurality of parallel column conductors or taps 20-1, 20-2, ..., 20-N.
  • the column conductors are non-delay conductors, i.e., the propagation velocity across the column conductors of taps is extremely fast compared to the delay line propagation velocity.
  • Column conductors 20-1, 20-2, ..., 20-N are terminated to prevent reflections.
  • Vertical delay line 22 is connected to a plurality of parallel row conductors 22-1, 22-2, ..., 22-N. Row conductors 22-1, 22-2, ..., 22-N are also grounded to prevent reflections.
  • the horizontal delay line with column conductors is disposed perpendicularly to the vertical delay line with row conductors and are substantially electrically isolated from each other.
  • the resultant structure creates a matrix with a unique row conductor and column conductor combination corresponding to each display location in display area 18.
  • the signal driver system 16 includes first driver 33, second driver 34, third driver 35, fourth driver 36, and control circuitry 40.
  • Control circuitry 40 selectively causes first driver 33 to produce a first electrical signal which propagates along horizontal delay line 20 in a particular direction.
  • Control circuitry 40 also causes second driver 34 to produce a second electrical signal which propagates along horizontal delay line 20 in the opposite direction from the first electrical signal.
  • control circuitry 40 causes third and fourth drivers 35, 36 to produce electrical signals which propagate along vertical delay line 22 in opposite directions.
  • each electrical signal created by drivers 33, 34, 35, 36 is of insufficient voltage to cause the conduction of electricity across illuminating material 24.
  • the four electrical signals can produce an activating signal which causes electricity to conduct across illuminating material 24 and causes the illuminating material to emit light.
  • first and second drivers 33, 34 travel along horizontal delay line 20, they place a voltage on consecutive column conductors along their delay line.
  • the amplitudes of the signals reinforce and the conductor at that point has a voltage which reflects the reinforcement of the first and second signals.
  • signals from the third and fourth drivers 35, 36 travel along vertical delay line 22 and reinforce at selected points on the delay line.
  • the row conductor at a point of convergence has a voltage which reflects the reinforcement of the third and fourth signals. If the convergence of all four signals, as conducted by the row and column conductors, reaches the threshold activation voltage at a display location, the pixel located at that display location illuminates.
  • the reinforcement and convergence points may be controlled to cause illumination at any display location.
  • FIG 14a is a detailed diagram of an embodiment of Driver circuit 40.
  • RAM 343 holds the video pattern for the display 14. To simplify the description, a single bit set to a logic "1" in RAM 343 will be presented on the display 14 as an active pixel 12.
  • a ROM 341 is selected to operate in parallel to the RAM 343. The ROM 341 can be replaced by a sequencing circuit but is used here for simplification of the operational description.
  • the video data pattern is in RAM 343.
  • the clock 344 generates a clock signal 344a which causes the RAM/ROM address counter 342 to increment.
  • the clock 344 is also connected to a pulse width control circuit (optional) which outputs a pulse 345a of a width selected by the control circuitry 345.
  • the pulse width control circularity also has an input 346e which is generated from ROM 341. The purpose of the 346e bits are to select the pulse width (optional) for gray scale which will not be described here but which is a standard pulse width controlled gray scale method.
  • the pulse 345a connects to logic gates 347-350.
  • the signals 346a-b follow the video pattern in the RAM 343.
  • the signals 346c-d follow the pattern in the ROM 341.
  • the RAM 343 outputs are timed to correspond to every Column 20-1 through 20-N. If the bit is set, the Column is activated.
  • the ROM bit pattern is set to generate a row activation sequence of pulses 346c-d to meet initially at ROW 22-1 when all the column bits are in the transmission structure 20.
  • the sequence column bits 346a stored in the RAM intended for a given row are in reverse sequential order from the sequence of column bits 346b intended for that row. This causes all selected bits in ROW 22-1 to activate simultaneously. The process is repeated for the next ROW 22-2 through ROW 22-N.
  • the timing between signals 346a-b and 346c-d is as described in figure 14b. This is accomplished by the relative location of corresponding bits 346a and selected to converge at predetermined display locations as stored in the RAM.
  • the relative bit position of corresponding display location bits 346a to 346b and 346c to 346d is always fixed and simplifies the design of controller 40. If the transmission structures are designed to operate at the video data input rate, the RAM can be eliminated and simpler delay circuits can be employed as previously described.
  • Alternative control arrangements are considered equivalent if they deliver a sequence of bits or other signals intended to converge at a uniquely selected combination of display locations.
  • the implementing circuitry may vary without departing from the scope and intent of the invention.
  • the ROM may be replaced by any sequencing circuit that will sequentially activate each row when the full combination of column signals for a designated row are present.
  • FIG 14 takes advantage of the superposition or reinforcement of two signals from opposing ends of the delay line 20.
  • Figure 14b shows a detail of a simplified delay line illustrating the concept of convergence. Convergence is the summing or reinforcement of amplitudes of two or more waves or pulses timed to meet at a specific location along a transmission medium.
  • the transmission medium may be any material or architecture that permits controlled propagation velocity of a wave or pulse such that two or more signals can be timed to meet at specific locations along the medium.
  • the medium may be a surface or a line of transmission material.
  • the transmission material may be a pair of wires, a coaxial wire, a wave guide, a strip line, a microstrip, a surface acoustic wave, a semiconductor carrier mobility, pizeo material, ferrous material, lumped inductors and capacitors, or any combination thereof.
  • the transmission medium may be constructed such that the activation signal, in forms of a wave or pulse, travels along the plane or along routed lines simulating a surface or combinations of delay transmission lines or planes, with connections to form a surface that promotes a selection of display locations or pixels arranged on a surface or any device connecting pixels attached to the transmission path.
  • the display elements or pixels may be light emissive elements such as luminescence, reflective or refractive elements.
  • a dual input reinforcing signal delay line may include two activation signal generators 241 and 242.
  • the activation signal generators may, for example, generate voltage pulses Vp1 and Vp2.
  • the generators are connected at opposite ends of a transmission line.
  • One of the signal generators may be a modulated signal generator configured to generate a stream of activation signals for each transmission sequence.
  • the delay line is a lumped delay line made up of delay elements 243.
  • the delay elements may be segments of a uniform continuous delay line.
  • the delay elements may consist of discrete delay elements which are situated off panel and connected by wire or non-delay leads.
  • Taps 244 may be connected to the transmission line between the delay elements 243. The taps are distributed on the delay line at delay intervals such that the width of the activation signal pulses, when centered on any one tap, does not overlap the next tap. In actual practice, a far greater number of taps and delay elements may be located along a delay line than illustrated in figure 14b.
  • the propagation delay of the transmission line is extremely slow compared to the propagation delay of the tap lines.
  • the tap lines be constructed to have no effective delay relative to the transmission along the delay line, and that the voltage signal Vp1 and Vp2 be present on the entirety of taps 244-1, 244-2 and 244-3 during the time period that it takes for the signals Vp to pass the tap line connection points on the delay line.
  • the delay structure may be made up by a high speed data bus connected to the non-delay taps by switches controlled by a vertical sync pulse propagated through a series of serially connected integrated delay elements.
  • FIG 14c shows a timing diagram illustrating the operation of the transmission lines.
  • Vp1 and Vp2 enter the ends of the transmission line at time t0.
  • time t1 equal to the delay imposed by one of the delay elements 243, the signal will travel through the delay element to tap 244-0.
  • Vp2 travels through a delay element to tap 244-2.
  • Vp1 and Vp2 meet at tap 244-1.
  • the superposition of Vp1 and Vp2 reinforces the voltage level additively, since both Vp1 and Vp2 are of the same polarity.
  • signal Vp1 has moved to tap 244-2, and Vp2 has moved to tap 244-0.
  • both Vp1 and Vp2 have cleared the transmission line.
  • the voltage pulse doubled only at time t2 at tap 244-1. All other taps received a pulse amplitude equal, at most, to Vp1 and Vp2.
  • Figure 14d shows a timing diagram for a complex pulse generating system.
  • two pulses are time to start and meet at tap 244-1 at time t2.
  • pulse Vp2 continues to travel to tap 244-0 and pulse Vp1 continues to travel to tap 244-2.
  • Signal generator 241 generates a new pulse Vp1N at time t2, which meet Vp2 at time t3 at tap 244-0.
  • signal generator 242 also generates a new pulse Vp2N, which will in turn meet original Vp1 pulse at tap 244-2 at time t3.
  • the signals continue and Vp1N converges with Vp2N at tap 244-1.
  • This complex pulse configuration illustrates that a voltage doubling convergence can be generated at more than one tap in the time it would take for a signal to propagate the entire length of the transmission line.
  • the doubling of pulses along the taps of the first transmission line can coincide with pulse doubling along taps of a second transmission line which may be oriented in a perpendicular geometry to the first transmission line in order to activate specified locations.
  • the coincidence of signals at differing taps along a transmission line can be controlled by affecting the timing of the signal generation.
  • Figure 14e illustrates a simplified parallel interlaced screen geometry with dual input lump delay transmission lines.
  • the taps of the horizontal transmission line 240 make up the columns and the taps of the vertical transmission line 245 make up the rows of the display area.
  • the display locations or elements are located at the XY junctions of the array.
  • the illustrated example shows only a three by three matrix for simplicity. However, much larger matrices are possible and contemplated.
  • the characteristics of the elements of the system are as follows.
  • Each display element has an activation threshold, Va, that is greater than three times but less than four times the amplitude of a non-reinforced signal Vp placed on the transmission lines.
  • the activation threshold voltage, Va is the minimum voltage required to activate a display element.
  • the convergence of three signals Vp will not be sufficient to activate the display location. However, the convergence of four will be sufficient to activate the display location.
  • the tap to tap delay is two times the pulse width of signal Vp.
  • the pixel element will respond to the pulse width being used. Additional circuitry may be provided to capture and hold a threshold activation signal level at the proper threshold to eliminate any requirement that the transmission line activation signals be present for the required element activation time period. Furthermore, since the activating voltage across a display element is the sum of the absolute voltages, the signs of the voltage signals are eliminated in order to simplify the description of the operation.
  • Figure 14f illustrates the signal timing required to activate the center pixel 5.
  • the activation pattern to light display location 5 requires simultaneous transmission of pulses Vp1 and Vp2 from either end of transmission line 240 and simultaneous transmissions of pulses Vp1-1 and Vp2-1 from either end of transmission line 245. All four signals are transmitted at time t0.
  • pulse Vp1 has reached column 1 and pulse Vp2 has reached column 3.
  • Pulse Vp1-1 transmitted from driver 241-V has reached row 1
  • pulse Vp2-1 from driver 242-V on transmission line 245 has reached row 3.
  • the column signals place a voltage on pixels 1, 4, 7 and 3, 6, 9.
  • the vertical delay line 245 puts a voltage on display elements 1, 2, 3 and 7, 8, 9.
  • Display elements 1, 3, 7 and 9 are all subjected to activation signals of two times Vp.
  • Display locations 4 and 6 each area subjected to only Vp. These voltage levels are all too low to activate any display location.
  • Vp1 and Vp2 converge at tap 244-1 and present a voltage level of 2 times Vp on column 2, display locations 2, 5 and 8. No voltage levels are presented on columns 1 and 3.
  • signals Vp1-1 and Vp2-1 converge at row 2 and present a voltage level 2Vp on row 2, display locations 4, 5 and 6. No voltage levels are presented at rows 1 and 3.
  • the combined voltage levels at display locations 2, 4, 6 and 8 are 2Vp and are insufficient to activate any of those display locations.
  • Display locations 1, 3, 7 and 9 receive no activation voltage, and display location 5 is presented with an activation voltage of 4Vp.
  • the activation level 4Vp exceeds Va and is sufficient to cause illumination at display location 5 as the result of the 4-way convergence and reinforcement of voltage signals. No other display location is activated.
  • Vp1 has moved to column 3
  • Vp2 has moved to column 1
  • Vp1-1 has moved to row 3
  • Vp2-1 has moved to row 1.
  • the voltage level at display locations 1, 3, 7 and 9 have exceeded 50% of the threshold voltage level Va but have not reached such threshold level.
  • Display locations 2, 4, 6 and 8 are each presented with a voltage level Vp, which is also not sufficient to activate any display locations.
  • all pulses have cleared the display area and a new pulse sequence may be initiated. The new pulse sequence can be used to illuminate the next selected display location.
  • Selecting a single display location may be accomplished by merely selecting the relative timing of four simple pulses transmitted through each of the four drivers. It will be apparent that utilization of more complex activation signals can activate all selected locations along a selected column in a single column or row without activating any non-selected display locations. If, for example, it is desired to activate the selected location along row 1, a modulated signal reflecting the desired locations is transmitting from driver 241-H. If, for example, display locations 1 and 2 are selected for row 1, the signal transmitted would be a pulse stream 0il. A serially reversed pulse stream will be simultaneously transmitted from driver 2142-H, i.e., 110.
  • a row 1 activation sequence will be transmitted from driver 241-V and a serially reversed sequence from driver 242-V, i.e., 001 and 100 respectively.
  • driver 242-V i.e., 001 and 100 respectively.
  • a threshold voltage of 4Vp will be present at display locations 1 and 2.
  • any display locations be subject to a voltage level of greater than 3 Vp and no other display locations will be activated.
  • a single transmission sequence of two times the total propagation delay of each delay line will be sufficient to activate all selected locations in any column or row.
  • the row activation time is two times the elemental delay times (the number of columns, X, plus 1).
  • the total frame time will be the row activation time times the number of rows.
  • a VGA display is 640 columns by 480 rows.
  • the display would have two transmission lines, the column line would have 640 taps separating 641 delay elements, and the row line would have 480 taps.
  • the delay elements may be discrete or continuous delay elements.
  • the standard frame rate for a VGA display is 16.67 milliseconds. The display area must be filled within the standard frame rate time.
  • Row rate frame rate/(rows)
  • the clock rates required to control a display according to this embodiment may be calculated by the inverse of the elemental delay. 1/54.17 X 10 -9 sec equals 18.46 MHz. Those or ordinary skill in the art will recognize that this rate is easily attainable with today's commercially available components.
  • the timing requirements could be relaxed by dividing a display into a number of display areas, each having its own row and column delay lines.
  • a standard VGA display could be divided twelve display areas resulting in a four by three matrix of sub areas each 160 columns by 160 rows. According to the above formulas, the elemental delay would be 647 ⁇ sec and requiring a clock rate of only 1.55 MHz.
  • the transmission lines composed of delay elements may be arranged in a number of ways. Discrete delay elements may be located on or off of a display panel in a number of configurations.
  • Figure 14a shows an edge bonded delay line 245 with non-delay tap lines 244.
  • Figure 14h shows a center bonded delay line 246 with non-delay taps, and 14i shows a plane bonded delay 247, with a plurality of taps 244.
  • These delay and tap line configurations may be combined in any fashion resulting in a dual perpendicular interlaced tap line screen geometry.
  • the delay lines 245, 246 or 247 have the characteristic of providing for a series of elemental delays between each tap line.
  • the elemental delays may be the result of a segregated continuous delay by tap line connections or may be discrete elemental delays.
  • Lumped delay refers to elemental delays between tap lines whether the delay line is made up of discrete delay elements or is a continuous delay transmission line. In some applications, it may be desirable to have the delay elements integrated into the display panel. If the elemental delay requires a delay element which is larger than the display element pixel pitch, other configurations may be utilized.
  • Figure 14j shows a serpentine delay transmission line 248, with three non-delayed taps 244, each extending through a four-element column of display locations.
  • Figure 14k shows a serpentine delay transmission line 249, where alternating legs of the transmission line extend along four display element columns.
  • Figure 15 shows a partial cross-section diagram of the slab construction implementing horizontal delay line 20 in the four-driver preferred embodiment.
  • an additional slab is provided for the vertical or column delay line, and two additional slabs may be provided for each of the display areas.
  • Each delay line is composed of a serpentine propagation path, sandwiched between ferrite, dielectric and copper layers as shown in Figure 15.
  • the serpentine propagation path may be fabricated from conducting material and may protrude beyond the edges of the sandwich layers for ease of making connections to the display panel taps.
  • Grounded conducting layers 30, 31, advantageously metal or highly conductive layers, enable uniform propagation of the two electric signals created by drivers 33, 34 along delay line 20.
  • Dielectric layers 28, 29 separate conducting layers 30, 31 from ferrite layers 26, 27.
  • the ferrite layer may be sandwiched with or impregnated in printed circuit board material.
  • Edges 136 of the delay line propagation path provide a connection site to column conductors.
  • Vertical delay line 22 would be constructed identically, but oriented perpendicularly, to horizontal delay line.
  • a transmission line with a selected propagation velocity may constructed for the delay lines by appropriate selection of materials. By matching the velocity of propagation of the delay line to the video signal, line rate memory buffers may be avoided, and a video signal may be amplified and placed directly on a display.
  • the velocity of propagation of an electrical signal transversing a delay line is given by the relationship:
  • V p C divided by the square root (ur*er)
  • the velocity of propagation V p can be as low as 139.47 X 10 3 inches per second.
  • strip line methods of adding distributed capacitance and inductance can further slow propagation speed by changing the shape of a conductor trace to increase the capacitance and inductance of the trace.
  • a transmission line timing technique is utilized to select a display area row or column. This operates as a time dependent multiplexer from a source to a selected one of multiple output lines.
  • the output lines are referred to as "taps" in the instant application.
  • the current concept can be applied to other multiplexing applications outside of the display device field. According to the invention, a significant advantage is obtained by relying on signal reinforcement as a result of selected convergence of signals to select a desired tap or output.
  • a selection arrangement with a two-signal reinforcement scheme could be applied with a single transmission line being connected with a single driver on one end and terminated with a grounding resistor or other signal sink.
  • the second signal input could be a direct enable or multiplex input.
  • Signal convergence to reinforce an activation signal at a selected location is possible with a single delay transmission line and drivers at opposing ends as described above or with a first driver connected at a first end and a reflective termination provided at a second end of the transmission line.
  • a shorted termination will result in a traveling pulse being reflected negatively from the unterminated end of the transmission line.
  • a first positive going pulse is transmitted, followed by a negative going pulse.
  • the positive going pulse when reaching the open termination, will be reflected negatively in the opposite direction on the transmission line and will reinforce the second pulse upon coincidence at a selected location controlled by the relative timing of the pulses.
  • a first end of a transmission line may be connected to a driver circuit while the second end is terminated in an open connection.
  • the open termination will result in a positive reflection of a transmitted signal in the opposite direction.
  • two pulses may be transmitted by the driver and timed so that the first pulse passes entirely through the transmission line and is reflected at the grounded termination in the opposite direction.
  • the second pulse is transmitted to coincide with the reflected first pulse at a selected location.
  • the point of coincidence has a pulse reinforcement which will be an activation signal, either alone or in connection with an additional enabling input, either through a direct input technique or a second transmission line time selection technique.
  • Figure 16 shows an alternative delay line tap configuration where the taps are arranged in non-uniform or staggered delay locations.
  • a first activation signal generator 151 and a second activation signal generator 152 transmit pulse patterns to opposite ends of the transmission delay line.
  • the patterns are designed to match in superposition over appropriate tap locations 1 through N. The match will only occur once as the pulse pattern Vp1-1 through N and Vp2-1 through N pass one another. In the configuration illustrated in Figure 16, the pulses will match at a predetermined time at tap locations 1, 3 and N only.
  • the delay line 153 is located between the drivers 151 and 152.
  • Figure 17 shows an alternative configuration of a delay line circuit with first and second signal generators 151 and 152. These signal generators transmit serially reversed selection patterns through isolation circuits 154 into a delay transmission line.
  • a third signal Vp3 is transmitted from signal generator 155 in order to provide a voltage boost at all tap locations along the transmission line.
  • the voltage boost Vp3, together with coincident signals and Vp2 exceed the selection or activation threshold, Va, in order to select the desired tap or taps 1 through N of the transmission line 156.
  • Utilization of a boosting delay line permits use of smaller voltage levels Vp1 and Vp2 in order to reach a threshold offset.
  • Boost circuits also help alleviate constraints due to pulse rise and fall times for the first and second activation signals.
  • Figure 18 shows a dual supply RMS driver arrangement.
  • the configuration essentially divides the source supply for the drivers 310 and 320 into two parts. This permits the application of RMS voltages across the display elements (1 through n).
  • the transmission structure 305 1 is placed orthogonal to transmission structure 305, forming an X-Y matrix.
  • 305 1 can be viewed as a back-plane structure.
  • the driver 320 would be required to drive the entire load of all the cells 1-n. IN a typical display, the load would be seen as considerable capacitance, since the capacitance of each cell is in parallel. Driving this capacitance in a short dV/dt time restricts the driving speed.
  • Some display types such as LCD's require RMS voltage.
  • the RMS voltage achieved by signals transmitted through the two transmission lines 305 and 305 1 .
  • the generator 310 drives a positive pulse Vp1 and generator 320 drives a negative pulse Vp2.
  • the RMS is achieved by generator 310 driving a negative pulse Vp1 and generator 320 driving a positive pulse Vp2' .
  • the advantage of this arrangement is that the drivers 310 and 320 only have to switch through (1/2) the voltage required on the pixel (1..n) elements.
  • Figure 18a shows a four supply RMS driver configuration.
  • Generators 310' and 320' have been added. With this arrangement, the voltage across pixel 1, for example, will be the SUM of the generator voltages. This permits the generator 310, 310 , 320 and 320 ' to be (1/4) the voltage required on pixel (1..n) elements.
  • Transmission line delay lines may be constructed of cable, wave guides, strip guides and micro strip methods. According to the invention, it is advantageous to provide a three-dimensional slab construction for a transmission line.
  • the slab construction allows establishing a transmission propagation delay over a selected highly variable range based on the material selection and geometry utilized.
  • Figure 19 shows an edge view of a multiple tap delay line slab configuration which can be used in the display circuitry according to the invention.
  • the slab includes a center material 160 composed of a magnetic permittive material such as ferrite.
  • the ferrite material surrounds a conductor 161, which may be in a serpentine configuration, in order to increase the linear propagation path of the slab and the inductance of the transmission line.
  • the conductor includes interconnects 162 configured to form a bottom plate of a distributed capacitor. The plates are separated by a dielectric material 163 and the top plate of the distributed capacitor is formed by a conductor 164.
  • Figure 20 illustrates an equivalent circuit using electrical symbology for the various components of the transmission line.
  • the ferrite 160 and the conductors 161 make up the inductance of the transmission line.
  • the conductors 161 are connected by serial interconnects 162, which also act as one plate of a distributed capacitor system.
  • the second plate is provided by conductor 164, and the plates are separated by dielectric 163.
  • the transmission line propagation velocity Vp and associated linear delay is calculated according to the formulas described above.
  • Figure 21 shows a perspective view of a configuration with electrical taps 165 connected to selective interconnects 162 through openings provided in the conductor 164. Note that, in this configuration, allowances must be made for the area of the capacitive plates lost due to openings in the conductor 164.
  • Figure 22 shows a further alternative configuration utilizing discrete plug-in interconnects 162.
  • the inductance can be increased by increasing the thickness of the ferrite layer 164 and the conductors 161 associated with the interconnects 162.
  • the ferrite material with a higher or lower permittivity may be selected.
  • the capacitance can be affected by adjusting the spacing between the conductor 164 and the interconnect 20 or using a dielectric 163 with different dielectric constants or thicknesses, or changing the dimension or configuration of interconnects 162. Also in this configuration, taps may be connected directly to the interconnects 162.
  • the present invention also includes a method for selectively activating any of a plurality of different display locations across a display area. Such method embodies the principles of the present invention.
  • the method includes the step of selectively transmitting first and second electrical signals 42, 48 along delay line structure 14.
  • Delay line structure 14 provides at least one continuous propagation path that extends through each of the display locations 32.
  • a second step of the method is directing the propagation of first and second electrical signals 42, 48 along transmission means 14 so that first and second electrical signals 42, 48 converge to produce an activating signal at a selected display location.
  • a third step is producing a visual signal at the selected display location upon receipt of an activating signal at that selected location.
  • the individual display element When using a delay transmission line for addressing display locations or pixels, the individual display element must respond within the width of the pulse or signal traveling along the delay transmission line. Utilization of nonlinear circuits connecting the transmission structure to the display location allows utilization of a narrow activation signal with respect to the display location response time.
  • the LCD cells require an activation voltage of typically two volts for several milliseconds.
  • Typical LCD displays require activation pulse widths of approximately 35 microseconds. The 35 microsecond pulse will create a sufficient RMS level if the pulse level is high enough, in the typical case 40 volts.
  • activation pulses narrower by orders of magnitude than 35 microseconds may be used. Zener diodes may be used as effective nonlinear devices to form a barrier between the transmission structure and one side of a pixel display element.
  • Figure 23 shows a diagram of an LCD 300 with a diode connected to the delay line 305 through a nonlinear circuit.
  • the nonlinear circuit includes two back-to-back Zener diodes which create an RMS voltage across the LCD.
  • Zeners 301, 302, 303, 304 can be standard one-quarter watt, 10 volt zeners with a forward voltage drop of 0.7 volts.
  • the internal resistance of the electrode connecting the LCD is represented by resistor 306, and parasitic resistance is represented by resistor 307.
  • resistor 306 parasitic resistance
  • resistor 307 parasitic resistance
  • a 2 nanosecond pulse may charge the LCD for 72 microseconds.
  • the row rate In order to sustain a continuous active display element state in this configuration, the row rate must be faster than 72 microseconds.
  • a typical VGA row rate is 34.7 microseconds, or twice as fast as required.
  • the premise of operation is to have a voltage on the column side of an LCD pixel element, the anode of Zener diode 301, and a corresponding complementary voltage on the row side, the anode of Zener diode 304, of the LCD display element. If the voltage is greater than the Zener voltage of diode 302, the display element is charged with a positive voltage on the anode of Zener 302 and a negative voltage on the anode of Zener 303. To place the opposite polarity voltage on the LCD display element and generate an RMS voltage across the display element, a negative voltage greater than the Zener voltage of diode 301 and a positive voltage greater than the voltage of Zener diode 303 are required. This charges the display element. In order to begin charging the LCD element with a positive voltage on the anode of Zener
  • the transmission delay line voltage on the anode of Zener 301 must be 10 volts plus .7 volts.
  • the complementary voltage of -12.7 volts is applied to the row side of the display element cell. The difference between the applied voltage minus the sum of the Zener voltage drops and the diode forward voltage drop is 2 volts on the anode of Zener 302 and -2 volts on the anode of Zener
  • the height and width of the pulse on the transmission line required to charge the LCD cell depends on the cell's capacitance and resistance.
  • the pulse height must be equal to or greater than the Zener diode drops plus the desired voltage on the cell.
  • the width of the pulse must be great enough to charge the LCD cell in the specified time. In the example illustrated in Figure 12, the cell is charged to 2 volts.
  • a conservative estimate for an LCD cell is a capacitance of 4 picofarads, and resistance in the range of approximately 100 ohms.
  • An elementary rule of thumb is that a capacitor may be fully charged in 5 time constants or 5(R*C).
  • the charging time for a cell would be no more than 2 nanoseconds.
  • a more concise computation can be had according to the following formula:
  • the display element cell can be charged with an activation signal in the 2 nanosecond range.
  • the charge time can be further reduced.
  • Increasing the pulse repetition rate allows narrower pulses to be used to create the RMS value.
  • the limit on pulse width will be affected by the response of the nonlinear device.
  • the repetition rate required to maintain specific voltage levels is determined by the discharge time of the cell.
  • the discharge time for the cell is the length of time that the cell will be illuminated. A rule of thumb is that the worst case discharge time is equal to a single time constant, RC.
  • the parasitic resistance of a typical LCD cell is at least
  • the discharge time will be 72 to 73 microseconds.
  • Utilization of nonlinear devices as pulse expanders allows an extremely short activation pulse of 2 nanoseconds to illuminate an LCD display element for a period of at least 72 microseconds.
  • Figure 24 shows the application of nonlinear circuits to a passive matrix design for a display.
  • Drivers 310 transmit activation signals to either end of a column delay transmission line 311 and a row delay transmission line 312.
  • Non-delay column taps 313, 314 and 315 are connected through back-to-back Zener diode sets 316 to the column delay transmission line 311.
  • Display timing that takes advantage of the voltage retention feature of the nonlinear devices may be employed to enhance performance of the passive matrix displays. For example, if the display locations along column 316 are active, any or all of the rows associated with the column may be activated simultaneously.
  • Figure 25 shows a simplified display with back-to-back Zener diodes connected to each display element. Like reference numerals are utilized for like elements. Connecting back-to-back Zener diodes to each side of display elements 1 through 9 and the respective column or row taps results in an active matrix design. The display locations will remain active as long as a refresh rate higher than the time for the parasitic cell discharge is maintained. The display element cells may be turned off after they are activated.
  • the circuit design according to Figure 14 provides significant advantages over traditional active matrix designs. The traditional design requires drivers for each row and column, while this design drastically reduces the number of drivers required. In addition, a traditional design would require a transistor at each display location. This design allows implementation of an active matrix without such transistors.
  • Figure 26 shows a cross section of a display illustrating a display element or pixel architecture where each pixel is made up of elements 320, 321 and 322.
  • a gas layer 323 is provided between the pixel elements and a transmission structure 324.
  • the gas layer will act as a nonlinear element in similar fashion to the Zener diodes described above.
  • Element 321 is a light emitting element sandwiched between a cell conductor 322 and a transparent row conductor 320.
  • the gas layer may be noble gas or ferrous oxide.
  • Cell conductor 322 may be a solid or non-transparent conductor to block radiation from the ionization of the gas 323 or may include an ultraviolet light- sensitive light-emissive coating to enhance the brightness of the illuminating material 321.
  • Material 325 may be a transparent glass housing containing the circuit components.
  • the idiom tin oxide (ITO) which may be used as a transparent conductor material 320 conducts and charges the cell conductor 322 to the voltage level of the column conductor 324, minus the gas ionization voltage. The charge remains on the conductors 320 and 322 until bled off by the display element parasitic resistance or discharged by reversing the voltage.
  • the structure allows for active matrix performance without individual semiconductor devices.
  • a UV barrier material 326 may be placed between display elements in order to enhance the contrast between display locations.
  • the delay transmission lines and driver systems are not illustrated in Figure 26.
  • Figure 27 shows a three dimensional perspective view of the embodiment illustrated in Figure 26.
  • FIG 28 shows a display configuration using thin film transistor (TFT) active matrix type display elements.
  • TFT thin film transistor
  • This configuration applies selective convergence technology to a more traditional thin film transistor active matrix display.
  • Thin film transistors 330 are provided at the display locations.
  • the non-delay tap lines 313, 314 and 315 are connected through back-to-back Zener pairs 316 to the column delay transmission line 311.
  • Non-delay tap lines 317, 318 and 319 are connected to the row delay transmission line 312 through back-to-back Zener diodes 316.
  • a signal input to the thin film transistors is connected to the column tap lines, and the gate input to each transistor is connected to a row tap line.
  • Thin film transistors may have an operating speed as slow as 16 microseconds.
  • Zener diodes can be utilized to overcome some of the pulse width response limitations for individual delay elements.
  • the limitations can be further reduced by utilizing additional diodes.
  • the response limitation is mainly due to the internal capacitance of Zener diodes.
  • Zener diodes can be constructed with very small capacitance levels which permit widths to be optimized in the nanosecond range.
  • the physical length of the delay transmission lines can be shortened. More taps per unit length and hence increased display resolution are possible. Shorter transmission lines allow a lower power loss due to resistance of a line.
  • cost of construction is reduced by the use of less exotic materials. For example, if a standard printed circuit board has a propagation time of 4 nanoseconds per foot and the pulse width is set to 1 nanosecond, then a typical 160 tap transmission slab would require 80 feet of trace or delay material.
  • Another function of pulse width expansion circuits may be to provide an offset or threshold voltage.
  • Diodes typically have forward voltages that are very low and which limit their use in providing a threshold to a display location.
  • the low forward voltage of diodes can be overcome by providing a reverse voltage DC bias on the diode.
  • DC bias on the diode is adjustable and is an advantage over other display methods which require fixed thresholds.
  • the threshold may be adjusted by simply changing the DC bias voltage.
  • An adjustable bias permits construction of a more universal display driver system that does not require changes in part specifications with each different application caused by different thresholds. The system would be suited to various threshold requirements simply through adjustment of the bias level.
  • Figure 29 illustrates a diode bias display element.
  • a delay transmission input 335 is advantageously biased to -5 volts.
  • a second transmission input 336 is biased to a positive +5 volt level.
  • Transmission input 337 is also biased to a +5 volt, and transmission element input 338 is biased to a -5 volts.
  • the transmission element inputs must generate a voltage greater than the bias levels in order to activate the display element 339.
  • a positive going pulse Vp1 across the transmission elements 335 and 336 activates those inputs.
  • the negative going pulse Vp2 activates inputs 337 and 338.
  • the bias voltage levels determine the magnitude of Vp1 and Vp2 required to activate the display input. In the example illustrated in Figure 29, the maximum pulse amplitude generated by Vp1 is 10 volts.
  • Figure 30 shows a diode configuration for a display device with nine display elements configured in a three by three matrix.
  • the small number of display elements is chosen for purposes of illustration only and is not intended to limit the possible display sizes.
  • the display configuration utilizes four delay lines.
  • Delay lines 360 and 363 are provided for charging display locations, thereby activating an illumination response.
  • Delay lines 361 and 362 are provided for triggering a discharge of the delay locations, thereby turning off the localized illumination.
  • Figure 31 shows an exploded view of the physical construction of the screen architecture for a dual serpentine trace screen geometry.
  • the figure is simplified for the sake of illustration.
  • the delay line trace structure includes a ground plane 401 and two parallel traces 402, 403.
  • the geometry and material selection for all components are made such that the elements exhibit desired levels of inductance and capacitance in order to provide an acceptable predictable signal propagation velocity to achieve a signal reinforcement condition at selected display locations.
  • the display locations may be individual pixels 404.
  • Each trace is advantageously made up of inductor sections 406 and capacitor sections 407.
  • the figure illustrates a single inductor and capacitor for each display location. However, there may be a plurality of each element or any other geometrical configuration which results in the desired component values.
  • a dielectric material 408 is located between the capacitor portion of the signal trace and the ground plane.
  • Each trace has a driver input end 409 and a termination 410.
  • the inductor portions of the trace are advantageously encased in a ferrite material 411 to increase the inductance.
  • the circuit described shows only a single inductor and capacitor element between pixels. This requires that the inductance and capacitance per element be larger than would be necessary if the number of elemental inductors and capacitors are increased.
  • a display may be constructed with a width of 40 inches and an 800 line horizontal resolution. This will result in a pixel pitch .05 inches.
  • the pixel pitch is the distance between pixels and may be the same in both the horizontal and vertical dimensions.
  • the system may be set up to display video information at various rates.
  • a typical selected data rate may be 53.3 nanoseconds per pixel.
  • a system configured according to the invention will have a propagation time equal to the data rate, resulting in a propagation delay of 53.3 nanoseconds per .05 inches.
  • the delay time of each trace is defined by the LC circuit parameters of the trace configuration. For the sake of this calculation, we assume that the capacitor portions of the trace do not have any inductive properties and the inductor portions do not have any capacitive properties.
  • the transmission delay time, td is defined:
  • L and C cannot be entirely arbitrary, because the relationship determines the impedance of the signal path and the output impedance of the driver must match the impedance of the signal path.
  • a 50 ohm impedance is selected. Fifty ohm drivers are commonly available.
  • the transmission line impedance, Z may be defined:
  • the capacitance C is defined by:
  • the inductance L is defined as follows:
  • the length of the capacitor, Cl is selected to be two thirds of the pixel pitch:
  • the capacitor width Cw is selected to be:
  • Er is the dielectric constant of the dielectric material 408
  • A is the area of the capacitor portion of the trace, which in this example is Cw*Cl;
  • d is the height of the dielectric which may be .00001 inches fabricated on conventional PCB technology; and .225 ⁇ 10 -12 is the dielectric constant of air.
  • the system can be constructed using the configuration illustrated in figure 23 by selection of a dielectric with a constant of 75.8, which is in the range of off the shelf non-ceramic dielectrics. If necessary for a particular application, other materials such as ceramics are available with dielectric constants of 12,000 to 400,000.
  • the inductance, L, of a stripline inductor is given by:
  • Ui is the permeability of the ferrite layer
  • Ll is the length of the trace
  • Tf is the thickness of the ferrite layer
  • Tt is the thickness of the trace.
  • the inductor illustrated has a length, Ll, of:
  • the thickness of the ferrite layer may be selected within the possible fabrication range to be .01 inches and the trace thickness may be .00001 inches.
  • the desired permeability for the ferrite material may be calculated and used to select a material.
  • the propagation path is designed in a configuration such that a portion of the trace forms an inductor and on each side of the inductor the trace forms a capacitor.
  • the dielectric material may be masked onto the ground plane layer low under the inductor section of the trace and high under the capacitor section of the trace. Note that the inductor pattern may be varied from what is shown to increase or decrease the inductance. Changing the geometry of the trace is especially important as the transmission structures reverse themselves at the edges of the display to maintain the characteristic impedance and avoid unwanted reflections of the signal.
  • Figure 32 shows an exploded view of a propagation structure for a four input dual perpendicular edge mounted transmission delay structure with non-delayed taps in a gas discharge type display. The figure is simplified for the sake of illustration.
  • the structure illustrated is advantageously contained in a gas tight housing with a transparent cover.
  • a column transmission structure 451 exhibits a predetermined signal propagation velocity determined by the geometry and materials selected.
  • the column delay structure has a driver input 452 at one end and a second input (not illustrated) at an opposite end of the structure.
  • a plurality of column conductors 453 are connected to the transmission structure.
  • a row transmission structure 454 may have a similar configuration but is oriented perpendicularly to the column transmission structure.
  • the a row transmission structure 454 has driver inputs at its ends 455.
  • the column transmission structure may be located on a ground plane 456 with dielectric material 457 located between the ground plane and the trace, at least in the capacitive area 458 of transmission structure.
  • the trace configuration defines the inductive characteristic of the inductor area 459 of the transmission structure.
  • the row transmission structure may be located on the ground plane 456 or on a separate ground plane 460.
  • a plurality of non-delay row conductors 461 are connected to the row transmission structure.
  • the row conductors are transparent conductors each connected to the transmission structure by a via 462. Other configurations can be utilized without departing from the scope of the disclosure.
  • a cell conductor 463 and gas layer 464 are located between the column and row conductors.
  • a display location or pixel 465 is at each intersection of row and column conductors.

Abstract

L'invention concerne un appareil et un procédé de création d'images visuelles sur une surface d'affichage (18). Cet appareil fait appel à la convergence sélective du déplacement de signaux électriques circulant pour éclairer ou modifier les aspects visuels de zones d'affichage sélectionnées dans une surface d'affichage (18). L'appareil de cette invention peut comporter un mécanisme d'affichage (120) qui, lorqu'il est activé, soit s'éclaire soit modifie son aspect visuel, au moins un trajet (20, 22) de propagation de signaux qui oriente la propagation des signaux sur la surface d'affichage (18), ainsi qu'une unité (40) de commande de signaux destinée à transmettre les signaux de manière sélective. Le premier et le second trajet (20, 22) de propagation de signaux peuvent assurer des trajets de propagation uniques passant par chacune des zones de l'écran (18). L'unité (40) de commande de signaux diffère de manière sélective la transmission du second signal par rapport au premier signal, faisant de ce fait converger les signaux vers une zone choisie dans le but de modifier l'aspect visuel de l'écran (18) au niveau de la zone choisie. En modifiant de façon répétée l'aspect des zones d'affichage sur la surface d'affichage (18), il est possible de créer des images visuelles. L'invention ne réclamant qu'un circuit d'attaque, les exigences en matériel sont minimes.
PCT/US1995/014417 1994-11-09 1995-11-09 Ecran video et appareil et procede de commande WO1996015519A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU41476/96A AU4147696A (en) 1994-11-09 1995-11-09 Video display and driver apparatus and method

Applications Claiming Priority (6)

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US33873994A 1994-11-09 1994-11-09
US33878694A 1994-11-09 1994-11-09
US33874694A 1994-11-09 1994-11-09
US08/338,746 1994-11-09
US08/338,786 1994-11-09
US08/338,739 1994-11-09

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EP0969445A1 (fr) * 1998-06-30 2000-01-05 Sun Microsystems, Inc. Dispositif et procédé pour l'activation sélective d'éléments adressable d'affichage
WO2000060567A1 (fr) * 1999-04-02 2000-10-12 Sun Microsystems, Inc. Procede et appareil permettant la complicite selective d'elements d'affichage adressables, plus particulierement destines a des agencements avec propagation de signaux d'image le long d'un conducteur d'affichage pourvu de points de connexion
EP1139321A1 (fr) * 1998-10-06 2001-10-04 Canon Kabushiki Kaisha Procede de commande d'affichage d'image
EP1422684A1 (fr) * 2001-06-29 2004-05-26 Alexander Mikhailovich Ilyanok Ecran plat a balayage automatique
WO2009024523A1 (fr) * 2007-08-23 2009-02-26 Seereal Technologies S.A. Appareil d'affichage électronique, et dispositif de commande des pixels d'un écran
WO2010064184A1 (fr) 2008-12-05 2010-06-10 Philips Intellectual Property & Standards Gmbh Delo avec structure de retard intégrée
WO2010064183A1 (fr) * 2008-12-05 2010-06-10 Philips Intellectual Property & Standards Gmbh Circuit et procédé d’alimentation sélective d’une pluralité d’éléments de charge

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GB2149182A (en) * 1983-10-31 1985-06-05 Sharp Kk Electroluminescent panels
EP0154662A1 (fr) * 1984-03-15 1985-09-18 Hans Werba Dispositif d'affichage optique par ligne
US4958152A (en) * 1987-06-18 1990-09-18 U.S. Philips Corporation Display device and method of driving such a device

Cited By (20)

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US6157375A (en) * 1998-06-30 2000-12-05 Sun Microsystems, Inc. Method and apparatus for selective enabling of addressable display elements
EP0969445A1 (fr) * 1998-06-30 2000-01-05 Sun Microsystems, Inc. Dispositif et procédé pour l'activation sélective d'éléments adressable d'affichage
US6628273B1 (en) 1998-06-30 2003-09-30 Sun Microsystems, Inc. Method and apparatus for selective enabling of addressable display elements
US6972741B1 (en) 1998-10-06 2005-12-06 Canon Kabushiki Kaisha Method of controlling image display
US7268750B2 (en) 1998-10-06 2007-09-11 Canon Kabushiki Kaisha Method of controlling image display
EP1139321A1 (fr) * 1998-10-06 2001-10-04 Canon Kabushiki Kaisha Procede de commande d'affichage d'image
EP1139321A4 (fr) * 1998-10-06 2002-06-19 Canon Kk Procede de commande d'affichage d'image
US6456281B1 (en) 1999-04-02 2002-09-24 Sun Microsystems, Inc. Method and apparatus for selective enabling of Addressable display elements
WO2000060567A1 (fr) * 1999-04-02 2000-10-12 Sun Microsystems, Inc. Procede et appareil permettant la complicite selective d'elements d'affichage adressables, plus particulierement destines a des agencements avec propagation de signaux d'image le long d'un conducteur d'affichage pourvu de points de connexion
EP1422684A4 (fr) * 2001-06-29 2005-10-05 Alexander Mikhailovich Ilyanok Ecran plat a balayage automatique
EP1422684A1 (fr) * 2001-06-29 2004-05-26 Alexander Mikhailovich Ilyanok Ecran plat a balayage automatique
WO2009024523A1 (fr) * 2007-08-23 2009-02-26 Seereal Technologies S.A. Appareil d'affichage électronique, et dispositif de commande des pixels d'un écran
DE102007040712B4 (de) * 2007-08-23 2014-09-04 Seereal Technologies S.A. Elektronisches Anzeigegerät und Vorrichtung zur Ansteuerung von Pixeln eines Displays
WO2010064184A1 (fr) 2008-12-05 2010-06-10 Philips Intellectual Property & Standards Gmbh Delo avec structure de retard intégrée
WO2010064183A1 (fr) * 2008-12-05 2010-06-10 Philips Intellectual Property & Standards Gmbh Circuit et procédé d’alimentation sélective d’une pluralité d’éléments de charge
CN102239512A (zh) * 2008-12-05 2011-11-09 皇家飞利浦电子股份有限公司 具有集成的延迟结构的oled
JP2012511172A (ja) * 2008-12-05 2012-05-17 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 遅延構造体を組み込まれた有機発光ダイオード
US8686660B2 (en) 2008-12-05 2014-04-01 Koninklijke Philips N.V. OLED with integrated delay structure
RU2514205C2 (ru) * 2008-12-05 2014-04-27 Конинклейке Филипс Электроникс Н.В. Осид со встроенной структурой задержки
KR101944382B1 (ko) * 2008-12-05 2019-02-07 베이징 시아오미 모바일 소프트웨어 컴퍼니 리미티드 집적 지연 구조를 갖는 ｏｌｅｄ

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