WO1996004714A1

WO1996004714A1 - Level converting circuit

Info

Publication number: WO1996004714A1
Application number: PCT/JP1995/001296
Authority: WO
Inventors: Kazumasa Takashima; Yuji Yokoyama
Original assignee: Hitachi, Ltd.
Priority date: 1994-08-02
Filing date: 1995-06-29
Publication date: 1996-02-15

Abstract

A level converting circuit comprising a p-channel field effect transistor (11) for receiving signals at a GTL interface level and an npn bipolar transistor (14), wherein the field-effect transistor (11) and the bipolar transistor (14) are connected between their source and drain to form a level conversion output node and the two transistors are also connected between their drain and base. The field-effect transistor (11) converts the level of the input signals, i.e., the GTL interface level, into a level at which the transistor (14) operates and further raises the converted level. Therefore, the GTL interface level can be converted into a higher level at a high speed.

Description

Description Level conversion circuit Technical field

The present invention relates to a technique for converting a level of a small amplitude signal, and more particularly to a technique effective when applied to an SRAM (static random access memory). Background art

A SRAM as an example of a semiconductor memory device includes a memory cell array in which a plurality of static memory cells are arranged in a matrix. The selection terminal of a static memory cell is coupled to a lead line for each row direction, and the data input / output terminal of the memory cell is coupled to a complementary data line for each column direction. Each complementary data line is commonly connected to a complementary common data line via a column switch circuit including a plurality of switches coupled one-to-one to the complementary-data lines. An externally input address signal is transmitted to a row decoder and a column decoder. The code line is coarsely moved to the selection level based on the decode output of the row decoder, and the column selection switch is turned on based on the decode output of the column decoder, whereby data is written to a specific memory cell or the memory cell is written. Data can be read. As a control signal supplied from outside, the chip select signal CS * (The symbol * indicates that the signal to which it is attached is a reactive signal or the signal that is inverted with respect to the signal without the symbol *. And the write enable signal WE *. Chip selection is performed by asserting the chip select signal CS * to low level. When the write enable signal WE * is asserted to the oral level in such a selected state, data can be written to the memory cell.

As an example of a document describing SRAM, there is Japanese Patent Publication No. 57-21795.

In the case of the SRAM, particularly in the sink-port eggplant SRAM which takes in an address signal, write data to a memory cell, and various control signals in synchronization with a clock signal supplied from the outside, There is a timing regulation from the waveform edge of the clock signal to the data output timing, and therefore, it is extremely important to speed up the operation of the buffer for receiving the clock signal, address signal, and the like. To increase the speed of the buffer, it is desirable to handle low-amplitude signals by applying bipolar transistors and reducing the power supply voltage to 3.3 V or the like.

Conventionally, as a low-amplitude interface circuit, an ECL (EmiterCoupledLogic) interface method or a GTL (GunninngTranascseiverlogi) method has been used.髙 When the potential side power supply V cc = 3.3 V, the ECL interface level is set to the high level with the reference potential V ref = (V cc-0.9 V) as the logical threshold, as shown in Fig. 9. The level is V ref + 0.4 V, and the low level is V ref — 0.4 V. For this reason, the ECL interface level signal can be directly handled by the bipolar transistor.

However, as shown in FIG. 9, the GTL interface level has a high level of V ref +0.2 V and a low level of V ref = V ss +0.8 V as a logical threshold value. V ref — set to 0.2 V. In other words, the logic threshold of the ECL interface level is While the power supply voltage is close to Vcc and its amplitude is 0.8 V, the logic threshold value of the GTL interface level is close to the low-potential power supply Vss and its amplitude is 0.4 V . The minimum potential between the base and the emitter of the bipolar transistor is 0.7 to 0.8 V. Considering the operation margin, at least the input signal potential is required to be 1.2 V or more. Signals cannot directly drive bipolar transistors.

An object of the present invention is to provide a level conversion circuit for converting a signal of a GTL interface level at a high speed.

It is another object of the present invention to provide an input buffer including such a level conversion circuit.

Still another object of the present invention is to provide a semiconductor integrated circuit having the input buffer. Disclosure of the invention

According to the present invention, a level conversion output node is formed by coupling the source electrode of a p-channel field effect transistor (11) for capturing a signal at the GTL interface level and the collector electrode of a bipolar transistor (14). A level conversion circuit is formed by coupling the drain electrode of the p-channel field effect transistor (11) and the base electrode of the bipolar transistor (14). In this level conversion circuit, the input signal of the GTL interface level is converted by the p-channel field-effect transistor (11) to a level that can be captured by the npn-type bipolar transistor (14), and is converted as such. The converted signal is further converted to 髙ぃ level by the bipolar transistor (14). Therefore, the p-channel field effect transistor (11) When combined with the npn-type bipolar transistor (14), it is possible to provide a level conversion circuit capable of performing high-speed level conversion of a GTL interface level signal.

At this time, in order to further speed up the operation of the level conversion circuit, an n-channel type in which a signal at the GTL interface level is received at the gate and a drain electrode is coupled to the base electrode of the bipolar transistor (14) A field effect transistor (16) is provided to speed up the charge extraction of the base electrode.

An n-channel field effect transistor (17) is connected in parallel to the p-channel field effect transistor (11), and the P-channel field effect transistor (11) and the n-channel field effect transistor are connected in parallel. By connecting the gate electrodes of the effect transistors (17) to each other, the output amplitude can be limited to a predetermined level even when the input level undesirably becomes 髙ぃ potential.

A constant current source (1) is connected between a junction between the collector electrode of the bipolar transistor (14) and the source electrode of the P-channel field effect transistor (11) and a high potential side power supply (Vcc). By providing 3), the current flowing therethrough can be limited, and the quiescent current in the level conversion circuit can be reduced.

Further, by providing a constant current source (15) between the emitter electrode of the bipolar transistor (14) and the low potential side power supply (Vss), the influence of ground noise can be reduced.

An input buffer to which the level conversion circuit is applied includes a first conversion circuit (10) for taking in a GTL interface level signal, and a reference voltage (V) for determining a logic value of the GTL interface level signal. ref) and a second conversion circuit (20) for taking in the first conversion circuit (10). The level conversion circuit is applied to the second conversion circuit (20). The reference voltage (V ref) is supplied to a p-channel type field effect transistor (2 1) in the level conversion circuit applied to the second conversion circuit (20). This makes it possible to quickly determine the logic value of the GTL interface level signal and take it into the inside. As a circuit for determining a logical value, a differential amplifier circuit (52) for amplifying a level difference between an output signal of the first conversion circuit and an output signal of the second conversion circuit is employed. Can be done.

A semiconductor integrated circuit to which the input buffer is applied is provided with an input buffer (501-1-0 to 501-n, 502,503,511) for taking in a GTL interface level signal from outside. And a logic circuit for processing a signal captured by the input buffer. As a result, it is possible to shorten the time from when the GTL interface level signal is received from the outside to when the processing in the logic circuit based on the signal is determined. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is an example circuit diagram of a level converter provided with a level conversion circuit according to one embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining an operation of a main part in the level conversion circuit. ―

FIG. 3 is a circuit diagram showing an example of a differential amplifier circuit and an emitter follower circuit in an address receiver provided in an SRAM according to an embodiment of the present invention. FIG. 4 is a block diagram showing an example of a computer system including the SRAM.

FIG. 5 is an overall block diagram of the SRAM.

Fig. 6 is a block diagram of an example of an address receiver installed in the SRAM. It is.

FIG. 7 is an example circuit diagram of a current mirror circuit in the address receiver.

FIG. 8 is an example circuit diagram of a circuit for generating a reference voltage supplied to the address receiver.

FIG. 9 is an explanatory diagram for comparing the ECL interface level and the GTL interface level.

FIG. 10 is a simulation characteristic diagram of the circuit shown in FIG. FIG. 11 is a circuit diagram of another embodiment of the level conversion circuit.

FIG. 12 is a circuit diagram of still another embodiment of the level conversion circuit. BEST MODE FOR CARRYING OUT THE INVENTION

In order to explain the present invention in more detail, this will be described with reference to the accompanying drawings.

FIG. 4 shows a computer system including a synchronous SRAM according to an embodiment of the present invention.

The computer system shown in FIG. 4 accesses a SRAM array (semiconductor array unit) 401 composed of a plurality of synchronous SRAMs 400 arranged in an array and the SRAM array 410. By doing so, a CPU (central processing unit) 403 for performing predetermined data processing, an interface circuit 404 for interfacing the CPU 403 with the SRAM array 401, and the like. Esteem. The synchronous SRAM array 401 is capable of high-speed read / write, and is used as a main memory or a cache memory of the computer system.

The interface circuit 404 decodes the address buffer 405 for taking in the address signals A 0 to AK from the CPU 403 and the input address. A decoder (DCR) 406 for generating chip select signals CS1 * to CSm * by a command and a controller (CONT) 407 for generating control signals for the SRAM array 401 Esteem. Of the address signals A 0 to AK output from the CPU 403, AO to An are supplied to the SRAM array 401 as address signals of the individual SRAMs 400 of the SRAM array 401. The address signals Aπ + 1 to AK are input to the decoder 406. By decoding the address signals An + 1 to AK, a desired SRAM 4 Chip select signals CS 1 * to CS m * for selecting 00 are generated. The controller 407 receives a write enable signal WE * from the CPU 403 and a memory select signal MS, and the controller 407 sends a write enable signal to the 51-81 array 401. WE * is supplied. This write enable signal WE * is commonly input to all SRAMs 400 in the SRAM array 401. Also, the data input terminals and data output terminals of all the SRAMs 400 included in the SRAM array 401 are coupled to a data input / output buffer (DBD) 410, respectively. The data input / output buffer 410 is coupled to the CPU 403 via the data bus 411.

When a write instruction is given to the SRAM array 401 by asserting the write enable signal WE * to a low level by the CPU 403, the chip select signal CS 1 * from the decoder 406 is output. The SRAM 400 selected according to CSm * is set to the data write state. At this time, the data D1 to DB transmitted from the CPU 403 via the data bus 411 are taken in by the data input / output buffer 410, and are written as the write data Di1 to DiB in the SRAM4. Supplied to the 0 data input terminal. The CPU 403 sets the write enable signal WE * Is negated to a high level, the data is read from the SRAM 401, and the SRAM 4 selected according to the chip select signals CS1 * to CSm *, as described above. The data Do 1 to D 0 B read from 00 are output to the data bus 4 1 1 via the data input / output buffer 4 10.

The working power of the SRAM 400 is not particularly limited, but is supplied from the interface circuit 404. When the low-potential power supply Vss is set to 0 V (zero volt), the high-potential power supply Vcc is set to 3.3 V. At this time, various signals such as control signals and data exchanged between the SRAM 400 and the CPU 403 or the interface circuit 404 are at the GTL interface level. The supply path of the operation power supply to the SRAM is typically shown in FIG. 4 also for one SRAM.

FIG. 5 representatively shows an overall configuration example of one SRAM 400.

Although not particularly limited, the SRAM shown in FIG. 5 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In FIG. 5, reference numeral 506 denotes a memory cell array in which a plurality of static memory cells are arranged in a matrix. The selection terminals of the memory cells are connected to word lines in each row direction, and data input / output of the memory cells is performed. The terminals are coupled to complementary data lines (also referred to as complementary bit lines) for each power ram direction. Each of the complementary data lines is commonly connected to a complementary common data line via a column switch circuit 509 that includes a plurality of switches coupled one-to-one with the complementary data line.

Of the address signals A0 to An input from the outside, A0 to Am are transmitted via address receivers 501 to 0 to 501 to m arranged correspondingly. The address signals Am + 1 to An are transmitted to the row decoder 504, and the column decoder 5 via the address receivers 501 to m + 1 to 501-n arranged corresponding thereto. It is transmitted to 08. The word driver 505 drives the word line corresponding to the input address signal to a selected level based on the decoded output of the row decoder 504. Although not particularly limited, the word driver 505 includes a plurality of drive circuits corresponding to the number of word lines. When a predetermined word line is driven, a memory cell connected to this word line is selected. Further, the column decoder 508 turns on the column selection switch corresponding to the address signal supplied thereto, and makes the complementary data line connected to the ON-state column switch conductive to the complementary common data line. At this time, the potential of the complementary common data line is amplified by a sense amplifier included in the data input / output circuit 5 10 and can be output to the outside via an output buffer. When write data is externally supplied to an input buffer provided in the data input / output circuit 5100, the complementary common data line is driven in accordance with the write data, and thereby, the complementary data line selected by the address signal is driven. Information corresponding to the data is stored in a predetermined memory cell via the line.

In addition, a chip select signal CS *, a write enable signal WE *, and a clock signal CLK as externally applied control signals are transmitted via the CS receiver 502, the WE receiver 503, and the clock receiver 5111, respectively. The control unit 507 receives the operation control signal, and the control unit 507 generates an operation control signal for each unit of the present embodiment. When the chip select signal CS * is asserted low, the SRAM is enabled, and in such a state, the write enable signal WE * is driven high. In this case, data is written to the memory cell, and when the write enable signal WE * is set to low level, Is in a state of reading memory cell data. Although not particularly limited, the SRAM of this embodiment is of a clock synchronous type, and is written to address signals A0 to An, a chip select signal CS *, a write enable signal WE *, and further to a memory cell. Write data to be read, read data from a memory cell, etc. are taken in or output in synchronization with the clock.

The address signals Am + 1 to An, the chip select signal CS *, the write enable signal WE *, the clock signal CLK, and the write data are all at the GTL interface level outside the SRAM. Signaled. Therefore, address receivers 501--0 to 501-n, clock receivers 502, 503, and 51, and the data in the data input / output circuit 510 The data receivers and the like are GTL interface-level inputs. It has a signal level conversion function.

Next, the detailed description of the write data receiver in the address receivers 501-0 to 501-n, the clock receivers 502, 503, 511, and the data input / output circuit 5 10 The configuration will be described. These various receivers are input buffer circuits for taking in external signals at the GTL interface level into the SRAM, and are not particularly limited, but all have the same configuration in the present embodiment. Therefore, in the following description, an address receiver corresponding to the input address signal AO will be described in detail.

FIG. 6 exemplarily shows a configuration example of an address receiver 510-11 for taking in an address signal A0.

A level converter 51 is provided as an input first stage for receiving a clock signal or the like from outside the SRAM according to the present embodiment. The level converter 51 includes, but is not limited to, an input address signal AO, a reference voltage Vref which is a reference level of the input address signal AO, and a constant current source. The reference voltages VIEP and VIEN for driving the IC are taken in. The input address signal A0 is set to a GTL interface level, and has a function of converting such a signal having a very small amplitude level to a CMOS level at high speed. A differential amplifier circuit 52 for amplifying a small amplitude signal is arranged at the subsequent stage of such a level converter 51, and after being amplified and amplified there, an emitter emitter follower circuit 53 at the subsequent stage and a current mirror circuit 54 are provided. , 55, and output driver circuits 56, 57 to output complementary level address signals a0, a0 *.

FIG. 1 shows a configuration example of the level converter 51.

Although not particularly limited, the level converter 51 includes a first conversion circuit 10 for taking in the input address signal A0 at the GTL interface level, and a reference voltage V for logic determination of the input address signal A0. A second conversion circuit 20 for taking in ref and an output unit 30 are provided. The first conversion circuit 10 and the second conversion circuit 20 each constitute a level conversion circuit.

The first conversion circuit 10 is used to form a p-channel type MOS transistor 11 for receiving the input address signal AO, an npn type bipolar transistor 14 coupled thereto, and a constant current source. The p-channel MOS transistor 13 and the n-channel MOS transistors 12 and 15 of FIG. The source electrode of the p-channel type MOS transistor 11 and the collector electrode of the npn type bipolar transistor 14 are commonly connected to the drain electrode of the p-channel type MOS transistor 13. The source electrode of this p-channel type MOS transistor 13 is coupled to the 髙 potential side power supply Vcc, and its gate electrode is supplied with a reference voltage VIEP. Function as In addition, the drain electrode of the P-channel type MOS transistor 11 is coupled to the low potential side power supply V ss via the n-channel type MOS transistor 12. The emitter electrode of npn-type bipolar transistor 14 is coupled to low-potential-side power supply V ss via n-channel MOS transistor 15. The reference voltage VIEN is input to the gate electrodes of the n-channel MOS transistors 12 and 15, and each functions as a constant current source. The connection point between the p-channel type MOS transistor 13 and the npn type bipolar transistor 14 in the first conversion circuit 10 is used as a level conversion output node of the first conversion circuit 10. This output node is coupled to the output section 30 at the subsequent stage. As described above, the source electrode of the p-channel MOS transistor 11 and the collector power of the npn-type bipolar transistor 14 are combined to form a level conversion output node. Since the drain electrode and the base electrode of the npn-type bipolar transistor 14 are coupled, the bipolar transistor 14 can be driven according to the input of the input address A0 of the GTL interface level. The input address signal A0 at the interface level can be accurately captured.

FIG. 2 shows an equivalent circuit for explaining the basic operation of the first conversion circuit 10. In the figure, for convenience of explanation, the n-channel MOS transistor 15 is omitted, and the n-channel MOS transistor 12 and the p-channel MOS transistor 13 are equivalently represented as resistors R 1 and R 2, respectively. It is shown.

Assuming that the gate-source voltage of the P-channel type MOS transistor 11 is V gs and the source current is i 1, the source current i 1 is

i 1 = A (V gs) ²

It is said. Where A is a constant. Also, assuming that the collector current of the npn type bipolar transistor 14 is i 2, the collector current i 2 is i 2 = β i 2

It is said. Here, is the current amplification factor of the bipolar transistor 14. Assuming that the current flowing through the resistor R 2 is i, this current i is

i = i 1 + i 2 = (1 + β) i 1 = A (I + β) (V gs) ² . therefore,

d i / d V g s = 2 A (1 + β) (V g s)

Becomes Since the value of 3 is large, the current i greatly changes with the change of V gs. In other words, when the potential of the drain electrode of the p-channel MOS transistor 11 (potential of the node N) changes due to a change in the input address signal A0 at the GTL interface level, this potential change is caused by the subsequent npn By accurately detecting the voltage between the base and emitter of the bipolar transistor 14, the input address signal A 0 at the GTL interface level is level-converted to high speed.

FIG. 10 shows a simulation result of the circuit shown in FIG.

(4) The potential-side power supply Vcc is 3.3 V, and the low-potential-side power supply Vss is 0 V.

In response to a change in the input voltage Vin due to the input address signal AO at the GTL interface level, the node N level is about 0.9 V at the center of amplitude, about 1.2 V at the high level, and about 1.2 V at the low level. It is raised to about 0.7 V. Although the bipolar transistor cannot be driven at the GTL interface level, as described above, the high level of the node N is raised to about 1.2 V by the p-channel type MOS transistor 11. The npn-type bipolar transistor 14 can be driven. Then, the potential of the node N is converted by a bipolar transistor into a potential change with a logic threshold of 2 V.

The second conversion circuit 20 has basically the same structure as the first conversion circuit 10. It is said to be done. That is, to form a p-channel type MOS transistor 21 for taking in a reference voltage V ref for logic determination of the input address signal A 0, an npn-type bipolar transistor 24 coupled thereto, and a constant current source. The p-channel MOS transistor 23 and the n-channel MOS transistors 22 and 25 are connected to each other, and the source electrode of the p-channel MOS transistor 21 and the collector electrode of the bipolar transistor 24 are connected to the p-channel MOS transistor. Commonly connected to the drain electrodes of the MOS transistors 23. The source electrode of the p-channel type MOS transistor 23 is coupled to the 髙 potential side power supply Vcc, and the gate electrode thereof is supplied with the reference voltage VIEP, and functions as a constant current source. The drain electrode of the p-channel MOS transistor 21 is coupled to the lower potential power supply V ss via the n-channel MOS transistor 22. Further, the emitter electrode of the bipolar transistor 24 is connected to the n-channel MOS transistor 21. It is coupled to the low-potential-side power supply V ss via the transistor 25. The reference voltage VIEN is input to the gate electrodes of the n-channel MOS transistors 22 and 25, and each functions as a constant current source. The connection point between the p-channel MOS transistor 23 and the bipolar transistor 24 in the second conversion circuit 20 is an output node, and this output node is connected to the output section 30 in the subsequent stage.

The output unit 30 is configured as follows. The output section 30 is formed by combining npn-type bipolar transistors 31 and 33 and n-channel MOS transistors 32 and 34 for forming a constant current source. The output signal from the first conversion circuit 10 is input to the base electrode of the bipolar transistor 31, and the output signal from the second conversion circuit 20 is input to the base electrode of the bipolar transistor 33 . Bipolar Tranges An output signal can be obtained from the emitter electrodes of the transistors 31 and 33. This output signal is transmitted to the differential amplifier circuit 52 shown in FIG. FIG. 3 shows a configuration example of the differential amplifier circuit 52 and the emitter follower circuit 53.

The differential amplifier circuit 52 is not particularly limited, but has η ρ π-type bipolar transistors 303 and 304 coupled differentially, and is connected to the base electrodes of the bipolar transistors 303 and 304. The output signal from the output section 30 in FIG. 1 is transmitted. The collector electrodes of the bipolar transistors 303 and 304 are coupled to the negative potential power supply Vcc via load resistors 301 and 302, respectively. Further, the emitter electrodes of the bipolar transistors 303 and 304 are coupled to the low-potential-side power supply V ss via the constant current source 305. The constant current source 305 is formed by an η-channel type MOS transistor, and a reference voltage V Ε 入力 is input to its gate electrode. The collector electrodes of the bipolar transistors 303 and 304 are used as the output nodes of the differential amplifier 52 and are coupled to the emitter emitter follower 53 at the subsequent stage.

The emitter follower circuit 53 includes two η ρ η-type bipolar transistors 308 and 309 and constant current sources 306 and 307 provided corresponding thereto. The collector electrodes of the bipolar transistors 308 and 309 are coupled to the high potential side power supply Vcc. The emitter electrodes of the bipolar transistors 308 and 309 are coupled to the low-potential-side power supply V ss via the constant current sources 306 and 307, respectively. The constant current sources 306 and 307 are each formed by an η-channel MOS transistor, and a reference voltage VI Ε is input to the gate power supply. The emitter electrodes of the bipolar transistors 308 and 309 are used as output nodes, which are coupled to the current mirror circuits 54 and 55 shown in FIG. Is done.

Next, the current mirror circuits 54 and 55 will be described. Since the current mirror circuits 54 and 55 have the same configuration as each other, only one of them will be described.

FIG. 7 representatively shows a configuration example of the current mirror circuit 54.

The p-channel MOS transistors 71 and 72 are differentially coupled, and a current mirror circuit is applied as the drain-side constant current source. This current mirror circuit is formed by an n-channel MOS transistor 74 and an n-channel MOS transistor 73 mirror-coupled thereto. The MOS transistors 73 and 74 have the same dimensions, and function as a constant current source when the gate-drain voltages are equalized. The source electrodes of the p-channel type MOS transistors 71 and 72 are coupled to a 髙 potential side power supply V cc via a p-channel type MOS transistor 75. The p-channel MOS transistor 75 functions as a constant current source by supplying the reference voltage VIEP to the gate electrode. The junction between the p-channel MOS transistor 72 and the n-channel MOS transistor 73 is the output node of the current mirror circuit 54.

FIG. 8 shows an example of a configuration of a circuit for generating the reference voltages VIEP and VIEN.

In FIG. 8, reference numeral 8001 denotes an n-channel MOS transistor for determining a current, a depletion type is applied to the MOS transistor 8001, and the gate electrode and the source electrode are connected to the low potential side power supply V ss. When connected to a line, it functions as a constant current source. The constant current path of this MOS transistor 801 includes a π-channel type MOS transistor. A star 805 and a p-channel type MOS transistor 802 are arranged, and a constant current flows through them.

In the MOS transistor 802, the source electrode is coupled to the 髙 potential side power supply Vcc line, the drain electrode and the gate electrode are coupled, and a constant drain current flows to reduce the source-drain voltage. It is kept constant.

Reference numeral 803 denotes a p-channel type MOS transistor. The MOS transistor 803 has a source electrode coupled to the high potential side power supply Vcc line, and a gate electrode connected to the gate electrode of the MOS transistor 802. , A drain current equal to that of the MOS transistor 802 flows. That is, a current mirror is formed by the MOS transistor 802 and the MOS transistor 803. To the MOS transistor 803, a p-channel type MOS transistor 804 and an n-channel type MOS transistor 807 are connected in series.

The MOS transistor 804 is a MOS transistor for voltage adjustment. The output of the operational amplifier 806 as a detection circuit for detecting the difference between the source and drain voltages of the MOS transistors 802 and 803 is used. Controlled. The non-reactive input terminal (+) of the operational amplifier 806 is coupled to the drain electrode of the MOS transistor 802, and the non-reactive input terminal (one) is coupled to the drain of the MOS transistor 803. With such a connection, the MOS transistor 804 is connected to the MOS transistor when the voltage between the source and the K-line of the MOS transistor 803 is lower than that of the MOS transistor 802. If the voltage between the source and the drain of 803 is lowered, and conversely, if the voltage between the source and drain of the MOS transistor 803 is lower than that of the MOS transistor 802, the MOS transistor To increase the source-drain voltage of 803, the operational amplifier 806 Controlled.

The gate electrode and the drain electrode of the MOS transistor 807 are connected, and the source electrode is connected to the low potential side power supply VSS line. The gate (drain) electrode of the MOS transistor 807 is a node 814, which is coupled to the output terminal of the reference voltage Vref. A drain current equal to that of the MOS transistor 801 flows through the MOS transistor 807 by the current mirror, so that the threshold voltage of the MOS transistors 801 and 807 is A potential equal to the difference appears, which is the reference voltage VIEN generated by the circuit of this embodiment (see equation below). Further, a π-channel type MOS transistor 815 is provided at a stage subsequent to the n-channel type MOS transistor 807. The drain electrode of the n-channel MOS transistor 815 is coupled to the high-potential-side power supply Vcc via a p-channel MOS transistor 816 as a load of the MOS transistor 815. In addition, the source electrode of the n-channel type MOS transistor 815 is connected to the lower potential side power supply Vss. With such a configuration, the drain electrode of the n-channel type MOS transistor 815 serves as the output node of the reference voltage VIEP.

Here, the drain current of the MOS transistor 801 is I ml, the gate length is Lml, the gate width is Wml, the threshold is V th ml, the mobility is, and the gate capacitance per unit area is Co x. If the drain current of the MOS transistor 807 is Im7, the gate length is Lm7, the gate width is Wm7, and the threshold value is Vthm7, the reference voltage VIEN is expressed as follows.

I ml = ^ Co x (Wml / 2 Lml) (0-V th ml)

= Cox (Wml / 2 Lml) (V th ml) ²

I πιΊ = μ C ox (Wm7 / 2 Lm7) (VI EN- V th m7) ² Here, if I ml = I m7, Wml = Wm7, Lml = Lm7,

^ Cox (Wml / 2 L ml) (V th ml) ²

= μ C ox (Wm7 / 2 Lm7) (VI EN- V th m7) ²

I V t h ml I = V I EN- V t h m7

Becomes Therefore, the reference voltage V I EN is

V I EN = V t h m7— V t h ml

This is equal to the difference between the threshold values of the MOS transistors 801 and 807.

Furthermore, in order to stabilize the reference voltage VIEN and the reference voltage VIEP generated based on the reference voltage, a current mirror composed of p-channel type MOS transistors 809 and 810 and a MOS transistor 809 N-channel MOS transistors 811 and 808 connected in series to the p-channel MOS transistor 812 and n-channel MOS transistor connected in series to the MOS transistor 810 813 transistors are provided, and the gate potential of the MOS transistor 811 is applied to the gate electrode of the MOS transistor 805. The MOS transistors 808, 811 and 812 have their gate electrodes and drain electrodes coupled to each other, and the MOS transistor 813 is of a depletion type as in the case of the MOS transistor 1. In addition, the source electrode and the gate electrode are coupled to the low potential side power supply Vss line.

In the above-described configuration, the source / drain voltages of the MOS transistor 802 and the MOS transistor 803 forming the current mirror may vary due to process variations of elements, fluctuations in the operating environment (eg, ambient temperature, power supply voltage), and the like. The potential difference causes a difference in the drain currents of the MOS transistors 80 2 and 80 3. There is a case where the reference voltage Vref output from 4 deviates from the set value. Then, the potential difference is detected by comparing the source-drain voltage of the MOS transistors 802 and 803 with the operational amplifier 6, and the detection result is transmitted to the gate electrode of the MOS transistor 804. Thus, the source-drain voltage of the MOS transistor 804 is controlled. With such voltage control, the MOS transistor 8002,

Since the source-drain voltages of 803 are equalized, desired reference voltages VIEN and VIEP can be obtained irrespective of device process variations and operating environment variations.

By supplying the stabilized reference voltages VIEN and VIEP as the control voltage of the constant current source, the stable operation of the constant current source is enabled.

According to the embodiment, the following operation and effect can be obtained.

(1) As shown in Fig. 9, the GTL interface level is based on the reference potential V ref = V ss +0.8 V as the logic threshold, the high level is V ref +0.2 V, The level is set to V ref — 0.2 V, and such a GTL interface level signal cannot directly drive a bipolar transistor. However, the p-channel MOS transistor 11 enables the GTL interface level Is converted to a level that can be captured by the npn-type bipolar transistor 14. The signal thus converted is further converted to a higher level by the bipolar transistor 14. Therefore, a high-speed level conversion of the GTL interface level signal can be performed by a combination circuit of the p-channel type MOS transistor and the npn type bipolar transistor.

(2) The collector electrode of the npn-type bipolar transistor 14 and the source electrode of the channel-type MOS transistor 11 and the 髙 potential side power supply V cc By providing the MOS transistor 13 as a constant current source between the power supply and the power supply, the current flowing therethrough can be limited, so that the power consumption current can be reduced. Further, in this case, one constant current source can be shared by the p-channel type MOS transistor 11 and the npn-type bipolar transistor 14 and the number of elements can be reduced.

(3) By providing MOS transistor 15 as a constant current source between the emitter electrode of npn-type bipolar transistor 14 and low-potential power supply V ss, the level caused by noise of low-potential power supply V ss Variations are less likely to be transmitted to the emitter of the nn-type bipolar transistor 14, so that ground noise can be reduced. This is particularly effective when the low-potential-side power supply Vss is likely to fluctuate due to a large current change in a semiconductor memory device capable of simultaneously outputting multiple bits.

(4) A first conversion circuit 10 for capturing a signal at the GTL interface level, and a second conversion circuit 20 for capturing a reference voltage V ref for logic determination of the GTL interface level signal. When the input buffer is formed including the following, the GTL interface level signal is quickly acquired by applying the level conversion circuit having the above-described operation effect as the first conversion circuit 10 and the second conversion circuit 20. A possible input buffer can be obtained.

(5) Since the level difference between the output signal of the first conversion circuit 10 and the output signal of the second conversion circuit 20 is relatively small, the level difference is amplified by the subsequent differential amplifier circuit 52. By doing so, the level can be set to a sufficient level for the subsequent circuit.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it is needless to say that various modifications can be made without departing from the gist of the invention. . The first conversion circuit 10 and the second conversion circuit 20 shown in FIG. 1 can be configured as follows.

For example, as shown in FIG. 11, an n-channel type MOS transistor 16 for extracting electric charges from the base electrode of the npn type bipolar transistor 14 may be provided. In this case, the gate electrode of the n-channel type MOS transistor 16 is coupled to the gate electrode of the p-channel type MOS transistor 11. According to such a configuration, the charge can be extracted from the base electrode of the npn-type bipolar transistor 14 at a high speed by the n-channel MOS transistor 16, so that the operation can be speeded up.

Further, as shown in FIG. 12, an n-channel MOS transistor 17 may be connected in parallel to a p-channel MOS transistor 11. In such a configuration, for example, even when an input signal at the GTL interface level such as the address signal AO becomes abnormally high, the collector potential of the npn-type bipolar transistor 14 (potential of the level conversion output node) Rise can be limited.

Further, the constant current source on the collector side or the emitter side of the npn-type bipolar transistor 14 may be omitted. For example, a resistance element may be provided instead of the p-channel type MOS transistor 13 forming the constant current source on the collector side of the npn type bipolar transistor 14. Also, the n-channel MOS transistor 15 which is a constant current source on the emitter side of the π n-type bipolar transistor 14 is omitted, and the emitter electrode of the bipolar transistor is directly coupled to the low potential side power supply V ss. Is also good. In addition, the p-channel MOS transistors 12, 15, 22, and 25 shown in FIG. 1 can be omitted. In this case, the emitter electrodes of the bipolar transistors 14 and 24 are directly coupled to the lower potential power supply V ss. You. Further, in FIG. 1, a resistance element can be applied in place of the p-channel type MOS transistors 12, 13, 22, 23.

In the previous embodiment, the address receiver corresponding to the input address signal A0 was described in detail. However, the address receiver corresponding to other address bits, the CS receiver 502, the WE receiver 503, and the clock receiver 51 1. The same configuration as that of the address receiver corresponding to the input address signal A0 can be applied to the write data receiver and the like provided in the data input / output circuit 510. In other words, the same configuration as the address receiver corresponding to the input address signal A0 should be applied to all receivers for taking in signals from the outside of the SRAM by the GTL interface level into the SRAM. Can be. Industrial applicability

In the above description, the case where the invention made by the present inventor is mainly applied to the sink-port eggplant SRAM, which is the application field behind it, has been described. The present invention is not limited to this, and can be widely applied to various semiconductor memory devices such as a dynamic RAM and a read-only memory, and further to a semiconductor integrated circuit such as a microcomputer. The present invention can be applied to the condition that a signal of at least a GTL interface level is acquired.

Claims

The scope of the claims

1. A ρ-channel type field-effect transistor for capturing a signal at the GTL interface level, and an η ρ η-type bipolar transistor disposed at a subsequent stage of the ρ-channel type field-effect transistor The source electrode of the transistor and the collector electrode of the η ρ η type bipolar transistor are coupled to form a level conversion output node, and the drain electrode of the ρ channel type field effect transistor and the π ρ η type bipolar transistor Level conversion circuit that is connected to the base electrode.

2. A gate electrode is coupled to the gate electrode of the ρ-channel type field effect transistor, and a drain electrode is coupled to the base electrode of the πρη-type bipolar transistor. 2. The level conversion circuit according to claim 1, further comprising an η-channel field-effect transistor capable of extracting the electric charge of said base electrode.

3. A gate electrode is connected in parallel with the ρ-channel field-effect transistor, and a gate electrode is connected to the gate electrode of the ρ-channel field-effect transistor to limit a rise in the potential of the level conversion output node. 2. The level conversion circuit according to claim 1, comprising an η-channel type field effect transistor.

4. The level conversion circuit according to claim 1, wherein a constant current source is provided between the level conversion output node and the 髙 potential side power supply.

5. The level conversion circuit according to claim 1, wherein a constant current source is provided between the emitter electrode of the ηρη type bipolar transistor and the low-potential-side power supply.

6. a first conversion circuit for capturing a signal at the GTL interface level; A second conversion circuit for taking in a reference voltage for determining the logic value of the GTL interface level signal is provided, and an external signal is taken in through the first and second conversion circuits. The first conversion circuit is a p-channel field-effect transistor for taking in a signal at a GTL interface level, and is disposed after the p-channel field-effect transistor. The source electrode of the p-channel field-effect transistor and the collector electrode of the npn-type bipolar transistor are combined to form a level conversion output node; A drain electrode of the effect transistor and a base electrode of the np π-type bipolar transistor are coupled to each other; The path includes a p-channel field-effect transistor for capturing the reference voltage, and an npn-type bipolar transistor disposed after the p-channel field-effect transistor, and a source of the P-channel field-effect transistor. The electrode is coupled to the collector electrode of the npn-type bipolar transistor to form a level conversion output node, and the drain electrode of the p-channel field-effect transistor is coupled to the base electrode of the npn-type bipolar transistor. And an input buffer circuit.

7. In each of the first conversion circuit and the second conversion circuit, a gate electrode is coupled to a gate electrode of the p-channel field-effect transistor, and a drain electrode is connected to a base electrode of the npn-type bipolar transistor. 7. The input buffer circuit according to claim 6, further comprising an n-channel type field-effect transistor coupled and capable of extracting a charge of a base electrode of the npn-type bipolar transistor.

8. In each of the first conversion circuit and the second conversion circuit, the gate electrode is connected in parallel with the P-channel field effect transistor. 7. The semiconductor device according to claim 6, further comprising an n-channel field-effect transistor connected to a gate electrode of the p-channel field-effect transistor for limiting a rise in the potential of the level conversion output node. Input buffer circuit.

9. The input buffer according to claim 6, wherein in each of the first conversion circuit and the second conversion circuit, a constant current source is provided between the level conversion output node and a high potential side power supply. circuit.

10. The method according to claim 6, wherein in each of the first conversion circuit and the second conversion circuit, a constant current source is provided between an emitter electrode of the η ρ π-type bipolar transistor and a low potential side power supply. Input buffer circuit as described.

11. The input buffer circuit according to claim 6, further comprising a differential amplifier circuit for amplifying a level difference between an output signal of the first conversion circuit and an output signal of the second conversion circuit.

12. The input buffer circuit according to claim 11 and a logic circuit for performing processing using an output of the differential amplifier circuit provided in the input buffer circuit are formed on one semiconductor substrate. Semiconductor integrated circuit.

13. In each of the first conversion circuit and the second conversion circuit provided in the input buffer circuit, a gate electrode is coupled to a gate electrode of the ρ-channel type field effect transistor, and a drain electrode is provided. And a η-channel type field-effect transistor coupled to a base electrode of the ηρη-type bipolar transistor and capable of extracting electric charges from the base electrode of the ηρη-type bipolar transistor. 12. The semiconductor integrated circuit according to item 2.

14. In each of the first conversion circuit and the second conversion circuit provided in the input buffer circuit, the ρ channel type field effect transistor is connected in parallel, and the gate electrode is connected to the Ρ channel type field effect transistor. 13. The semiconductor integrated circuit according to claim 12, further comprising an n-channel type field effect transistor connected to a gate electrode of a transistor for limiting a rise in the potential of the level conversion output node.

15. In each of the first conversion circuit and the second conversion circuit included in the input buffer circuit, a constant current source is provided between the level conversion output node and the 髙 potential side power supply. 13. The semiconductor integrated circuit according to item 12.

16. In each of the first conversion circuit and the second conversion circuit provided in the input buffer circuit, a constant current source is provided between the emitter electrode of the npn-type bipolar transistor and the low-potential-side power supply. 3. The semiconductor integrated circuit according to item 1 2.