WO1996004685A1 - A power semiconductor device - Google Patents

A power semiconductor device Download PDF

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Publication number
WO1996004685A1
WO1996004685A1 PCT/GB1995/001857 GB9501857W WO9604685A1 WO 1996004685 A1 WO1996004685 A1 WO 1996004685A1 GB 9501857 W GB9501857 W GB 9501857W WO 9604685 A1 WO9604685 A1 WO 9604685A1
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WO
WIPO (PCT)
Prior art keywords
region
transistor
semiconductor device
recombination centres
junctions
Prior art date
Application number
PCT/GB1995/001857
Other languages
French (fr)
Inventor
David Arthur Garnham
Koenraad Teunis Francis Rutgers
Original Assignee
Texas Instruments Limited
Texas Instruments Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Limited, Texas Instruments Incorporated filed Critical Texas Instruments Limited
Priority to JP8506343A priority Critical patent/JPH10512396A/en
Priority to DE69524419T priority patent/DE69524419T2/en
Priority to EP95927852A priority patent/EP0774167B1/en
Publication of WO1996004685A1 publication Critical patent/WO1996004685A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H01L29/66295—Silicon vertical transistors with main current going through the whole silicon substrate, e.g. power bipolar transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/221—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities of killers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1012—Base regions of thyristors
    • H01L29/102—Cathode base regions of thyristors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body

Definitions

  • the present invention provides, in a sixth aspect, a method of making a semiconductor device comprising two or more p-n junctions in series and including a region of a first conductivity type that is bordered by two p-n junctions, the method comprising ion implanting, with a chemical species that gives rise to recombination centres, part of the first region through which, in the use of the device, the majority of the current conducted through the p-n junctions bordering the first region does not flow.
  • Figure 2 shows the transistor of Figure 1 in plan at the stage of production before the metal layer has been added. Only a single transistor is shown although usually many transistors are made on the substrate which is divided up when the transistors are completed. The location of the cross section of Figure 1 is marked on Figure 2 at I-I.
  • the anode region of the diode may receive a same gold implant, which may be achieved by opening windows in the oxide and the photoresist to expose the anode region, in addition to the part of the base region that will be under the base bond pad, and implanting into both regions at the same time.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

A semiconductor device having two or more p-n junctions, being in particular a bipolar transistor or a thyristor. The device has a gold ion implant (14) in a region of the device between two of or the two p-n junctions, which region is the base (2) in the case of a bipolar transistor, located away from the current carrying active region of the device. The device has a low resistance and may be turned off rapidly because the implanted gold provides recombination centres which act as a sink for carriers drawing them from the active region.

Description

A POWER SEMICONDUCTOR DEVICE
The present invention relates to semiconductor devices, especially to power semiconductor devices, for example, bipolar transistors.
In many applications of power bipolar transistors it is desirable for such a transistor to have both a short switching time and a small voltage between the emitter and collector of a transistor when the saturation current is flowing through it (Vce sat) * the latter ensures that power dissipated in the transistor is kept to a minimum. Those two objectives have not previously been achieved in the same transistor.
At present there are two types of power transistor using planar technology in which transistors are formed at the surface of a semiconductor substrate. The transistors are used in such applications as driving fluorescent lighting tubes at high frequencies.
The first type of transistor is optimised to have a short switching time. That is achieved by damaging the surface layer of the substrate by grinding with alumina grit before the transistors are formed in that layer. That process forms a large number of recombination centres with the result that the lifetime of the carriers is greatly reduced. That in turn has the result that the transistors may be rapidly switched off. Unfortunately the damage makes the semiconductor material more resistive and therefore increases Vce sat of the transistor. The damage also reduces the current gain (hfe) of the transistor.
The second type of transistor is optimised to have a small Vce saf To achieve that the substrate is etched before the transistors are formed to expose a fresh damage-free surface. The semiconductor material making up the transistors therefore has a low resistance resulting in transistors of a low Vce saf Tne corresponding long lifetime of carriers in the transistors means that the transistors cannot, however, be rapidly switched off.
It is an object of the present invention to provide a transistor that has a small Vce sat and a short switching time.
The present invention provides, in a first aspect, the use, in a semiconductor device comprising two or more p-n junctions in series and including a region of a first conductivity type that is bordered by two p-n junctions, of recombination centres that are located away from the part of the region of a first conductivity type through which the majority of the current conducted between the p-n junctions bordering the region of the first conductivity type flows, to draw carriers from that part to increase the rapidity with which the semiconductor device may be turned off.
The drawing of the carriers from the active region through which the current mainly flows is made use of in the following aspects of the invention.
The present invention provides, in a second aspect, a semiconductor device comprising two or more p-n junctions in series and including a region of a first conductivity type that is bordered by two of or the two p-n junctions, a region of added recombination centres that are located within the region of the first conductivity type away from that part of that region through which the majority of the current conducted between the p-n junctions bordering that region flows, wherein that part of that region is substantially free from added recombination centres.
The present invention provides, in a third aspect, a semiconductor device comprising two or more p-n junctions in series and including a region of a first conductivity type that is bordered by two p-n junctions, a region of added recombination centres that are located away from the part of that region through which the main part of the current conducted between the p-n junctions bordering that region flows, wherein material of the semiconductor device is silicon, the recombination centres are gold and the concentration of the recombination centres is less than 2 x 1013 cm-2.
In the first, second and third aspects, the semiconductor device may be a bipolar transistor, in which case the region of the first conductivity type is the base region of the transistor and is bordered by emitter and collector regions.
In those aspects the semiconductor device may be a thyristor.
In those aspects of the invention, the region of extrinsic recombination centres may be located entirely within the region of the first conductivity type or the base region as the case may be.
The present invention provides, in a fourth aspect, a bipolar transistor comprising emitter, base and collector regions and having a region of added recombination centres located in the base region away from the part of the base region through which the majority of the current conducted between the emitter and collector regions flows.
The present invention provides in a fifth aspect a bipolar transistor having an ion implant in a selected region wherein the transistor, as compared to a transistor identical to the claimed transistor but without the ion implant, has a minimum time in which the transistor may be turned off reduced by 5% or more and a vce,sat increased by less than 10%.
In the fourth and fifth aspects of the invention the region of added recombination centres may be located entirely within the base region.
The region of the recombination centres or the ion implant may be located away from the region of the transistor or semiconductor device through which flows substantially all the current flowing between the two p-n junctions, or may be located to one side of the of the current flowing between the two p-n junctions, or may be located in a region of the semiconductor device where, when the device is conducting, the current density is less than 1%, or is less than 0.1%, of the maximum current density present in the device or transistor.
The material of the semiconductor device or the transistor may be silicon.
The added recombination centres may be platinum, argon or, preferably, gold.
The concentration of the gold is advantageously less than 2 x 1013 atoms cm-2 and may be between 1 x 1012 and 2 x 1013 atoms cm"2 and is preferably about 1 x 1013 atoms cm-2.
The region of added recombination centres may be divided into a plurality of separate sub-regions.
The region of added recombination centres or a sub- region thereof may be located under a bond pad.
The region of added recombination centres may be made by ion implantation, which may be effected through a window in a layer of material that in the finished device insulates semiconductor material from metallisation; preferably the insulating material and any other windows in that material are protected during the implantation by a mask.
The present invention provides, in a sixth aspect, a method of making a semiconductor device comprising two or more p-n junctions in series and including a region of a first conductivity type that is bordered by two p-n junctions, the method comprising ion implanting, with a chemical species that gives rise to recombination centres, part of the first region through which, in the use of the device, the majority of the current conducted through the p-n junctions bordering the first region does not flow.
A transistor according to the invention may be integrated on the same substrate as a diode connected between the emitter and collector of the transistor to conduct current in the opposite sense to the current carried by the transistor in the active mode. That diode may also have added recombination centres.
The region of recombination centres results in the time in which the semiconductor device, a transistor for example, may be switched off being short; as the base current is reduced as the transistor is switched off, the carriers stored in the base are drawn to the implanted region where they recombine. Since the active region has not been implanted, the resistance of the device, and therefore, in the case of a bipolar transistor, Vce sat and hre, are not affected.
There will now be described, by way of example only, a power bipolar transistor according to the present invention with reference to the accompanying drawings, of which:
FIGURE 1 is a cross section of a bipolar transistor after the metallisation stage has been completed.
FIGURE 2 shows the transistor of figure 1 in plan at the stage of production just before the metallisation stage.
Figure 1 is a cross section of a bipolar transistor formed at the surface of an n-type silicon substrate 1. The base region of the transistor is provided by a p-type region 2 formed at the surface of the substrate 1. The emitter region of the transistor is provided by an n-type region 3 formed at the surface of the substrate within the base region 2. The collector of the transistor is provided by the remainder of the substrate 1. The base region is ringed by a deeper, less heavily doped p-type region .5 which increases the breakdown voltage of the transistor.
A layer of oxide 6 grown by oxidising the silicon of the substrate overlies the substrate. The oxide 6 has windows 7, 8 and 9. An aluminium metal layer overlies the oxide layer and makes contact to the base 2 and emitter 3 regions through the windows in the oxide. The metal layer is patterned into two separate regions. The first provides a base bond pad 11 and a base contact 12, and the second provides an emitter contact 13 and an emitter bond pad (figure 2) .
The metal layer is formed by the conventional process of depositing a layer of aluminium which is sintered to from a eutectic with the silicon for ohmic contact and mechanical strength, followed by etching to pattern it.
A collector contact 17 is formed on the rear side of the substrate 1.
Figure 2 shows the transistor of Figure 1 in plan at the stage of production before the metal layer has been added. Only a single transistor is shown although usually many transistors are made on the substrate which is divided up when the transistors are completed. The location of the cross section of Figure 1 is marked on Figure 2 at I-I.
Referring to Figures 1 and 2, the base region 2 is a large rectangular region within which the emitter region 3 is formed in a fingered shape. The fingered shape is used to obtain the large current capability required of a power transistor. The window 8 has the same shape so that electrical contact may be made to all parts of the emitter region 3 with the emitter contact 12. The window 7 through which connection is made to the base region 2, with the base contact 12, is also fingered and is interdigitated with the window 8.
The methods by which the structures described above may be made are well known.
The window 9 in the oxide layer 6 is large and has the metal base bond pad 11 deposited over it. The base bond pad is used to connect the base region 2 to the base terminal of the packaged transistor. A second bond pad, via which connection is made between the emitter region 3 and the emitter terminal of the packaged transistor, is formed on top of the oxide so that this bond pad is insulated from the base region 2. The location of where the second bond pad is formed is marked in Figure 2 with a box 10 outlined with a dash-dot line.
At the stage of production shown in Figure 2, a photoresist mask is formed over the transistor with a window leaving the window 9 in the oxide exposed. Gold is implanted through the windows in the photoresist and the oxide into the base region 2 of the transistor. An accelerating voltage of 80 keV for the gold ions is used. The photoresist is removed and the transistor is annealed at 930 °C for 5 minutes in an oxidising atmosphere to repair the damage caused by the implantation; the oxide that grows over the windows in the oxide layer 6 during the anneal step is removed by etching. The result of the implantation is that part of the base region has gold recombination centres having a concentration of 1 x 1013 cm"2. That concentration may be measured by integrating the concentration profile of gold atoms produced a secondary ion mass spectrometer.
Figure 1 shows the region 14 under the base bond pad 11 that is implanted with gold and has a high carrier recombination rate. The effect of the gold implanted region 14 on the operation of the transistor is thought to be as follows.
When the transistor is conducting current between the emitter and the collector, the majority of that current flows through base region 2 through the part of the base region below the emitter region 3. That part of the base region is known as the "active" part. Since the gold implant is not on the current path through the emitter region 3, the base region 2 and the collector region 1, the implant does not cause any additional resistance to current flow along that path and so Vce sa^ is not increased. The current flow is represented in Figure 3 by arrows 15. The direction of those arrows indicates the direction of conventional current.
While a bipolar transistor is conducting there is a large charge of minority carriers (in this case electrons) stored in the active part of the base region. These have to removed if the transistor is to be turned off so that only leakage current passes between the emitter and the collector. The gold implanted region 14 acts as a sink for minority carriers in the base. That is because the carrier lifetime in that region is short because the added gold atoms provide extra recombination centres which means that the concentration of minority carriers in that region is low. There is, therefore, a concentration gradient between the active part of the base region and the gold implanted region 14, which gradient causes a diffusion current drawing minority carriers from the active part of the base region. That diffusion current is represented by a dashed arrow 16 in
Figure 3. While the transistor is being turned off by reducing the voltage between the base and the emitter, the diffusion current caused by the gold implant aids in the reduction of the concentration of minority carriers in the active part of the base region and so reduces the time it takes for the transistor to be turned off.
A series of transistors was made with concentrations of the implanted gold atoms of 1 x 1012, 5 x 1012, 1 x 1013 and 2 x 1013 cm-2 respectively. The first of those was found to have a switching time of barely less than the same transistor made with no gold implant. It was found that as the concentration was increased the time for the device to be switched off was reduced. At 2 x 1013 cm-2 an increase in Vce sa , relative to a similar device without the gold implant, was noted but not to an unacceptable value.
It is not necessary for the region of recombination centres to be located underneath the bond pad, but that location is convenient as it does not require that any extra space be used for the region.
In large devices it may be desirable to provide more than one region of recombination centres distributed across the device to ensure that all parts of the device that carry the major part of the current are sufficiently close to the recombination centres to provide a carrier concentration gradient and hence the diffusion current generated sufficient to draw the carriers from the active region and turn the device off as quickly as is desired.
An example of a method by which a bipolar transistor as illustrated in Figures 1 and 2 may be made is as follows. A 100 mm diameter of n-type 60-80 Ω cm float- zone silicon having a thickness of 635 μm (25 mils) is phosphorus doped at 1200 °C for 4 hours using POCI3 as the source of phosphorus. The wafer is then annealed at 1325 "c for 156 hours. The resulting phosphorus doped regions extend 240 μm (9.5 mils) from both sides of the wafer. The upper phosphorus doped region is removed by grinding to leave a wafer 355 μm (14 mils) thick.
The top surface of the wafer is then polished and the base and emitter regions of a plurality of transistors are formed at that surface. The phosphorus doping in the lower two thirds of the wafer serves to reduce the collector resistance of the finished transistors.
The region 5 for increasing the breakdown voltage and the base region 2 are formed using two boron ion- implantation stages.
For the region 5, an oxide mask layer of 0.8 μm thickness is grown in an oxidising atmosphere and is patterned to expose a window. Through that window 7.0 x 1012 ions cm"2 are implanted and the wafer is annealed for 60 hours at 1300 *C. The boron penetrates the wafer to a depth of 4.4 μm. The anneal is performed in an oxidising atmosphere which results in more oxide forming in the window.
For the base region 2, a new window in the oxide layer is opened and 5.2 x 1014 ions cm"2 are implanted. The wafer is then annealed for 2.2 hours at 1300 'C in an oxidising atmosphere.
A further window is then opened in the oxide layer and the emitter region 3 is phosphorus doped through that window by exposing the wafer to POCI3 for 110 minutes at 110 βC. The phosphorus penetrates to a depth of 0.62 μm.
The next stage is to ion-implant the gold region 14. Oxide covering the window 9 is first removed and then a layer of photoresist is spun onto the wafer and is patterned to expose a window extending over most of the window 9 to just inside its perimeter. 1 x 1013 ions cm"2 of gold are then ion-implanted through the window in the photoresist and through the window 9 in the oxide into the part of base region that will be under the base bond pad. An accelerating voltage of 80 keV is used. The photoresist is then removed and the wafer is annealed at 930 °C for 5 minutes in an oxidising atmosphere.
The oxide covering each of the windows 7, 8 and 9 is then removed by etching and the aluminium layer is then deposited on the top surface of the wafer and patterned. An aluminium layer is also deposited on the bottom surface of the wafer to act as the collector contact 17. The wafer is divided into chips having a single transistor on each.
As mentioned above an antiparallel diode connected between the emitter and the collector may be integrated on each chip. The diode is preferably formed using another boron ion-implantation stage between the two described above. A window in the oxide layer is opened and 5.2 x 1014 ions cm"2 are implanted into the n-type substrate to form the anode of the diode. The wafer is then annealed for 2.2 hours at 1300 °C in an oxidising atmosphere. The anode penetrates the wafer to a depth of 0.64 μm.
The anode region of the diode may receive a same gold implant, which may be achieved by opening windows in the oxide and the photoresist to expose the anode region, in addition to the part of the base region that will be under the base bond pad, and implanting into both regions at the same time.
When an antiparallel diode is integrated with the transistor, a separate emitter bond pad need not be provided; an aluminium connection to the anode of the diode may serve as a bond pad for connecting to both the anode and the emitter.

Claims

CLAIMS :
1. The use, in a semiconductor device comprising two or more p-n junctions in series and including a region of a first conductivity type that is bordered by two p-n junctions, of recombination centres that are located away from the part of the region of a first conductivity type through which the majority of the current conducted between the p-n junctions bordering the region of the first conductivity type flows, to draw carriers from that part to increase the rapidity with which the semiconductor device may be turned off.
2. A semiconductor device comprising two or more p-n junctions in series and therefore including a region of a first conductivity type that is bordered by two p-n junctions, a region of added recombination centres that are located within the region of the first conductivity type away from that part of that region through which the majority of the current conducted between the p-n junctions bordering that region flows, wherein that part of that region is substantially free from added recombination centres.
3. A semiconductor device comprising two or more p-n junctions in series and including a region of a first conductivity type that is bordered by two p-n junctions, a region of added recombination centres that are located away from the part of that region through which the majority of the current conducted between the p-n junctions bordering that region flows, wherein the recombination centres are gold and the concentration of the recombination centres is less than 2 x 1013 cm"2.
4. A use as claimed in claim 1, or a semiconductor device as claimed in claim 2 or claim 3, wherein the semiconductor device is a bipolar transistor, the region of the first conductivity type being the base region of the transistor and bordered by emitter and collector regions.
5. A use as claimed in claim 1, or a semiconductor device as claimed in claim 2 or claim 3, wherein the semiconductor device is a thyristor.
6. A use as claimed in claim 1 or claim 4 or claim 5, or a semiconductor device as claimed in any one of claims 2 to 4, wherein the region of added recombination centres is located entirely within the region of the first conductivity type.
7. A bipolar transistor comprising emitter, base and collector regions and having a region of added recombination centres located in the base region away from that part of the base region through which the majority of the current conducted between the emitter and collector regions flows.
8. A bipolar transistor having an ion implant in a selected region wherein the transistor, as compared to a transistor identical to the claimed transistor but without the ion implant, has a minimum time in which the transistor may be turned off reduced by 5% or more and a vce sat increased by less than 10%.
9. A transistor as claimed in claim 7 or claim 8, wherein the region of added recombination centres is located entirely within the base region.
10. A use as claimed in any one of claims 1, 4, 5 and 6, or a semiconductor device as claimed in any one of claims 2 to 6, or a transistor as claimed in any one of claims 7 to 9, wherein the region of the recombination centres or the ion implant is located away from the region of the semiconductor device or transistor through which flows substantially all the current flowing between the two p-n junctions.
11. A use as claimed in any one of claims 1, 4, 5, 6 and 10, or a semiconductor device as claimed in any one of claims 2 to 6 and 10, or a transistor as claimed in any one of claims 7 to 10, wherein the region of the recombination centres or the ion implant is located to one side of the current flowing between the two p-n junctions.
12. A use as claimed in any one of claims 1, 4, 5, 6, 10 and 11, or a semiconductor device as claimed in any one of claims 2 to 6, 10 and 11, or a transistor as claimed in any one of claims 7 to 11, wherein the region of recombination centres or the ion implant is located in a region of the semiconductor device or transistor where, when the device is conducting, the current density is less than 1% of the maximum current density present in the device or transistor.
13. A use, semiconductor device or transistor as claimed in claim 12, wherein the region of recombination centres or the ion implant is located in a region of the semiconductor device or transistor where, when the device is conducting, the current density is less than 0.1% of the maximum current density present in the device or transistor.
14. A use as claimed in any one of claims 1, 4, 5, 6 and 10 to 13, or a semiconductor device as claimed in any one of claims 2 to 6 and 10 to 13, or a transistor as claimed in any one of claims 7 to 13, wherein the added recombination centres are gold.
15. A use, or a semiconductor device, or a transistor, as claimed in claim 14, wherein the concentration of the gold is less than 2 x 1013 atoms cm"2.
16. A use, or a semiconductor device, or a transistor, as claimed claim 15, wherein the concentration of the gold is between 1 x 1012 and 2 x 1013 atoms cm"2.
17. A use, or a semiconductor device, or a transistor, as claimed in claim 16, wherein the concentration of the gold is 1 x 1013 atoms cm"2.
18. A use as claimed in any one of claims 1, 4, 5, 6 and 10 to 13, or a semiconductor device as claimed in any one of claims 2 to 6 and 10 to 13, or a transistor as claimed in any one of claims 7 to 13, wherein the added recombination centres are platinum.
19. A use as claimed in any one of claims 1, 4, 5, 6 and 10 to 13, or a semiconductor device as claimed in any one of claims 2 to 6 and 10 to 13, or a transistor as claimed in any one of claims 7 to 13, wherein the added recombination centres are argon.
20. A use as claimed in any one of claims 1, 4, 5, 6, and 10 to 19, or a semiconductor device as claimed in any one of claims 2 to 6 and 10 to 19, or a transistor as claimed in any one of claims 7 to 19, wherein the region of added recombination centres is divided into a plurality of separate sub-regions.
21. A use as claimed in any one of claims 1, 4, 5, 6, and 10 to 20, or a semiconductor device as claimed in any one of claims 2 to 6 and 10 to 20, or a transistor as claimed in any one of claims 7 to 20, wherein the region of added recombination centres or a sub-region thereof is located under a bond pad.
22. A use as claimed in any one of claims 1, 4, 5, 6, and 10 to 21, or a semiconductor device as claimed in any one of claims 2 to 6 and 10 to 21, or a transistor as claimed in any one of claims 7 to 21, wherein the region of added recombination centres is made by ion implantation.
23. A use, or a semiconductor device, or a transistor, as claimed in claim 21, wherein the ion implantation is effected through a window in a layer of material that in the finished device insulates semiconductor material from a metal layer.
24. A method of making a semiconductor device comprising two or more p-n junctions in series and including a region of a first conductivity type that is bordered by two p-n junctions, the method comprising ion implanting, with a chemical species that gives rise to recombination centres, part of the first region through which, in the use of the device, the main part of the current conducted through the p-n junctions bordering the first region does not flow.
25. A method as claimed in claim 24, wherein the ion implantation is effected through a window in a layer of material that in the finished device insulates semiconductor material from a metal layer.
26. A method as claimed in claim 24 or claim 25, wherein the semiconductor device is a bipolar transistor.
27. A bipolar transistor substantially as herein described with reference to, and as illustrated by, Figures 1 and 2 of the accompanying drawings.
28. A method of making a bipolar transistor substantially as herein described with reference to and as illustrated by Figures 1 and 2 of the accompanying drawings.
29. An integrated circuit comprising a bipolar transistor as claimed in any one of claims 7 to 23, and 27, or as made by the method of claim 26 or claim 28, or a semiconductor device as claimed in claim 4 or in any one of claims 5, 6 and 10 to 23 when dependent on claim
4, and comprising a diode connected between the emitter and collector of the transistor, or between the anode and cathode of the semiconductor device, to conduct current in the opposite sense to the current carried by the transistor, or the semiconductor device, in the active mode.
30. An integrated circuit as claimed in claim 29, wherein the diode has added recombination centres.
31. An electronic ballast for an fluorescent tube, comprising a bipolar transistor as claimed in any one of claims 7 to 23, and 27, or as made by the method of claim 26 or claim 28, or a semiconductor device as claimed in claim 4 or in any one of claims 5, 6 and 10 to 23 when dependent on claim 4, or an integrated circuit as claimed in claim 29.
PCT/GB1995/001857 1994-08-05 1995-08-04 A power semiconductor device WO1996004685A1 (en)

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JP8506343A JPH10512396A (en) 1994-08-05 1995-08-04 Power semiconductor device
DE69524419T DE69524419T2 (en) 1994-08-05 1995-08-04 POWER SEMICONDUCTOR DEVICE
EP95927852A EP0774167B1 (en) 1994-08-05 1995-08-04 A power semiconductor device

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GB9415874.8 1994-08-05
GB9415874A GB2292252A (en) 1994-08-05 1994-08-05 Rapid turn off semiconductor devices

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US20020102958A1 (en) * 2001-01-29 2002-08-01 Buer Kenneth V. Sub-harmonically pumped k-band mixer utilizing a conventional ku-band mixer IC
JP5061407B2 (en) * 2001-01-31 2012-10-31 富士電機株式会社 Semiconductor device and manufacturing method thereof
JP4856419B2 (en) * 2005-11-29 2012-01-18 ルネサスエレクトロニクス株式会社 Bidirectional planar diode

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EP0341000A2 (en) * 1988-05-02 1989-11-08 General Electric Company Gated turn-off semiconductor device

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EP0774167A1 (en) 1997-05-21
EP0774167B1 (en) 2001-12-05
DE69524419T2 (en) 2002-08-01
US6093955A (en) 2000-07-25
GB2292252A (en) 1996-02-14
GB9415874D0 (en) 1994-09-28
DE69524419D1 (en) 2002-01-17
JPH10512396A (en) 1998-11-24

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