WO1996003800A1 - Circuit d'extraction de signal d'horloge autoreglable, haute vitesse, a detection de frequence - Google Patents

Circuit d'extraction de signal d'horloge autoreglable, haute vitesse, a detection de frequence Download PDF

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Publication number
WO1996003800A1
WO1996003800A1 PCT/US1994/008223 US9408223W WO9603800A1 WO 1996003800 A1 WO1996003800 A1 WO 1996003800A1 US 9408223 W US9408223 W US 9408223W WO 9603800 A1 WO9603800 A1 WO 9603800A1
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WIPO (PCT)
Prior art keywords
signal
circuit
sample
phase
output
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PCT/US1994/008223
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English (en)
Inventor
Aaron W. Buchwald
Original Assignee
The Regents Of The University Of California
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Publication date
Application filed by The Regents Of The University Of California filed Critical The Regents Of The University Of California
Priority to US08/392,958 priority Critical patent/US5757857A/en
Priority to PCT/US1994/008223 priority patent/WO1996003800A1/fr
Priority to CA002171734A priority patent/CA2171734A1/fr
Publication of WO1996003800A1 publication Critical patent/WO1996003800A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H04L7/0274—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit with Costas loop

Definitions

  • the invention relates to the field of clock extraction circuits used in digital communication, and in particular, to a high speed self-adjusting clock extraction circuit used with nonreturn-to-zero (NRZ) data.
  • NRZ nonreturn-to-zero
  • Communication of information using digital methods is preferable in most instances to analog methods due to the immunity to interference, error correcting channel coding methodologies available, time division multiplexing of signals for increased channel usage, and source coding for efficient information transfer, which is available in the digital format.
  • information is transmitted digitally, it is broken into a sequence of symbols belonging to a finite alphabet. In order to receive these signals, the receiver must by synchronized with the incoming data such that the information can be sampled at the appropriate time.
  • a receiver In a video system, a receiver must recognize individual bits. Therefore, a clock in a video system must exist at the bit rate to provide bit level synchronization. Bits are ordered into larger groups, called bytes, which in turn are reordered into even still larger groups designated as lines, which in turn are organized into larger groups still, defined as frames. For video operation, a receiver must know when the beginning of each frame occurs. Usually, synchronization at the frame and line levels is determined by software and system protocols. However, at the lowest level, bit synchronization must occur, otherwise there will be no intelligible information available to make software controlled decisions at higher levels.
  • a common modulation format for digital data is the nonreturn to zero (NRZ) format, which is also known on-off keying because the signal is on for one binary state, and off for the other.
  • the binary NRZ signal makes transitions from one binary state to the other only when there is a change in the bit value.
  • the signal 111 in NRZ format will be an unbroken high logic level for three bit intervals. If the signal should then become 1110, a negative transition will occur after three bit intervals and a single bit interval will be at the low logic level where the signal will remain until a logical 1 is again to be represented.
  • NRZ format is that is does not occupy as much bandwidth as other digital formatting schemes, such as return-to-zero (RZ) or Manchester coding. Further, about 90 percent of the signal energy of NRZ data is contained with in the bit rate frequency, B , and about 80 percent of the energy lies within a frequency of B ⁇ -
  • a convenient way to picture random digital data is to superimpose sections of the digital signal separated by integer multiples of the bit period T. Such a plot is called an "eye diagram" and illustrates the structure inherent in random data.
  • Figure 1 is a block diagram of a typical prior art fiber optic receiver, generally denoted by reference numeral 10, associated with eye diagrams of the data and clock signals at various nodes within the circuit.
  • the eye diagram of Figure 2a is the input data signal provided at input 10 to preamplifier 14.
  • the dispersion of the optical fiber typically band limits the data, therefore, the square wave NRZ data is modeled in this example as having sinusoidal transitions between the high and low logic states.
  • the input signal is shown without noise and is very weak so that it must be amplified by preamplifier 14, where it is unavoidably corrupted by noise so that the form at output 16 appears as shown in the eye diagram of Figure 2b.
  • the noise of the preamplifier generally determines the overall signal-to-noise ratio of the receiver, as the input signal is weakest at input 12 of receiver circuit 10.
  • FIG. 2c is an eye diagram of the filtered data and recovered clock signal at output 20 of post-amplifier 18. Note that the recovered clock signal undergoes a positive transition 22 at the center of each bit interval.
  • a decision circuit 24 compares the received data with the zero voltage level on every positive zero crossing of 22 of the clock and makes a decision as to the polarity of the bit. This process is known as retiming the data because the weak input signal is cleaned, regenerated and synchronized or retimed to a local clock.
  • the eye diagram of the retimed data and recovered clock are then provided at output 26 of decision circuit 24 as shown in the eye diagram of Figure 2d.
  • the clock signal is extracted from output 20 by a clock extraction circuit 28 and reinserted into decision circuit 24 for retiming the data.
  • a demultiplexer 32 is coupled to output 26, typically to demultiplex interleaved multiple digital signals transmitted in the fiber optic through circuit 10.
  • recovering a clock signal from random data is crucial to the error-free operation of any receiver circuit.
  • the decision circuit must also sample data at an appropriate time, otherwise its performance will degrade. Because the input data is random, there will be random phase reversals in the data which eliminate any strong spectral component in the data input stream.
  • Prior art clock extraction circuits from NRZ data can be classified in two main categories: (a) open loop filters; and (b) closed looped synchronizers.
  • open loop filters have almost exclusively been used in high bit rate receivers.
  • the periodic timing information is extracted from the data by first using a nonlinear edge enhancement circuit to generate a spectral line at the bit rate.
  • a signal is then passed through a narrow band filter centered at the bit rate frequency.
  • SAW surface-acoustic-wave
  • the open loop technique suffers from instabilities and nonlinear problems, such as frequency acquisition and cycle slipping. Further, open loop systems usually need to be manually adjusted to center the clock edge in the bit interval. A one-time manual adjustment clearly does not track phase offsets due to temperature variations and component aging.
  • the filter in the open looped circuit is also generally external to the receiver electronics and is bulky, leading to both packaging and interconnection problems.
  • the closed looped synchronizer is integratable and can continually compensate for changes in the environment and input bit rate.
  • the closed loop system requires a voltage control oscillator (VCO) to be tuned by a suitably filtered error signal in order to align the transitions of the clock to the center of the bit interval.
  • VCO voltage control oscillator
  • the invention is a clock recovery circuit for establishing bit synchronization with an NRZ data formatted bit stream.
  • the circuit comprises a matched filter for receiving the NRZ bit stream for producing a filtered output signal indicative of edge transitions in the bit stream.
  • a first and second sample and hold circuit have inputs coupled to the matched filter.
  • a sample and hold circuit shall be defined to include any circuit which performs an equivalent function to a sample and hold circuit, such as a tracking and hold circuit.
  • the sample and hold circuits are complementarily clocked by a VCO signal.
  • the first sample and hold circuit holds in- phase samples and the second sample and hold second holds quadrature samples.
  • a third sample and hold circuit having an input coupled to the second sample and hold circuit.
  • the third sample and hold circuit is clocked on positive and negative transitions of a data output signal generated from the first sample and hold circuit.
  • a multiplier multiplies or corrects the sign of the quadrature sample signal output from the third sample and hold circuit.
  • a lowpass filter is coupled to the multiplier and filters output of the multiplier to obtain a DC value of phase error between the data output signal and the quadrature sample or what can be thought of as the data crossover sample.
  • a variable controlled oscillator (VCO) has its control input coupled to the filter. The variable controlled oscillator generates the VCO signal with a controllable phase according to the DC value provided by the filter.
  • the VCO is coupled to the first and second sample and hold circuits to complementarily clock the first and second sample and hold circuits.
  • a data transition tracking loop which is high speed, inherently self-adjusting, is independent of data transition density with significantly reduced ripple in the error signal generated by the multiplier.
  • the circuit further comprises a limiter coupled to the output of the first sample and hold circuit.
  • the limiter has its output coupled to the multiplier so that output of the multiplier, which is representative of phase error, is monotonic across the phase error signal centered on a bit interval.
  • the output of the limiter is the data output signal.
  • the phase error signal output by the multiplier is a sawtooth wave form.
  • the circuit further comprising another limiter coupled to the VCO signal of the
  • VCO for generating a clock signal indicative of a recaptured clock from the data bit stream.
  • circuit further comprising a frequency lock detector for providing a frequency error signal to the VCO.
  • the VCO is responsive to the frequency error signal to shift frequency of the VCO in alignment with bit rate frequency of the data stream prior to phase lock.
  • the frequency lock detector is enabled only when absolute value of phase error exceeds a predetermined threshold.
  • the circuit is arranged and configured to operate in a bit interleaved fashion so that the first and second sample and hold circuits each comprise a pair of complementarily clocked tracking and hold circuits having their input coupled to the matched filter and a multiplexer having its inputs coupled to outputs of the pair of tracking and hold circuits.
  • the tracking and hold circuits are complementarily clocked by selected outputs from the VCO.
  • the VCO has a lead output, Q, and an lag output, I.
  • the tracking and hold circuits of the first sample and hold circuit are clocked by the lag output from the VCO while the pair of tracking and hold circuits of the second sample and hold circuit are clocked by the lead output from the VCO.
  • the third sample and hold circuit comprises a pair of complementarily clocked tracking and hold circuits complementarily clocked by the data output signal and having their input coupled to an output of -the multiplexer included within the second sample and hold circuit which generates data cross-over samples.
  • a multiplexer is coupled to outputs from the pair of tracking and hold circuits included in the third sample and hold circuit.
  • the multiplexer of the third sample and hold circuit has an output coupled to the filter.
  • An inverter is coupled between an output of one of the tracking and hold circuits and an input of the multiplexer to invert tracked and held data cross-over samples when the tracking and hold circuit coupled thereto is clocked by a negative transition of the data output signal.
  • the tracking and hold circuits and multiplexers comprising the first, second, and third sample and hold circuits are matched through substantially identical integrated circuit fabrication to inherently null out systematic phase errors within the circuit.
  • the frequency lock detector comprises a fourth sample and hold circuit comprised of a pair of tracking and hold circuits complementarily clocked by the data output signal each having their inputs coupled to the lowpass filter.
  • a multiplexer has its inputs coupled to outputs of the pair of tracking and hold circuits of the fourth sample and hold circuit.
  • a second lowpass filter has its input coupled to an ou ⁇ ut of the multiplexer of the fourth sample and hold circuit.
  • a summing node is coupled to the second lowpass filter for differencing with the phase error signal.
  • a limiter has its input coupled to the summing node to generate a frequency error signal.
  • the circuit further comprises a lock detect gate for breaking connection between the limiter and the lowpass filter when absolute value of the phase error signal is below a predetermined threshold, so that the VCO is controlled only by the phase error below the threshold and by the frequency error above the threshold.
  • the invention is also a method of recovering a clock signal from an NRZ data bit stream comprising the steps of detecting edge transitions of the NRZ data bit stream.
  • a quadrature sample signal is generated corresponding to the NRZ data bit stream.
  • the quadrature signal is selectively passed to a phase detector output.
  • the quadrature sample signal is passed to the phase detector output if the NRZ data makes a low to high transition.
  • a negative of the quadrature sample signal is passed to the phase detector output if the NRZ data signal makes a high to low transition. Otherwise if the NRZ data signal makes no transition, a previous phase error value is held in the phase detector output.
  • a variably controlled oscillator (VCO) is then controlled according to the phase detector output.
  • a recaptured clock signal is generated by the controlled VCO.
  • the method further comprising the step of generating from the output of the phase error detector a frequency error signal.
  • the frequency error signal is selectively combined with output of the phase detector to control frequency of the VCO to thereby frequency lock to the NRZ data bit stream.
  • the method further comprising the step of generating a monotonically increasing phase error signal extending across a bit interval centered on zero phase error in the form of a sawtooth wave form for controlling the VCO.
  • the method further comprises the step of generating from the output of the phase error detector a frequency error signal.
  • the frequency error signal is selectively combined with output of the phase detector to control frequency of the VCO to thereby frequency lock to the NRZ data bit stream.
  • the invention can be characterized as a circuit for recapturing a clock signal from an NRZ data bit stream comprising a clocked sample and hold circuit for sampling and holding an in-phase sample signal of the NRZ data bit stream.
  • a clocked sample and hold circuit is also provided for sampling and holding a quadrature sample signal of the NRZ data bit stream.
  • a phase detector circuit selectively passes the quadrature sample signal to a phase detector output. The quadrature sample signal is passed to the phase detector output if the NRZ data makes a low to high transition. The negative of the quadrature sample signal is passed to the phase detector output if the
  • NRZ data makes a high to low transition.
  • the previously passed quadrature sample signal is held at the phase detector output if the NRZ data makes no transition.
  • a variable controlled oscillator circuit receives the phase detector output and responsively generates an in-phase clock signal.
  • the clocked sample and hold circuit for sampling and holding an in-phase sample signal of the NRZ data bit stream and the clocked sample and hold circuit for sampling and holding a quadrature sample signal of the
  • NRZ data bit stream are complementarily clocked by the in-phase clock signal.
  • Figure 1 is a block diagram of a prior art fiber optic receiver.
  • Figures 2a-2d are eye diagrams of a random data and recovered clock signal at various nodes within the circuit of Figure 1.
  • Figure 3 is a functional block diagram of a circuit incorporating the invention.
  • Figure 4 is a functional block diagram of the circuit of Figure 3 which has been modified to include a frequency detector and frequency lock loop.
  • Figure 5 is a is a functional block diagram of a prior art circuit showing an early- late gate clock recovery circuit design.
  • Figure 6 is a is a functional block diagram of a prior art circuit which is a modification of the circuit of Figure 5 in which the time delay is equal to the bit interval.
  • Figure 7 is a modification of an early-late clock recovery circuit which has been modified according to the invention.
  • Figure 8 is a simplified timing diagram showing a typical NRZ data stream and its corresponding matched filter output as used in the circuit of Figure 7.
  • Figures 9a-c are simplified timing diagrams which illustrate the relationship of quadrature sample signals to early, on-time and late in-phase sample and which illustrates that the gradient or slope of the on-time sample is equal to the value of the crossover sample.
  • FIG 10 is a functional block diagram of a digital transition tracking loop (DTTL) of the invention.
  • DTTL digital transition tracking loop
  • Figure 11 is a timing diagram showing the form of the phase error signal produced in Figure 10.
  • Figures 12a and 12b are simplified timing diagrams showing the phase error signal and its derivative as a function of time for a slow and fast clock respectively.
  • Figure 13 is a functional block diagram of a circuit for extracting a frequency error signal from a sawtooth phase error signal.
  • Figures 14a and 14b are simplified timing diagrams which show frequency error polarity extraction from a sawtooth phase error signal for a slow and fast clock respectively.
  • Figure 15 is a graph illustrating dead-zone control for the generation of a frequency error signal.
  • Figure 16 is a functional block diagram of a circuit for implementing the dead- zone control shown in Figure 15.
  • the invention is a clock recovery or extraction circuit.
  • the circuit is used to extract a clock signal from random, nonreturn-to-zero (NRZ) data.
  • the general field of application for the ⁇ ircuit is in digital communications and is expected to be particularly useful for high speed, broad band modulation formats, although its use is not restricted to such schemes.
  • a functional block diagram of the illustrated embodiment of the invention is shown and described in connection with Figure 3.
  • a second embodiment in a modified circuit is shown in the block diagram of Figure 4.
  • the clock recovery circuit of Figures 3 and 4 is designed such that the residual phase-errors between the data signal and the extracted clock signal are minimized. This is accomplished in two ways. First, a negative feedback loop is used to phase lock the extracted the clock to the time varying deviations of the data signal. Second, any residual offsets in the steady state phase error are nulled out by using identical and matching, circuit building blocks in the phase detector.
  • the clock extraction circuit can also detect frequency differences between the data and the clock signal. This ability to detect frequency differences is used for acquiring an additional phase lock.
  • the frequency error signal is used to drive the clock signal to the correct frequency so that an initial phase lock can occur at start up.
  • the circuit is capable of performing at very high speeds and is inherently self- adjusting. As stated, it can detect frequency errors to assist in acquisition of initial phase lock.
  • the phase detector function is monotonic over the bit interval thereby improving phase tracking and frequency acquisition. Ripple induced phase jitter is significantly reduced by resampling the phase error only after a data transition. The phase error is independent of the transition density thereby eliminating data pattern dependent jitter.
  • the sensitivity of the circuit is improved by using sample and hold circuits before the decision circuit.
  • circuit will be of utility in fiber optic data links, disk drive read/write electronics, local area networks, and wireless communications. These areas are expected to seek continued growth in the future due to a demand for low cost, low power interconnection of computer networks, mobile data links, and multimedia services, such as video-on-demand, home shopping, home banking, interactive educational programs, and the like.
  • FIG. 5 is a functional block diagram of a conventional early- late gate clock recovery circuit using rectifiers in each arm of the circuit. The circuit is well known and discussions, of its performance can be found, for example, in Gardner, "Phase Lock Techniques, "New York, Wiley, 2d Ed. 1979, at page 235.
  • the speed of the circuit of Figure 6 is limited by the need to perform the integrate and dump functions. However, by replacing the correlators of the circuit of Figure 6 with a matched filter, a circuit is derived which can be used at high speeds.
  • the functional block diagram of this circuit is shown in Figure 7.
  • the difficulty with a practical limitation of a circuit describe in Figure 7 is that some type of assistance is required in frequency acquisition for the initial phase lock. Without this type of assistance, the VCO center frequency of the circuit of Figure 7 must be stable within 0.1 percent over all processing and temperature variations, which is difficult to meet in practical applications.
  • timing information for NRZ data is only present when the data make a transition. Therefore, the output of the phase detector between bit intervals can be ignored when no data transition occurs in the bit interval. The phase detector may thereby be shut off by a gating mechanism in absence of data transitions.
  • the modified early-late gate of the invention adds an additional sampling stage to transfer the phase-detector output to the loop filter only when a data transition has occurred.
  • a similar approach was used in an application for clock phase estimates at very low speeds by Paine et al, Transition Tracking Bit Synchronization System, " U.S. Patent 3,626,298 (1971).
  • Figure 8 shows a typical rectangular NRZ data pattern on line 34 before and on line 36 after being passed through a matched filter.
  • the matched filter produces a linear transition shown on line 36 that extends over one bit interval.
  • Positive going data transitions produce a linear positive slope and negative going data transitions produce a linear negative slope over one bit interval. Since we are only interested in what happens during data transitions, consider first the positive data pulse 38 shown on line 36 in Figure 8. Recall that the ultimate goal is to position the phase of the recovered clock so that the sample is taken at the point where the filtered data signal achieves a maximum signal-to-noise ratio.
  • the gradient or slope of the on-time samples can be found by shifting the sampling phase half a bit period.
  • Positive data pulse 38 is characterized by a data crossover sampling point 40 and an optimal sampling point 42.
  • This special case is illustrated in Figures 9a-c.
  • the phase-shifted sample point or the quadrature sample which is shifted forward by one quarter of a clock interval (half the bit interval), is shown in the case of an early clock in Figure 9a, indicating that the quadrature sample is negative; shown for an on-time clock in Figure 9b indicating the quadrature sample is zero; and in the case of a late clock, in Figure 9c, indicating that the quadrature is positive, which is also equal to the derivative or gradient of the curve at the in-phase sample point.
  • the opposite condition can be considered when the data pulse is negative such as shown for pulse 44 in Figure 8, in which case the plurality of the quadrature samples are reversed from those shown in Figures 9a-9c.
  • the sign or polarity reversal is removed by multiplying the quadrature samples by the retimed data, if the data is treated as taking the values (1, -1), which is typically the case for NRZ data.
  • the quadrature samples values are transferred to the loop filter only when the data transition occurs, we can obtain the following simple list of rules for obtaining the desired phase error signal. a. If the data makes a low to high transition, pass the quadrature sample to the phase detector output. b. If the data makes a high to low transition, pass the negative of the quadrature sample to the phase detector output. c. If the data makes no transition, hold the previous phase error value.
  • the circuits shown in functional block diagram of Figure 10 implements these rules. It can be seen from this circuit that the quadrature samples follow the data transitions as a function of the phase-offset.
  • the input data is coupled to a matched filter 46 which outputs the data transitions edges.
  • the output of matched filter 46 is coupled to two complementarily clocked sample and hold circuits 48 and 50.
  • Sample and hold circuit 48 is in the in-phase sample arm and is clocked on the positive data transitions. Its output is coupled to a limiter 52. Limiter 52 cleans up the noise from sample and hold circuit 48 and outputs unambiguous high and low logic signals (1, -1).
  • the output of limiter 52 is the data output, is also fed back both to a multiplier 54 for polarity correction of the phase error signal as discussed above, and is used as the clock input of sample and hold circuit 56.
  • the quadrature samples are taken by sample and hold 50 on the negative transition of the clock or what would be considered the cross ⁇ over point for an on-time signal.
  • the cross-over samples thus contains the phase error information as was illustrated in Figures 9a-c.
  • the phase error information is valid, however, only when a data transition occurs and the polarity of the quadrature signal switches with the data value. Therefore, the quadrature sample is processed by means of sample and hold circuit 56, which has its input coupled to the output of sample and hold circuit 50.
  • Sample and hold circuit 56 is devised such that it samples on both positive and negative data transitions. As a result, all quadrature samples that are taken by sample and hold circuit 50 will be ignored until a data transition occurs at which time the output will be passed to the phase lock loop after sign reversal if necessary by multiplication by the data signal.
  • the output of sample and hold circuit 56 is coupled to the second input of multiplier 54.
  • the output of multiplier 54 is the phase error signal.
  • the phase error signal is filtered by a low pass filter 58 whose dc output is the error correction signal which is coupled to VCO 60.
  • the phase of the clock generated by VCO 60 is varied in a direction so that the phase error signal is nulled, i.e. phased locked to the true data clock signal.
  • VCO 60 generates the clock for sample and hold circuits 48 and 50 and drives clock output limiter 62 to produce the recovered clock signal.
  • the plurality of the signal changes abruptly at a cycle-slip boundary, giving rise to a sawtooth-type phase detector characteristic illustrated in the timing graph of Figure 11.
  • the boundary at which cycle slipping might occur is defined as the cycle-slip boundary. It is the place in the data stream, where for example, synchronization might be suddenly lost and then reacquired, but only at an integer number of bit interval later with the possible loss of the interlying bits.
  • Figure 11 shows the phase error signal at the output of multiplier 54 as a function of the time offsets between the data transitions and the clock signal from VCO 60.
  • the sawtooth curve 64 clearly illustrates that the phase detector is monotonic over the entire bit interval [-T/2, T/2] so that the phase error signal follows the shape of the data transition until it abruptly changes sign at the time when the offsets equal to one-half the bit interval.
  • a bit interleaved data transition tracking loop is preferably used as shown in Figure 3.
  • substantially similar elements described in connection with Figure 10 are referenced with the same reference numerals in Figure 3.
  • the data again is input into a matched filter 46 and coupled to complementarily clocked track and hold circuits 64, 66, 68 and 70.
  • a sample and hold can only change its value when the clock changes. Therefore you get a staircase type of output from a sample and hold circuit.
  • a single circuit implementation of a sample and hold is difficult to make.
  • a track and hold circuit has two phases: 1) in the first phase it tracks the signal with unity gain; and 2) in the second phase it holds the value that was present at the clock edge.
  • a track and hold circuit can be built in a straight forward way.
  • a sample-and-hold function can be reproduced with two track-and-hold circuits and a multiplexor. In this way, one track- and-hold circuit is tracking while the other track-and-hold circuit is holding and vica versa.
  • two separate track and hold circuits are used to interleave data and to speed up the circuit operation.
  • the only circuit that has to run at full speed are the multiplexers, which are typically the fastest circuits.
  • the circuit speed is limited then only by one of the fastest types of circuits employed.
  • track and hold circuits 64-70 are then coupled through corresponding multiplexers 72 and 74.
  • Multiplexer 72 corresponds to track and hold circuit 64 and 66
  • multiplexer 74 corresponds to track and hold circuit 68 and 70.
  • the output of multiplexer 74 is then coupled through a buffer circuit 76 to track and hold circuits 78 and 80.
  • the purpose of buffer circuit 76 is to insert a circuit delay to generally match the delay inserted by limiter 52 to the data output signal, so that the quadrature sample input to track and hold circuits 78 and 80 is more or less still time correlated to the data output signal used as the complementary clock signal for track and hold circuits 78 and 80.
  • track and hold circuit 80 is inverted by inverter 82 to correct polarity reversal since track and hold circuit 80 is clocked on the negative data transition.
  • the output of inverter 82 is coupled to a multiplexer 84 whose other input is coupled to the output of track and hold circuit 78.
  • the output of multiplexer 84 is the phase error signal, coupled as before in the case of Figure 10 to lowpass filter 58 and thence to VCO 61.
  • the output of VCO 61 is the clock signal to track and hold circuits 64-70 and is provided through limiter 62 as the recovered clock signal.
  • the output data is coupled from multiplexer 72 through limiter 52 and provided as an output at node 86.
  • the output data is used as the clock signal for multiplexer 84.
  • Multiplexers 72 and 74 are clocked by VCO 61.
  • the I and Q outputs from VCO 61 are 90 degrees out of phase with each other and are separated in time by a half a bit interval, T/2, since VCO 61 generates a clock signal at half the bit rate. I is in phase with the true data clock rate when the phase error is nulled, while Q leads I by an interval of T/2.
  • VCO 61 operates at a center frequency which is half the data bit rate.
  • the output of VCO 61 is a quadrature output for sampling the data at the data crossover points.
  • the multiplexed track and hold circuits 64-70 perform the function of the sample and hold circuits of Figure 10 on a bit interleaved basis to sample and hold the data on both positive and negative going clock transitions in the same manner as described in connection with the circuit of Figure 10.
  • Track and hold circuits 78 and 80 with multiplexer 84 and inverter 82 perform in an bit interleaved manner substantially the same function as sample and hold circuit 56, and multiplier 54 of the circuit of Figure 10.
  • Track and hold circuits 64 and 66, together with multiplexer 72, comprises a repeatable structure.
  • the resampling circuit, track and hold circuits 78 and 80 with multiplexer 84 has a reverse of polarity for a negative data transition, in for example a fully differential circuit, this is easily realized by switching the polarity of the differential signals.
  • the layout of the resampling circuit is identical to the front end of the circuit except for a crossover in the wiring. This allows the three sets of track and hold circuits and multiplexer to be fabricated as substantially matched circuit groupings in an integrated circuit.
  • the phase detector of Figure 3 operates at very high speeds and since the phase detector and decision portion use identically fabricated integrated circuitry, the sampling phase is inherently self-adjusting.
  • the circuit samples at half the data bit time width, T/2 seconds, offset from the data crossovers. Although this sample point may not be optimal for sinusoidal pulse shapes, for any other pulse shape it achieves a maximum signal-to-noise ratio at the center of the bit interval which is the optimum sampling point.
  • the data decision is made after the multiplexor in limiter 52. Because the signal is sampled and held, it is not necessary to have a latch or regenerator to make sure that the bit won't change in the middle of a bit interval. If desired latching can be added after the limiter to further square-up the data-output.
  • the circuits of Figures 3 and 10 have a phase detector output which is monotonic over the bit interval. The output is independent of the data transition-density to a first order thereby substantially reducing data pattern dependent jitter in the recovered clock. Resampling the phase error signal at data transitions significantly reduces ripple in the error signal, and thereby reduces phase jitter in the recovered clock signal.
  • the circuit can also be viewed as a modification of a gradient based maximum a posteriori (MAP) estimator.
  • MAP gradient based maximum a posteriori
  • the receiver finds Pr(t
  • a MAP receiver and an likelihood receiver are the same thing.
  • the MAP is more desirable.
  • the illustrated circuit produces a MAP estimate under nominal operating conditions. It can be shown that an optimal MAP receiver is one that find Pr(t
  • the illustrated circuit produces a phase error that is the gradient of the optimal correlation function. Therefore, if used in a feedback system to drive the gradient to zero, the resulting clock signal will occur at a time that is the optimal MAP estimate of data arrival time.
  • the data transition tracking loop provides a MAP clock-phase estimate in steady state operation, provided there is no systematic offset.
  • the systematic offsets are typically the dominant factors responsible for performance degradation of high speed circuits
  • the primary advantage of these sampled data transition tracking loop is its symmetry, which makes the circuit insensitive to systematic errors.
  • the residual phase-error in recovered clock signal will be a result only of random mismatches in the circuits, which can be reduced or controlled to a high degree of accuracy in an integrated fabrication process.
  • the circuit of Figure 3 might not be able to lock in to a data signal that has a frequency which differs substantially from the VCO frequency.
  • the natural acquisition of the loop can only pull in frequency errors on the same order of magnitude as the closed looped bandwidth.
  • the pull-in range of the circuit can be quite narrow.
  • the VCO frequency is 5 GHz.
  • the maximum frequency deviation which can be tolerated is of the order of 10 megahertz or 0.2 percent of the VCO frequency. It may be impractical to design a VCO with a center frequency stable to within 0.2 percent in every application.
  • a simple frequency detector can be devised once it is realized that the phase error signal is a sawtooth type function of the error.
  • Figure 12a illustrates the relationship between the error function and its time derivative for a clock which is too slow, while Figure 12b illustrates the same relationship when the clock is too fast.
  • the derivative of the error function is in the proper direction or has the proper polarity most of the time. Therefore, to derive a frequency error signal that gives only the sign of the frequency error, we need to only process the derivative by a circuit such as shown in Figure 13.
  • the error signal, e is coupled to the input of a differentiator 88, whose output is coupled to a limiter 90.
  • the frequency error which is the output of limiter 90, is added to the error function itself by summing circuit 92 to obtain a signal which is the sum of phase error plus frequency error. This will transform the signal shown in Figures 12a and 12b, respectively, to the outputs shown in Figures 14a and 14b.
  • the data transition tracking loop is ideal for implementing sawtooth frequency detection because the error signal is resampled and contains virtually no ripple. Therefore, only a broad band low pass filter is needed to smooth glitches before producing the desired sawtooth function.
  • the data transition tracking loop can thus recognize frequency errors of at least 10 to 20 percent to provide a significant range over which VCO center frequencies can vary and still be pulled in by the circuit.
  • Figure 4 illustrates the basic structure of a practical data transition tracking loop with frequency detection.
  • Figure 4 is a modification of the circuit of Figure 3 in which a frequency detector has been included in the feedback path. Considerations of closed loop stability and jitter peaking dictate the gain and transfer function of the frequency filter 58a in the frequency error path.
  • a lock detector can be used to force the frequency to zero after the phase acquisition is complete.
  • One technique is the use of a dead zone near the point of zero phase error. This is described in connection with Figure 15.
  • the frequency error is enabled only when the phase error exceeds a given threshold.
  • Figure 15 is a graph showing plus and minus time error margins within the data bit width in which there is a dead zone 94 such that the frequency error is not enabled until the thresholds 96 or 98 are exceeded or reaches a point on curve 100 out of dead zone 94.
  • the circuit of Figure 16 is a functional block diagram by which the control technique of Figure 15 is implemented.
  • the Phase error to coupled to a full wave rectifier 118 to provide the absolute value of the phase error.
  • a predetermined threshold value is subtracted from the absolute value of the phase error in a su ⁇ ming node 120 with the difference being converted to a (0, 1) logic level by limiter 122.
  • the output of limiter 122 is coupled to multiplier 124 where it multiplies the frequency error signal. Because limiter 122 generates either only a 0 or a 1, multiplier acts as a dead zone switch, so that the circuit of Figure 16 is symbolically denoted in Figure 4 as switch 102. With this technique, the operation of frequency acquisition can be separated from phase tracking.
  • the average phase error signal will nominally equal zero and will have no effect on the loop.
  • the loop will not be locked. Therefore the phase error will continually slip cycles and rotate through [-pi, pi] in terms of clock phase or [-T/2, T/2] in terms of bit period times.
  • the phase will look like a linearly increasing quantity for a constant frequency error. Therefore the output of the phase detector with a constant frequency error will look like Figure 11 as a function of time.
  • This signal has an average value of zero. It will get lowpass filtered by the circuit elements and the resulting output signal is nominally zero (zero dc value) with some ac ripple due to imperfect suppression of the high frequency contents from the loop filter.
  • the phase error signal takes over and the frequency error feedback path is broken, indicated symbolically in the circuit of Figure 4 by switch 102.
  • What has been added to the circuitry of Figure 4 is the addition of a broadband lowpass filter 104 coupled to the output of multiplexer 84.
  • the output of filter 104 has a frequency one-quarter the frequency of the bit rate.
  • the output of filter 104 is then provided as inputs to track and hold circuits 106 and 108.
  • the output of circuits 106 and 108 are coupled to the inputs of multiplexer 110, whose output again is coupled to a lowpass filter 112.
  • the output of filter 112 is differenced at summing node 114 with the phase error.
  • the output from node 114 is then coupled through limiter 116 and provided to the switched locked detect gate 102.
  • the output of filter 104 which represents the phase error, is also coupled to the input of a phase filter 58b.
  • the output of frequency filter 58a and phase filter 58b are then summed at su ⁇ miing node 118 and provided to the input of VCO 61.
  • the remaining elements of the circuit of Figure 3 are identical or substantially similar to similarly numbered elements shown and described in connection with Figure 3.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Un circuit d'extraction de signal d'horloge fonctionnant selon le principe de la porte à anticipation-retard est appliqué à des liaisons de télécommunications série rapides au moyen de données de non retour à zéro (NRZ). Le circuit n'a pas de déphasage systématique et n'a donc pas besoin de circuits ou mécanismes externes de rephasage. Le circuit est utilisé dans des récepteurs intégrés haute vitesse pour des applications telles que les fibres optiques, les logiques lecture/écriture de mémoire à disques, les systèmes de communications mobiles et la transmission haute vitesse de données par paires torsadées dans des systèmes multimédia. On obtient et on conserve des échantillons en quadrature (50) qui prennent un profil de la transition de données NRZ en fonction du déphasage. Le passage du signal de données dans le limiteur (52) génère un signal d'erreur de phase en dents de scie. La dérivée de la fonction d'erreur extraite produit un signal d'erreur de fréquence permettant la détection de fréquence et l'assistance à l'acquisition de fréquence du circuit à boucle à verrouillage de phase (54, 58 et 60) générant le signal d'horloge extrait (Synchro) à partir d'un oscillateur à commande variable (60).
PCT/US1994/008223 1994-07-21 1994-07-21 Circuit d'extraction de signal d'horloge autoreglable, haute vitesse, a detection de frequence WO1996003800A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US08/392,958 US5757857A (en) 1994-07-21 1994-07-21 High speed self-adjusting clock recovery circuit with frequency detection
PCT/US1994/008223 WO1996003800A1 (fr) 1994-07-21 1994-07-21 Circuit d'extraction de signal d'horloge autoreglable, haute vitesse, a detection de frequence
CA002171734A CA2171734A1 (fr) 1994-07-21 1994-07-21 Circuit d'extraction de signal d'horloge autoreglable, haute vitesse, a detection de frequence

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1994/008223 WO1996003800A1 (fr) 1994-07-21 1994-07-21 Circuit d'extraction de signal d'horloge autoreglable, haute vitesse, a detection de frequence

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Cited By (2)

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Publication number Priority date Publication date Assignee Title
US9104654B2 (en) 2013-09-09 2015-08-11 Sandisk Technologies Inc. Method and device for efficient trace analysis
CN112241384A (zh) * 2019-07-19 2021-01-19 上海复旦微电子集团股份有限公司 一种通用的高速串行差分信号分路电路及方法

Citations (5)

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Publication number Priority date Publication date Assignee Title
US3626298A (en) * 1969-07-08 1971-12-07 Nasa Transition tracking bit synchronization system
US4570125A (en) * 1982-07-02 1986-02-11 U.S. Philips Corporation FSK Demodulator with concurrent carrier and clock synchronization
US4604755A (en) * 1984-06-01 1986-08-05 International Business Machines Corp. Feed forward dual channel automatic level control for dual tone multi-frequency receivers
US4879728A (en) * 1989-01-31 1989-11-07 American Telephone And Telegraph Company, At&T Bell Laboratories DPSK carrier acquisition and tracking arrangement
US4949357A (en) * 1988-03-15 1990-08-14 Alcatel N.V. Synchronizing circuit for offset quaternary phase shift keying

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3626298A (en) * 1969-07-08 1971-12-07 Nasa Transition tracking bit synchronization system
US4570125A (en) * 1982-07-02 1986-02-11 U.S. Philips Corporation FSK Demodulator with concurrent carrier and clock synchronization
US4604755A (en) * 1984-06-01 1986-08-05 International Business Machines Corp. Feed forward dual channel automatic level control for dual tone multi-frequency receivers
US4949357A (en) * 1988-03-15 1990-08-14 Alcatel N.V. Synchronizing circuit for offset quaternary phase shift keying
US4879728A (en) * 1989-01-31 1989-11-07 American Telephone And Telegraph Company, At&T Bell Laboratories DPSK carrier acquisition and tracking arrangement

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9104654B2 (en) 2013-09-09 2015-08-11 Sandisk Technologies Inc. Method and device for efficient trace analysis
CN112241384A (zh) * 2019-07-19 2021-01-19 上海复旦微电子集团股份有限公司 一种通用的高速串行差分信号分路电路及方法
CN112241384B (zh) * 2019-07-19 2022-07-01 上海复旦微电子集团股份有限公司 一种通用的高速串行差分信号分路电路及方法

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