WO1995034913A1 - Transistors a effet de champ a grille amorcee et circuits comprenant ces transistors - Google Patents

Transistors a effet de champ a grille amorcee et circuits comprenant ces transistors Download PDF

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Publication number
WO1995034913A1
WO1995034913A1 PCT/US1995/007452 US9507452W WO9534913A1 WO 1995034913 A1 WO1995034913 A1 WO 1995034913A1 US 9507452 W US9507452 W US 9507452W WO 9534913 A1 WO9534913 A1 WO 9534913A1
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Prior art keywords
gate
region
source
drain
transistor
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PCT/US1995/007452
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English (en)
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Robert J. Bayruns
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Anadigics, Inc.
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Publication of WO1995034913A1 publication Critical patent/WO1995034913A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6874—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor in a symmetrical configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1058—Channel region of field-effect devices of field-effect transistors with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/435—Resistive materials for field effect devices, e.g. resistive gate for MOSFET or MESFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/24—Frequency-independent attenuators
    • H03H11/245—Frequency-independent attenuators using field-effect transistor

Definitions

  • This invention relates to semiconductor field effect transistors and in particular, to semiconductor field effect transistors utilized as electronically variable resistance sources or attenuators.
  • FETs Field Effect Transistors
  • RF radio frequency
  • MF microwave frequency
  • to be attenuated input AC signal is applied, for example, to a FET's source terminal, and the attenuated signal is provided at its drain terminal.
  • the input signal is thus attenuated by the resistance between the source and drain of the FET; such resistance is controlled by the voltage applied to the FET's gate terminal. Consequently., the FET functions as a voltage controlled variable resistor.
  • GaAs MESFET GaAs MEtal Semiconductor Field Effect Transistor
  • a conventional n- channel GaAs MESFET has an n-doped GaAs epitaxial layer 105 deposited on a semi-insulating GaAs substrate 100, source and drain regions 120 and 125 formed in GaAs layer 105, and contacts 121 and 124 formed on the source and drain regions, respectively.
  • a gate metallization 115 is deposited on GaAs layer 105 and between the source and drain contacts, which forms with the GaAs layer a Schottky diode having a depletion region 110.
  • a region 102 between the depletion region and the semi-insulating substrate is defined as the channel region.
  • the source-to-drain resistance is defined as the resistance between the source and drain contacts. Because the source-to-drain resistance of the above- described MESFET is mainly determined by the channel resistance which is controlled a voltage applied to the gate, we use the term "channel resistance" hereinafter to refer the source-to-drain resistance. Varying the gate voltage changes the depletion region and the channel region thickness and thus the channel resistance. The channel or depletion region thickness is referred hereinafter as their dimensions along the direction perpendicular to the substrate.
  • Fig. lb illustrates a typical output characteristic of a GaAs MESFET. In this figure, I DS and V DS represent drain-to-source current and voltage, respectively.
  • Each of the curves represents I DS versus Vus at a particular gate voltage, V G .
  • I DS approximately linearly increases with V ⁇ s; the slope of the curve corresponds to the drain- to-source resistance at a specific gate voltage and such resistance varies with the gate voltage.
  • V G ⁇ gate voltage
  • I DS begins to saturate, i.e., it changes little when V DS increases more.
  • Fig. 1C shows an equivalent circuit diagram for a FET used as a variable resistance source.
  • the FET is shown as a variable resistor R DS ; signal to be attenuated, V,, is connected to one end of the variable resistor; a load, V LOAD , is connected to the other end of the resistor.
  • FET's channel resistance depends only on the gate voltage. In practice, however, it depends not only on the gate voltage but also on the input signal. As a result, the output signal is undesirably distorted, i.e., the waveform of the output signal is distorted as compared with the waveform of the input signal. This distortion, called FET's nonlinearity or nonlinear distortion, limits FETs' applications in many RF and microwave control circuits which require high linearity. This has been the subjects in many technical discussions and publications, e.g., in Caverly, "Distortion in broad- band gallium arsenide MESFET control and switch circuits," IEEE Trans. Microwave Theory Tech.. 39(4), pp.
  • AGC FET Automatic Gain Control Field Effect Transistors
  • DBS FET Direct Broadcast Satellite Field Effect Transistors
  • V DS1 the drain-to-source voltage at which the current begins to saturate, is not a constant and it changes with the gate voltage.
  • V DS ⁇ is approximately expressed in the following equation (See, e .g. , Sze , "Physics of semiconductor devices," A Wiley-Interscience Publication, p.318, 1981) where V P is the transistor's pinch-off voltage and it depends only on the doping concentration and the geometric dimensions of the transistor, V G is the gate voltage, and V BI is the internal bias voltage between the gate and the channel and it is normally fixed once the transistor is fabricated. Therefore, V DS ⁇ linearly depends on the gate voltage.
  • the channel resistance should depend only on the voltage applied to the gate terminal, in practice the channel resistance also depends on the input AC signal. Input AC signal modulates the depletion region thickness and as a result, effects the channel resistance.
  • V s is applied to the source of a
  • e is the permittivity of the channel semiconductor material
  • V is the input signal
  • V G is the gate voltage
  • q is the elementary charge
  • N d is the doping concentration in the channel, assuming the doping concentration is uniform.
  • R j . is the channel resistance
  • L is the channel length
  • ⁇ n is the electron mobility in the channel (assuming the channel is doped n-type)
  • h is the n- GaAs layer thickness
  • W is the channel width.
  • channel resistance Rj. depends on the depletion region thickness, d, which in turn depends on the input signal V
  • the channel resistance R ⁇ also depends the input signal, which results in nonlinear distortion. Note that this kind of distortion occurs even if the FET operates on the liner portion of its current output characteristic.
  • U.S. patent No. 4,574,249 to Williams is directed to transimpedance amplifier circuits; it also described a transimpedance amplifier using a four terminal FET as a variable feedback resistor.
  • the FET is either a conventional MOSFET type or a p-n-p silicon JFET illustrated in Fig. ID.
  • the Williams 's FET includes, besides source and drain terminals, a gate terminal at the source end (Gl) and another gate terminal at the drain end (G2) , and it operates by applying a differential DC voltage, i.e., Vj,.+ ⁇ V and ⁇ V, to Gl and G2, respectively.
  • a differential DC voltage i.e., Vj,.+ ⁇ V and ⁇ V
  • variable resistance circuit 200 uses an externally bootstrapped FET.
  • the variable resistance circuit 200 consists of a FET 205 having its gate and source connected by a capacitor C its gate and drain connected by another capacitor C 2 , and its gate coupled to a control voltage V G through a resistor.
  • variable resistance circuits operates as follows: Because the slow-varying gate control voltage V G is coupled to FET's gate 210 though resistor R, gate 210 is effectively floated with respect to AC signal. Accordingly, capacitors C j and C 2 impose additional AC signal at the gate, and the voltage at the gate partially follows the input signal. As seen from equations (1) and (2), this reduces the dependency of depletion region thickness on the input signal and reduces the distortion. In addition, as seen from equation (1) , because V DS1 depends on V G and V G partially follows the input signal v «> V DSI also partially follows the input signal. As a result, distortion due to the current saturation is also reduced.
  • this bootstrapped circuit has several limitations.
  • the circuit is only capable to feedback a portion of the input signal to the gate; the ratio of this portion to the input signal is approximately C 2 /(C,+C 2 ).
  • C, and C 2 normally have equal values, which results feedback of 50% of the input signal to the gate. It would be desirable to feedback more than 50% of the input signal to the gate to further reduce the distortion.
  • this circuit does not use active circuit component to suppress distortion, it still requires external components like resistors and capacitors, which makes it difficult and costly for monolithically integration.
  • a field effect transistor comprises channel, source and drain regions formed in a semiconductor layer deposited on a substrate having a substantially higher resistivity than the channel region, and a resistive gate region disposed over the channel region.
  • the resistive gate region provides, with respect to the channel region, distributed resistance and capacitance.
  • the distributed resistance and capacitance provide distributed feedback of input AC signal to the gate region.
  • a FET comprises a n-type GaAs layer deposited on a semi-insulating GaAs substrate. N-type source and drain regions are formed in the n-GaAs layer, defining therebetween a channel region. A resistive gate region made of resistive material such as cermet is deposited on the channel region. The resistive gate region provides, with respect to the channel region, distributed resistance and capacitance.
  • JFET junction field effect transistor
  • JFET comprises a semiconductor resistive gate region having a first conductivity type deposited on a substrate, a semiconductor layer having a second conductivity type deposited on the resistive gate region. Source and drain regions are formed in the semiconductor layer, forming therebetween a channel region.
  • the resistive gate region of the JFET provides, with respect to the channel region, distributed resistance and capacitance.
  • a preferred embodiment comprises a p-type implanted GaAs layer, as a resistive gate region, formed on a semi-insulating GaAs substrate and an implanted n-type GaAs layer formed on the resistive gate region. Source and drain regions are formed in the n-type GaAs layer, forming therebetween a channel region.
  • BGFETs Bootstrapped Gate Field Effect Transistors
  • the BGFETs are characterized by their resistive gate regions which provide, with respect to the channel regions, distributed resistance and capacitance, and by which the channel is formed on a layer that has a substantial higher resistivity than the channel region; preferably, such layer is a semi-insulating layer or an insulator such as semi-insulating GaAs layer or silicon oxide.
  • the channel region resistance substantially depends only on a control voltage applied at the gate.
  • a BGFET may be configured as a three or four terminal devices.
  • a three terminal BGFET is formed by providing a single electrical contact to the resistive gate region.
  • a four terminal BGFET is formed by providing a first gate contact to the portion of the gate region that is close to the source region, and a second gate contact to the portion of the gate region that is close to the drain region.
  • the four terminal BGFET offers additional flexibility over a conventional FET in biasing the BGFET in that a bias voltage may be applied between the first and second gate contacts of the four terminal BGFET.
  • a second aspect of the present invention relates to an electronically variable resistance circuit comprising an externally bootstrapped BGFET.
  • the electronically variable resistance circuit has input, output and control terminals, and it comprises a BGFET of the present invention coupled to an external bootstrap circuit.
  • the external bootstrap circuit comprises a first capacitive means coupled between the gate and source terminals of the BGFET, a second capacitive means coupled between the gate and drain terminals of the BGFET, and a resistive means coupled between the gate terminal of the BGFET and the control terminal of the circuit.
  • the input terminal of the circuit is coupled to the source terminal of the BGFET; the output terminal of the circuit is coupled to the drain terminal of the BGFET.
  • variable resistance circuit provides low distortion, high linearity attenuation, to input AC signal. Moreover, this circuit can be used to provide attenuation for AC signal having frequencies lower than the BGFET's own low frequency limit.
  • the variable resistance circuit comprises a first capacitive means coupled between the source and first gate terminals, a second capacitive means coupled between the drain and the second gate terminal; a first resistive means is coupled between the control terminal and the first gate terminal; a second resistive means is coupled between the control terminal and the second gate terminal.
  • the input and output terminals of the variable resistance circuit are connected to the source and drain terminals of the BGFET, respectively.
  • Another aspect of the present invention relates to attenuation circuit that utilizes the
  • the attenuation circuits include ⁇ r-type attenuation circuits and T-type attenuation circuits.
  • Figs. 1A-C illustrate a cross-sectional view, output characteristics, and an equivalent circuit diagram of a prior art GaAs MESFET, respectively;
  • Fig. ID shows a FET in William;
  • Fig. 2 shows a variable resistance circuit consisting of a FET and a bootstrapping circuit externally coupled to the FET;
  • Fig. 3A depicts a cross-sectional view of a first preferred embodiment of Bootstrapped-Gate Field Effect Transistors ("BGFETs”) of the present invention
  • Fig. 3B illustrates a three-dimensional view of the first preferred embodiment
  • Fig. 3C depicts, for the sole purposes of demonstrating the operating principle of the BGFETs, an equivalent circuit of a BGFET;
  • Fig. 3D illustrates a device symbol for a three-terminal BGFET
  • Figs. 3E and F depict a cross-sectional view of a four-terminal BGFET and its device symbol, respectively.
  • Fig. 4A depicts a three-dimensional view of a second preferred embodiment of BGFETs of the present invention
  • Figs. 4B and 4C illustrate the cross- sectional views of three-terminals and four terminal embodiments of the BGFET of Fig. 4A;
  • Fig. 5A illustrates a three-dimensional view of a third referred embodiment of the BGFETs
  • Figs. 5B and 5C illustrate the cross- sectional views of three-terminals and four terminal embodiments of the BGFET of Fig. 5A;
  • Fig. 6A illustrates a three-dimensional view of a second embodiment of the BGFETs
  • FIG. 6B shows a top view of an alternative embodiment of the BGFET of Fig. 6A;
  • Fig. 6C depicts the cross-section of an alternative embodiment to the BGFET of Fig. 6A;
  • Fig. 6D shows a topical view of a multi- fingered BGFET;
  • Fig. 7A illustrates a three-dimensional view of another embodiment of BGFETs of present invention.
  • Figs. 7B and 7C show the test results for the BGFET of Fig. 7A;
  • Fig. 7D shows the circuit diagram for a circuit utilized in testing the BGFETs
  • Fig. 8 shows the test results of the circuit of Fig. 7D; Figs. 9A-C illustrate more test results of
  • Figs. 10A-B illustrate two electronically variable resistance circuits of the present invention
  • Figs. 11A-B illustrate attenuation circuits utilizing BGFETs of the present invention.
  • a bootstrapped gate field effect transistor comprises source, drain and channel regions disposed on a semiconductor substrate layer, and a resistive gate region disposed over the channel region.
  • the substrate layer has a substantially higher resistivity than the channel region.
  • the resistive gate region provides, with respect to the channel region, distributed resistance and capacitance.
  • the distributed resistance and capacitance in response to AC signal applied at the source or drain, provides distributed AC feedback voltage to the resistive gate region. The distributed AC feedback substantially cancels the effect of the input AC signal on the channel resistance, thus suppressing nonlinear distortion.
  • a first preferred embodiment comprises a semi-insulating GaAs substrate 300 and an implanted n-type GaAs layer 301 formed on the substrate.
  • a resistive gate region 320 is deposited on n-type GaAs layer 301.
  • Source and drain regions 310 and 315, respectively, are formed in the expitaxial layer by ion-implantation of n-type dopant. Since the resistive gate region forms with epitaxial layer 301 a Schottky diode, a depletion region 335 is established between gate region 320 and layer 301.
  • a channel region 305 is thus defined as the region between the source and drain regions, and between the depletion region and the substrate.
  • Source contact 325, drain contact 330, and gate contact 321 are formed on the source, drain, and gate regions, respectively, for providing electrical contacts to the source, drain, and gate regions. Those contacts consist of metallization layers.
  • the resistive gate region consists of resistive materials. Cermet such as Cr-SiO x can be used to form the resistive gate region; the resistivity of Cr-SiO x can be adjusted by changing the ratio of Cr to SiO x in the cermet material.
  • resistive gate region 320 provides, with respect to channel region 305, distributed resistance and capacitance. Such distributed resistance and capacitance is illustratively shown as the resistor and capacitor network 330. The contacts to the source, drain, and gate regions are not shown in this drawing for simplicity.
  • the substrate 300 is a semi-insulating GaAs substrate.
  • the substrate refers to the semiconductor layer that is directly beneath the channel region.
  • the BGFETs of the first embodiment prefer substrates that have a substantially higher resistivity than that of the channel region, thus ensuring that the channel thickness is not affected by the variation of the voltage between the channel region and the substrate. More specifically, the channel thickness is only affected by a single junction, the junction between the gate and channel regions. Because of the substantially higher resistivity of the substrate, the effect to the channel thickness by the junction between the channel region and the substrate is negligible. As will be apparent from the following discussion, the effect of the input signal on the depletion thickness is reduced by the distributed feedback to the gate region which is provided by the distributed resistance and capacitance. In the preferred embodiment, because of the distributed feedback as well as the substantially higher resistivity substrate, the effect of the input signal on the channel region is suppressed and nonlinear distortion is substantially reduced.
  • the transistor of Fig. 3A is considered as being equivalent to four externally bootstrapped FETs serially connected along their source-to-drain path.
  • the four FETs are designated as T1-T4.
  • Each gate of the FETs is bootstrapped by two capacitors, C, and is connected to a slow varying gate voltage V G via a resistor, R.
  • the capacitors, C are intended to simulate the distributed capacitance between the resistive gate and channel.
  • the resistors, R are attributed to the distributed resistance of the resistive gate region.
  • the depletion thickness non-uniformity caused by input signal V d is most severe at the drain end of the channel and least sever at the source end of the channel.
  • the AC feedback voltage at the gate of FET T4 which is the nearest to the drain is the greatest, and the feedback voltage at the gate of FET Tl which is the farthest to the drain, is the smallest; the feedback voltage monotonically decreases from the gate of T4 to the gate of Tl.
  • Another significant advantage of the BGFETs over conventional FETs is that the distortion due to the FET's current saturation in its output characteristics is also greatly reduced or eliminated. Because of the distributed feedback, the channel thickness becomes uniform and is independent of the input AC signal at the source or drain of the BGFET. The depletion region pinch-off due to the input AC signal is thus eliminated. As discussed in the BACKGROUND OF THE INVENTION, the depletion region pinch-off which causes current saturation is one of the major mechanisms responsible for distortion. The elimination of the depletion region pinch-off at the drain eliminates the distortion due to the current saturation.
  • the input RF signal applied to the source or drain of the BGFET does not see the current saturation, even though the BGFET still displays such characteristics in its DC characteristics.
  • the input AC signal frequency needs to be greater than a cutoff frequency of the distributed resistance and capacitance.
  • FIG. 3D A device symbol for this type three-terminal BGFET is illustrated in Fig. 3D.
  • the gate terminal is illustratively shown in Fig. 3D as closer to the source terminal than the drain terminal, it is not intended to indicate that the gate terminal is located closer to the source; rather, it merely represents that this transistor utilizes a single gate contact to the resistive gate region.
  • electrical contact to the gate is accomplished by forming a first gate contact 322, designated as G s , at the source end of the transistor, and a second gate contact 323, designated as G D , at the drain end of the transistor. Because the resistive gate region comprises resistive material, a voltage may be applied to G s between G D . Thus, in this configuration, the transistor becomes a four terminal device. G s and G D can also be externally connected with a conductor so that the transistor be used as a three-terminal device.
  • Fig. 3F illustrates a device symbol of this device. It includes a source terminal, S, a drain terminal, D, a gate terminal at the source end, G s , and a gate terminal at the drain end, G D .
  • the resistor between G s and G D represent the distributed gate resistance along the channel.
  • the distributed resistance and capacitance of the transistor imposes a distributed feedback voltage on the gate region. Such feedback voltage is not uniform across the gate; rather, it is distributed along the channel. Consequently, the feedback at G s and G D is different.
  • this BGFET can be integrated into GaAs monolithic microwave circuits.
  • the semiconductor layer containing the channel region is formed on a semi-insulating substrate.
  • the semiconductor layer may also be formed on a semi- insulating or non-doped expitaxial buffer layer which is in turn formed on a substrate.
  • This device functions to suppress the distortion the same way as the preferred embodiment.
  • the above described preferred embodiment employs GaAs material and technology. Similar transistor can also be made utilizing silicon material and technology.
  • a silicon epitaxial layer is first deposited on a silicon dioxide substrate or a sapphire substrate, followed by the formation of the drain, source, and resistive gate regions. Contacts to those regions are subsequently made.
  • the resistive gate region is made of either cermet, lightly doped polysilicon, or other kinds of resistive material.
  • other semiconductor materials may also be utilized for making transistors that operate on the basis of the same principle to suppress distortion as the above- described preferred embodiment.
  • Fig. 4A illustrates a three dimensional view of a second preferred embodiment.
  • This BGFET comprises a Si0 2 substrate 400, an epitaxial p-type silicon layer 401 formed on the substrate, an silicon gate oxide layer 410 formed on layer 401, and a resistive gate region 415 deposited on the silicon oxide layer.
  • N-type source region 420 and drain region 425 are formed in p-type Si layer 401.
  • a channel region 405 is established under the gate Si0 2 layer and between the source and drain regions.
  • the resistive gate region provides, with respect to the channel region distributed resistance and capacitance which is illustratively shown as a resistor and capacitor network 430.
  • the resistance in the distributed resistance and capacitance is mainly due to the resistance of the resistive gate material; the capacitance is mainly due to the capacitance between the resistive gate and the channel.
  • This device has a similar structure as that of a conventional silicon MOSFET; however, the gate of this BGFET comprises resistive material instead of metal conductor as in the case of MOSFET, and the substrate is an insulating Si0 2 substrate.
  • a three terminal BGFET is established.
  • a four terminal BGFET can be constructed by, in addition to the contacts to the source and drain regions, forming a first gate contact 416, designated as G s , at the source end and a second gate contact 417, designated as G D , at the drain end.
  • FIG. 5A A cross-sectional view of a third preferred embodiment is illustrated in Fig. 5A.
  • This BGFET is a type of a GaAs Junction Field Effect Transistor (JFET) wherein a pn junction is utilized to modulate the channel resistance.
  • the BGFET comprises a semi- insulating GaAs substrate 500 and an n-type GaAs layer 506 deposited on the substrate. Two heavily doped n- regions, 525 and 530, are formed in layer 506 as source and drain regions, respectively.
  • a lightly doped p-type GaAs resistive gate region 510 is formed in layer 506 and between the source and drain regions.
  • the p-type GaAs resistive gate region and n-type GaAs layer 506 adjacent the gate region constitute a pn junction having a depletion region designated as 515, defining a channel region 505 between the depletion region and the substrate.
  • the distributed resistance and capacitance is illustratively shown as the resistor and capacitor network 520.
  • the distributed resistance is mainly due to the resistance of the gate region and the distributed capacitance due to the capacitance of the pn junction.
  • One way to fabricated this GaAs BGFET is to first form an n-type GaAs epitaxial layer on a semi- insulating GaAs substrate, followed by photo- lithography and an implantation of n-type dopants defining the source and drain regions, and another photo-lithography and an implantation of p-type dopants to form the resistive gate.
  • the doping concentration of the source or drain region is equal or higher than 10 18 /cm 3 for making low resistance contact.
  • the resistivity of the resistive gate region can be adjusted by changing the dose of the implanted dopant in the resistive gate region.
  • the device with similar structure can also be made with silicon material.
  • a Si0 2 or sapphire substrate may be utilized as the substrate; the source and drain and channel regions are made of n-type silicon material, and the resistive gate is made of p-type silicon material.
  • Figs. 5B and 5C depict the three-terminal and four-terminal BGFETs based on this embodiment.
  • Fig. 6A illustrates the cross-sectional view of a BGFET comprising a semi-insulating GaAs substrate 700 and an implanted GaAs resistive gate region 705 having a p-typed conductivity type formed on the substrate.
  • a GaAs channel region 720 having n-type conductivity type is formed on the gate region.
  • Source and drain regions 710 and 715 having n-type conductivity type are formed.
  • Source and drain contacts 735 and 740 are formed on the source and drain regions, respectively, for providing electrical contact to those regions.
  • This BGFET has a structure of a side-gate field effect transistor since the gate contacts are formed outside the region that is between the source and drain.
  • this BGFET is formed by first depositing an n-type epitaxial layer on a semi- insulating GaAs substrate, followed by a first p-type ion-implantation to form the gate region. A first n- type implantation is then performed to define the channel. Next, a second n-type ion-implantation and a second p-type ion-implantation are performed to define the source and drain regions, and the gate contact regions, respectively.
  • gate region 705 provides, with respect to channel 720 distributed resistance and capacitance.
  • the distributed resistance depends on the dosage of the first p-type implantation as well as the thickness of the gate region; the distributed capacitance depends on both the first p- type implantation that forms the gate region, and the first n-type implantation that forms the channel.
  • p-channel BGFETs of this kind can be similarly made by replacing the n-type regions with p- type regions, and p-type regions with n-type regions.
  • the substrate is not in direct contact with the channel region. Consequently, once the BGFET is fabricated, the channel resistance substantially depends only on the voltage between the resistive gate region and the channel region.
  • Fig. 6B illustrates a top view of an alternative BGFET to the one described above.
  • the elements in this figure are similarly designated as those of Fig. 6A for simplicity.
  • gate contact regions 725 and 730 are not formed alongside source and drain regions 710 and 740, respectively.
  • this embodiment has reduced interaction between gate contact regions and the source or drain region because they are further apart.
  • Fig. 6C depicts another alternative BGFET to the ones described above.
  • electrical contact to the gate region is made by forming contacts 745 and 750 disposed over a portion of resistive gate region 705 that is exposed by a mesa.
  • Fig. 6D illustrates a layout design of a multi-fingered BGFET which has a structure similar to that of Fig. 6A.
  • the BGFET includes a mesa 755 formed on a semi-insulating substrate 773 and interposed source regions 760 and drain regions 765 formed on the mesa.
  • Source and drain contacts 770 and 775 are deposited on an exposed surface of the semi-insulating substrate, each having contacting fingers 772 or 774 extending over an dielectric layer deposited over the mesa.
  • Via holes 771 and 776 are formed in the dielectric layer, allowing contacting fingers 772 and 774 to make electrical contact to the source and drain regions, respectively.
  • a gate contact 780 is similarly formed contacting a gate region through via holes 781.
  • a portion 785 of the gate contact is a thin film resistor which is used to further float the gate region with respect to AC voltage.
  • Fig. 7A depicts a second preferred embodiment.
  • This BGFET comprises a semi-insulating GaAs substrate 800, an implanted p-type gate region 805, an implanted n-type channel 820, and implanted n- type source and drain regions 810 and 815.
  • Source and drain contacts 835 and 840 are formed on the source and drain regions, respectively.
  • This transistor is formed on a mesa and it is electrically isolated from other devices on the substrate.
  • Gate contacts 845 are formed partially on top of the mesa and partially on the substrate, and it covers at least a portion of the side of the mesa. As a result, gate contacts 845 directly contact gate region 805 at the side of the mesa.
  • This BGFET further includes two n-type regions 812 and 815 formed beneath and in contact with the portion of the gate contact that is on the mesa. Those regions are utilized to control the electrical potential of the gate region in case the gate contacts fail to make a good electrical contact to the gate region through the side of the mesa.
  • a p-type ion-implantation is first performed on a surface of a semi-insulating GaAs wafer to form gate region 805.
  • the surface doping concentration of the p-type ion-implantation is about 6xl0 12 /cm 2 .
  • a mesa is defined by a first photo ⁇ lithography and etching. The etching may be conducted by wet chemical etching, reactive ion etching, or other etching techniques.
  • the channel region is then defined by a second photo-lithography, followed by a first n-type ion-implantation that forms channel region 820.
  • the distance between the source and drain, i.e. the channel length, L, for this transistor, is typically about 5 ⁇ m; the channel width, W, is approximately lOO ⁇ m.
  • the surface doping concentration for the first n-type ion-implantation is approximately 6.5xl0 12 /cm 2 . Note that the p-type implantation for forming the gate region is conducted on the entire surface of the wafer, whereas the first n-type ion-implantation for the channel region is only performed at the channel region.
  • Source region 810, drain region 815, and n- type regions 812 and 814 are then photo- lithographically defined, followed by a second n-type ion-implantation.
  • the surface doping concentration for the second n-type ion-implantation is higher than the first n-type ion-implantation.
  • Gate contacts 845 and source and drain contacts 835 and 840 are subsequently defined by the steps of photo-lithography, deposition of a metallization alloy layer, liftoff, and thermal annealing.
  • source and drain may be first formed with a first metallization alloy such as AuGe; gate contact are then formed with a second metallization alloys such as AuBe or AuZn which makes low resistance contact to p-type GaAs gate region through the side of the mesa.
  • first metallization alloy such as AuGe
  • second metallization alloys such as AuBe or AuZn which makes low resistance contact to p-type GaAs gate region through the side of the mesa.
  • the topology of the BGFET can also be arranged similarly as the one illustrated in Fig. 6B.
  • the gate contacts are formed on the "front" and “back” of the BGFET as in Fig. 6B instead alongside the source and drain regions.
  • Multi-fingered layout design as illustrated in Fig. ID may also be utilized.
  • Fig. 7B presents the test result of this BGFET's attenuation versus its gate voltage.
  • the transistor is used as a series attenuator, i.e. the test signal is applied to the source of the transistor and the output signal is measured at the drain of the transistor.
  • the attenuation is measured at a test signal frequency of 800 MHz.
  • the y axis represents the attenuation (in db) to the input signal, and the x-axis corresponds to the voltage applied to the gate.
  • the pinch off voltage is defined as the gate voltage at which the attenuation of the transistor is 20 dB, the pinch off voltage of this BGFET is approximately -3V.
  • the pinch off voltage of the BGFET can be adjusted by adjusting the dosage and energy of the implantation that form the n-type channel region and the p-type gate region.
  • Fig. 7C illustrates the test result of third order intercept point IIP3 (dbm) versus the attenuation (db) obtained from a two-tone test for the BGFET.
  • third order intercept points for a conventional Medium Power FET (“MPFET”) an implanted conventional Automatic Gain Control FET (“AGC FET”), and an Anadigics 1 Distribute Broadcast Satellite FET (“DBS FET”), which are comparable to the resulted disclosed in aforementioned reference Caverly et al .
  • the tests is performed by applying test signal at the source of a FET and measuring the attenuated signal at the drain of the FET. As discussed in the BACKGROUND OF THE
  • a transistor's nonlinearity mainly consists of two types of nonlinearity, harmonic frequency nonlinearity and Inter-Modulation ("IM”) frequency nonlinearity.
  • Harmonic frequency nonlinearity refers to unwanted signal having frequencies that are integer times of input signal frequencies; in typical applications, this type of nonlinearity can be easily eliminated with filter circuits.
  • IM nonlinearity refers to unwanted signal having frequencies such as, assuming input signal having frequencies f t and f 2 , (fj+f 2 ) , (fj- f 2 ) , (2fj+f 2 ) , (2fj-f 2 ) , etc.
  • IM nonlinearity is much more difficult to remove than harmonic frequency nonlinearity.
  • a two-tone test is a test devised to measure the nonlinearity of electronic devices and circuits such as FETs.
  • two input signals having equal power P ⁇ but at different frequencies, fj and f 2 , respectively are first combined and then applied to the source terminal of the FET under test.
  • the output signal power at frequency f, (or f 2 ) , P- ⁇ , i s "then measured.
  • P ta and measuring output signal power P o ⁇ a first curve of p out,f i (dbm) v. Pj,, (dbm) is thus obtained.
  • the output power is measured at one of the inter- modulation frequencies ("IM") , f I; such as (f t -f 2 ) (assuming f, > f 2 ) , (fj+f 2 ) , (2fj-f 2 ) , (2f]+f 2 ) , or etc.
  • IM inter- modulation frequencies
  • the first and second curves are then plotted in one drawing and the curves are extrapolated towards the higher P;, region of the drawing where the two curves intercept each other.
  • the output power of signals of the inter-modulation frequency at the point of interception is called intercept point.
  • a FET's intercept point for inter-modulation frequencies, f,, at (f ⁇ +f 2 ) and (f ⁇ f 2 ) is called second order intercept point (IIP2) ; the intercept point for inter-modulation frequencies, f lr at (2f j -f 2 ) , (2f 2 -f j ) , (2f t +f 2 ) , and (2f 2 +fj) are defined as third order intercept point (IIP3) .
  • Intercept point is a useful measure of a device's IM nonlinearity; it is normally independent of the input signal power. Higher value of the intercept point (in dbm) represents less non-linearity in a transistor. In particular, third order intercept point is independent of the test circuit configuration and thus, is a reliable measure of a device's total nonlinearity.
  • the vertical axis refers to the third order intercept point, IIP3, in dbm and the horizontal axis the attenuation in db.
  • the third order intercept point of the BGFET is about average 10 dbm better than that of the other types of FETs, which clearly demonstrates that the BGFET has a much better linearity than the others FETs.
  • Fig. 7D illustrates a test circuit configuration for measuring BGFET circuit performance. More specifically, B2 is a BGFET for providing attenuation and Bl is a shunt BGFET that is identical as B2.
  • a first signal source V provides first AC signal at a frequency of 250 MHz and a second signal source V 2 provides second AC signal having a frequency of 255 MHz.
  • Vj and V 2 constitute a two-tone signal generator 900, providing AC input signal to source S2 of transistor B2.
  • the AC input signal comprises frequency components of both 250 MHz and 255 MHz with equal power.
  • V c is a variable DC voltage source for controlling the attenuation.
  • Four capacitors, C x , C 2 , C 3 , and C 4 are utilized in the circuit for isolating DC voltage sources from the AC voltage source. The operation of the test circuit can be described as follows:
  • the input signal from two-tone signal generator 900 is provided to drain O x of transistor B ⁇ through capacitor C and to source S 2 of transistor B 2 through capacitor C 2 .
  • Drain D t of transistor B t is biased at +3V by a DC voltage source V ⁇ .
  • Variable DC voltage source V c is connected to the gate of B lf and to source S 2 of transistor B 2 through a 50K resistor. V c can be varied from 0V to +3V.
  • V c When V c is set at 0V, transistor Bl is turned off, i .e . transistor Bl exhibits a maximum resistance between its source and drain, whereas transistor B2 is turned on, i .e . transistor B2 displays a minimal resistance or attenuation between its source and drain.
  • the circuit allows maximum amount of input signal to reach the output terminal through transistor B2. At this moment, the circuit exhibits the least attenuation to the input signal.
  • transistor Bl When V c is controlled at +3V, transistor Bl is fully turned on to AC signal and transistor B2 is turned off. Most of the input signal from the two- tone generator is thus shunted to the ground through transistor Bl. At this moment the circuit allows the least amount of the input signal to reach the output terminal because transistor B2 provides a maximum attenuation.
  • V c from 0 to +3V changes the attenuation of the circuit from a minimum to a maximum. Consequently, by varying V c from 0V to +3V and measuring the intercept point, a plot of intercept point versus the attenuation for the transistor under test is thus obtained.
  • Fig. 8 shows the BGFETs' circuit performance tested using the circuit of Fig. 7D.
  • the y axis and x axis correspond to second and third order intercept points in dbm and attenuation, respectively.
  • the BGFETs used has the same structure as the one of Fig. 7A except that it has a pinchoff voltage of approximately -30V. As shown, the circuit's second order intercept point averages more that 60 dbm and the third order intercept point more that 30 dbm.
  • Figs. 9A-C represent test results for some BGFETs that have similar structures as that of Fig. 8A but with a different pinchoff voltage.
  • the surface doping concentration is about 6.5xl0 12 /cm 2 for the n-channel regions, and about 4xl0 12 /cm 2 for the p-type gate region.
  • Fig. 9A depicts the attenuation v. the gate voltage for one of those transistors.
  • a pinchoff voltage of -18V is obtained from this Figure.
  • Fig. 9B depicts the third order intercept point ("IIP3") v. attenuation for those BGFETs which have the same gate width of 10 ⁇ m but different gate length of 5, 10, 20, 30 and 40 ⁇ m.
  • IIP3 third order intercept point
  • Each curve in the drawing is labeled by two number written as LxW where L is the channel length and w is the channel width for the particular BGFET which the curve corresponds to.
  • Fig. 9C exhibits the test results of the second order intercept point ("IIP2") v. attenuation.
  • the BGFETs* IIP2 improves with decreased gate width.
  • Measurement of IIP2 v. L reveals that the IIP2 is not dependent on L.
  • At the attenuation of 10 dB all of the BGFETs exhibit IIP2 greater than 30 dBm.
  • a preferred electronically variable resistance circuit 920 of the present invention comprises a four terminal bootstrapped gate field effect transistor (BGFET) 900 having its source terminal, S, coupled to a first gate terminal, G s , through a capacitor C s , and its drain terminal, D, coupled to a second gate terminal, G D , through a second capacitor, C D .
  • BGFET bootstrapped gate field effect transistor
  • the circuit further includes an input signal terminal 925 connected to the source terminal of the BGFET, an output signal terminal 930 connected to the drain terminal of the BGFET, and a resistance control terminal 935 connected to gate terminal G s via a resistor R s , and to gate terminal G D via a resistor R D .
  • both the BGFET's internal distributed resistance and capacitance, and the external resistor R s and R D and capacitors C s and C D provide feedback to the FET's gate terminal.
  • ⁇ is the time constant of the equivalent feedback circuit and it is expressed as ⁇ — R E C E where R E and C E are the equivalent resistance and capacitance of the overall bootstrapped circuit. Because T of this circuit is more than that of the BGFET alone, the cutoff frequency for the circuit is thus less than that of a BGFET itself. Consequently, this circuit is able to operate to provide low distortion attenuation at lower frequencies lower than what would be operated at for a BGFET alone.
  • the input signal when input AC signal having a frequency higher than f c is applied to the input terminal and the output signal is provided at the output terminal, the input signal is attenuated by the resistance between the input and output of terminals of this circuit. Due to the feedback provided by the internal distributed resistance and capacitance of the BGFET and the external bootstrap resistors and capacitors, the attenuation is substantially linear and independent of the input signal.
  • this variable resistance circuit can be designed to operate in audio frequency range for providing electronically controlled, highly linear attenuation.
  • Fig. 11B illustrates a similar attenuation circuit utilizing a three terminal BGFET. More specifically, the circuit comprises a three-terminal BGFET 900, a resistor R Q connected between a control terminal 935 and the gate terminal of the BGFET, a first capacitor C s connected between the gate and source terminals of the BGFET, and a second capacitor C D connected between the gate and drain terminals of the BGFET.
  • the source and drain terminals of the BGFET are connected to an input terminal 925 and an output terminal 930, respectively.
  • the BGFETs of the present invention can be utilized in circuits where electronically variable resistance is required.
  • Those circuits includes various kinds of RF or microwave attenuation circuits, continuous time filter, etc.
  • Fig. 12A illustrates a preferred embodiment of a ⁇ -type attenuation network using three three- terminals BGFETs, Tl, T2 and T3 of the present invention.
  • the attenuation of the circuit is controlled by controlling the voltage applied to the gate terminals of the BGFETs.
  • BGFETs Tl and T3 may be replaced with conventional FETs; or BGFETs Tl, T2, and/or T3 may be replaced with the electronically variable resistance circuit of Figs. 11A or 11B.
  • BGFETs Tl, T2, and T3 may be replaced with the four-terminal BGFET of the present invention.
  • Fig. 12B depicts a preferred embodiment of a ⁇ -type attenuation circuit using the three-terminal BGFETs of the present invention.
  • BGFET T2 may be replaced with a conventional FET; or BGFETs Tl, T2, and T3 may be replaced with the electronically variable resistance circuit of Figs. 11A or 11B.
  • BGFETs Tl, T2, and T3 may be replaced with the four-terminal BGFET of the present invention.

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Abstract

Cette invention se rapporte à un nouveau type de transistors à effet de champ, à savoir des transistors à effet de champ à grille amorcée ('BGFET') servant à assurer une résistance variable. Un tel transistor BGFET comprend une région source (420), une région drain (425), une région grille (430) et une région canal (405). La région grille est constituée par un matériau résistif et elle fournit, par rapport à la région canal, une résistance et une capacitance réparties, qui imposent une rétroaction répartie à la région grille du signal C.A. appliqué aux régions source ou drain. Ces transistors BGFET peuvent en outre être amorcés de l'extérieur, pour réduire la limite de fréquence inférieure à laquelle ils peuvent fonctionner correctement.
PCT/US1995/007452 1994-06-16 1995-06-12 Transistors a effet de champ a grille amorcee et circuits comprenant ces transistors WO1995034913A1 (fr)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2394610A (en) * 2002-09-30 2004-04-28 Agilent Technologies Inc A low-distortion RF FET switch
EP1427017A1 (fr) * 2001-09-14 2004-06-09 Matsushita Electric Industrial Co., Ltd. Dispositif semi-conducteur
WO2017105554A1 (fr) * 2015-12-14 2017-06-22 Circuit Seed, Llc Transistor à effet de champ à courant de sursaturation et dispositif mos à transimpédance
US20180219519A1 (en) 2015-07-30 2018-08-02 Circuit Seed, Llc Low noise trans-impedance amplifiers based on complementary current field-effect transistor devices
US10211781B2 (en) 2015-07-29 2019-02-19 Circuit Seed, Llc Complementary current field-effect transistor devices and amplifiers
US10491177B2 (en) 2015-07-30 2019-11-26 Circuit Seed, Llc Multi-stage and feed forward compensated complementary current field effect transistor amplifiers
US10514716B2 (en) 2015-07-30 2019-12-24 Circuit Seed, Llc Reference generator and current source transistor based on complementary current field-effect transistor devices

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Publication number Priority date Publication date Assignee Title
US5208477A (en) * 1990-12-31 1993-05-04 The United States Of America As Represented By The Secretary Of The Navy Resistive gate magnetic field sensor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208477A (en) * 1990-12-31 1993-05-04 The United States Of America As Represented By The Secretary Of The Navy Resistive gate magnetic field sensor

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1427017A1 (fr) * 2001-09-14 2004-06-09 Matsushita Electric Industrial Co., Ltd. Dispositif semi-conducteur
EP1427017A4 (fr) * 2001-09-14 2006-10-18 Matsushita Electric Ind Co Ltd Dispositif semi-conducteur
GB2394610A (en) * 2002-09-30 2004-04-28 Agilent Technologies Inc A low-distortion RF FET switch
GB2394610B (en) * 2002-09-30 2006-07-26 Agilent Technologies Inc Switching system
US10211781B2 (en) 2015-07-29 2019-02-19 Circuit Seed, Llc Complementary current field-effect transistor devices and amplifiers
US10554174B2 (en) 2015-07-29 2020-02-04 Circuit Seed Llc Complementary current field-effect transistor devices and amplifiers
US10840854B2 (en) 2015-07-29 2020-11-17 Circuit Seed, Llc Complementary current field-effect transistor devices and amplifiers
US11456703B2 (en) 2015-07-29 2022-09-27 Circuit Seed, Llc Complementary current field-effect transistor devices and amplifiers
US20180219519A1 (en) 2015-07-30 2018-08-02 Circuit Seed, Llc Low noise trans-impedance amplifiers based on complementary current field-effect transistor devices
US10476457B2 (en) 2015-07-30 2019-11-12 Circuit Seed, Llc Low noise trans-impedance amplifiers based on complementary current field-effect transistor devices
US10491177B2 (en) 2015-07-30 2019-11-26 Circuit Seed, Llc Multi-stage and feed forward compensated complementary current field effect transistor amplifiers
US10514716B2 (en) 2015-07-30 2019-12-24 Circuit Seed, Llc Reference generator and current source transistor based on complementary current field-effect transistor devices
WO2017105554A1 (fr) * 2015-12-14 2017-06-22 Circuit Seed, Llc Transistor à effet de champ à courant de sursaturation et dispositif mos à transimpédance
US10283506B2 (en) 2015-12-14 2019-05-07 Circuit Seed, Llc Super-saturation current field effect transistor and trans-impedance MOS device
US10446547B2 (en) 2015-12-14 2019-10-15 Circuit Seed, Llc Super-saturation current field effect transistor and trans-impedance MOS device

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