WO1995024729B1 - Modular architecture for high bandwidth computers - Google Patents

Modular architecture for high bandwidth computers

Info

Publication number
WO1995024729B1
WO1995024729B1 PCT/US1995/002676 US9502676W WO9524729B1 WO 1995024729 B1 WO1995024729 B1 WO 1995024729B1 US 9502676 W US9502676 W US 9502676W WO 9524729 B1 WO9524729 B1 WO 9524729B1
Authority
WO
WIPO (PCT)
Prior art keywords
printed circuit
circuit board
memory
microprocessor
computer system
Prior art date
Application number
PCT/US1995/002676
Other languages
French (fr)
Other versions
WO1995024729A2 (en
WO1995024729A3 (en
Filing date
Publication date
Application filed filed Critical
Priority to AU20937/95A priority Critical patent/AU2093795A/en
Priority to JP52354395A priority patent/JP3727062B2/en
Priority to KR1019960705038A priority patent/KR970701885A/en
Priority to DE69521685T priority patent/DE69521685T2/en
Priority to EP95913540A priority patent/EP0749600B1/en
Publication of WO1995024729A2 publication Critical patent/WO1995024729A2/en
Publication of WO1995024729A3 publication Critical patent/WO1995024729A3/en
Publication of WO1995024729B1 publication Critical patent/WO1995024729B1/en

Links

Abstract

A computeur system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by replacing the printed circuit board incorporating the processor. Similarly, a type of peripheral bus used can be changed simply by replacing the printed circuit board containing the peripheral controller. High-density connectors connect the circuit boards. Some embodiments of the invention use a single backplane. Other embodiments place peripheral slots on a second, passive backplane.

Claims

AMENDED CLAIMS[received by the International Bureau on 17 May 1996 (17.05.96); original claims 1, 14 and 51 amended; new claims 58-90 added; remaining claims unchanged (14 pages)]
1. A computer system, comprising: a local bus; a memory bus; a first backplane including: a first printed circuit board including a microprocessor and being connected to the local bus and to the memory bus, a second printed circuit board including a memory and being connected to the memory bus, and a third printed circuit board having a peripheral controller and being connected to the local bus; and a second backplane having a peripheral connector and being connected to the first backplane; wherein the first backplane allows replacement of at least one of the first, second, and third printed circuit boards with a corresponding fourth printed circuit board having a similar general function as the at least one printed circuit board being replaced; and the first backplane is adapted to accommodate different local bus sizes corresponding to the microprocessor.
2. The system of claim 1, further including: a peripheral bus connected to the peripheral controller; a plurality of peripheral slots located on the second backplane and connected to the peripheral bus; and a high-density connector for connecting the peripheral bus between the first and second backplanes.
3. The system of claim 1, further including: a plurality of peripheral slots located on the second backplane and connected to the local bus; and a high-density connector for connecting the local bus between the first and second backplanes.
4. The system of claim 1, further including: a plurality of peripheral slots, located on the second backplane, and connected to a fourth bus; and a high-density connector for connecting the fourth bus between the first and second backplanes.
- 65 -
5. The system of claim 1, wherein the first backplane is connected to the second backplane through a high-density connector.
6. The system of claim 1, wherein the first printed circuit board is connected to the first backplane through a high-density connector.
7. The system of claim 1, wherein the second printed circuit board is connected to the first backplane through a high-density connector.
8. The system of claim 1, wherein the third printed circuit board is connected to the first backplane through a high-density connector.
9. The system of claim 1, wherein the microprocessor is a 32-bit microprocessor.
10. The system of claim 1, wherein the microprocessor is a 64-bit microprocessor.
11. The system of claim 1, wherein the microprocessor is an 128-bit microprocessor.
12. The system of claim 1, wherein the system contains at least one additional printed circuit board containing a memory.
13. The system of claim 1, wherein the system contains at least one additional printed circuit board containing a peripheral controller.
14. A computer system, comprising: a local bus for transmitting and receiving a plurality of first signals; a memory bus for transmitting and receiving a plurality of second signals; a peripheral bus for transmitting and receiving a plurality of third signals; a first printed circuit board including a microprocessor and associated circuitry and being connected to the local bus and the memory bus, the first printed circuit board transmitting and receiving the plurality of the first and second signals;
- 66 - a second printed circuit board including a memory and being connected to the memory bus, the second printed circuit board transmitting and receiving the plurality of the second signals; and a third printed circuit board having a peripheral controller and being connected to the local bus and the peripheral bus, the third printed circuit board transmitting and receiving the plurality of the first and third signals; wherein at least one of the first, second and third printed circuit boards is replaceable with a corresponding fourth printed circuit board having a similar general function as the at least one printed circuit board being replaced; and the computer system is adapted to accommodate different local bus sizes corresponding to the microprocessor.
15. The system of claim 14, wherein the first printed circuit board is connected to the local bus and the memory bus through at least one high-density connector.
16. The system of claim 14, wherein the second printed circuit board is connected to the memory bus through at least one high-density connector.
17. The system of clam 14, wherein the third printed circuit board is connected to the local bus and the peripheral bus through at least one high-density connector.
18. The system of claim 14, wherein the microprocessor is a 32-bit microprocessor.
19. The system of claim 14, wherein the microprocessor is a 64-bit microprocessor.
20. The system of claim 14, wherein the microprocessor is an 128-bit microprocessor.
21. The system of claim 14, wherein the system contains at least one additional printed circuit board containing a memory.
22. The system of claim 14, wherein the system contains at least one additional printed circuit board containing a peripheral controller.
- 67 -
23. A computer system, comprising: a local bus; a memory bus; a first printed circuit board containing a microprocessor thereon and connected to the local bus and the memory bus through a first high-density connector system; a second printed circuit board containing a memory thereon and connected to the memory bus through a second high- density connector system; and a third printed circuit board having a peripheral controller thereon and connected to the local bus through a third high-density connector system; and at least one of the first, second, and third high- density connector systems having a density of at least 100 contacts per linear inch.
24. The computer system of claim 23, wherein at least one of the high-density connector systems has at least 128 contacts per linear inch.
25. The computer system of claim 23, wherein at least one of the high-density connector systems has at least 300 contacts per linear inch.
26. The computer system of claim 23, wherein the first, second, and third printed circuit boards are on a first backplane, wherein a second backplane contains a peripheral connector, and wherein the first and second backplanes are connected with a high-density connector system having a density of at least 100 contacts per linear inch.
27. The computer system of claim 26, wherein the peripheral connector is connected to the local bus, and the high-density connector system connecting the backplanes connects the local bus across the backplanes.
28. The computer system of claim 26, wherein the peripheral connector is connected to the peripheral bus and the high-density connector system connecting the backplanes connects the peripheral bus across the backplanes.
- 68 -
29. A method of configuring a computer system having a local bus and a memory bus, comprising the steps of: connecting a first printed circuit board containing a first type of microprocessor thereon to the local bus and to the memory bus through a first high-density connector system; connecting a second printed circuit board containing a memory thereon to the memory bus through a second high- density connector system; and connecting a third printed circuit board having a peripheral controller thereon to the local bus through a third high-density connector system; and at least one of the first, second, and third high- density connector systems having a density of at least 100 contacts per linear inch.
30. The method of claim 29, further comprising the steps of: removing the first printed circuit board from the system; and connecting, in place of the first printed circuit board, a fourth printed circuit board containing a second type of microprocessor, to the local bus and to the memory bus through the first high-density connector system.
31. The method of claim 30, wherein the processors on the first and fourth printed circuit boards have different architectures.
32. The method of claim 30, wherein the processors on the first and fourth printed circuit boards have different bus widths.
33. The method of claim 30, wherein the processors on the first and fourth printed circuit boards have at least one of different timing characteristics, different power consumption characteristics, and different operating speeds.
34. The method of claim 29, further comprising the steps of: removing the second printed circuit board from the local bus; and
- 69 - connecting a fourth printed circuit board containing a different type of memory from the memory on the second printed circuit board to the memory bus through the second high-density connector system.
35. The method of claim 29, further comprising the steps of: removing the third printed circuit board from the peripheral bus; and connecting a fourth printed circuit board containing a different type of peripheral controller than the peripheral controller on the third printed circuit board to the peripheral bus through the third high-density connector system.
36. The computer system of claim 23, further comprising a fourth printed circuit board containing a second memory thereon and connected to the memory bus.
37. The computer system of claim 23, wherein the second printed circuit board contains a second memory.
38. The computer system of claim 23, wherein the second printed circuit board contains a second memory, and the microprocessor contains means connected to the second printed circuit board for controlling the first and second memory in an interleaved fashion.
39. The computer system of claim 23, wherein the second printed circuit board contains a second memory, and the microprocessor contains means connected to the second printed circuit board for controlling the first and second memory in a non-interleaved fashion.
40. The computer system of claim 23, wherein a number of memories on the second printed circuit board is determined by at least a size of the memories and a width of an address bus of the microprocessor.
41. The computer system of claim 23, further comprising a cache located on the first printed circuit board and connected to the microprocessor.
70 -
42. The computer system of claim 39, wherein the cache is removable from the first printed circuit board, thereby allowing different sizes of cache to be used with the microprocessor.
43. A computer system, comprising: a first plurality of slots for printed circuit boards using high-density connector systems, each connector system having a density of at least 100 contacts per linear inch; and a peripheral slot using through-hole connectors, wherein the first plurality of slots and the peripheral slot are located on a first backplane.
44. The computer system of claim 43, wherein the high- density connector systems are surface mount connectors.
45. The computer system of claim 43, wherein at least one of the high-density connector systems includes two high- density connectors placed on the first backplane so that at least two connectors contact both sides of a printed circuit board when the printed circuit board is mounted on the first backplane.
46. The computer system of claim 43, wherein the first plurality of printed circuit board slots are mounted on a front and a back side of the first backplane.
47. A computer system, comprising: a first plurality of slots for printed circuit boards using high-density connector systems, each connector system having a density of at least 100 contacts per linear inch, and located on a first backplane; a peripheral slot mounted on a second backplane; and a high-density connector system having a density of at least 100 contacts per linear inch connecting the first and second backplanes.
48. The computer system of claim 47, wherein the high- density connector is a surface mount connector.
49. The computer system of claim 47, wherein the first and second backplanes are connected using at least two high- density connector systems having a density of at least 128 contacts per linear inch.
50. The computer system of claim 47, wherein two of the plurality of slots are located on opposite sides of the first backplane.
51. A computer system, comprising: a local bus on a circular backplane; a memory bus on the circular backplane; a first printed circuit board including containing a microprocessor and associated circuitry thereon and being connected to the local bus and to the memory bus, the first printed circuit board transmitting and receiving a plurality of first signals from the local bus and a plurality of second signals from the memory bus; a second printed circuit board including containing a memory thereon and being connected to the memory bus, the second printed circuit board transmitting and receiving the plurality of second signals; and a third printed circuit board having a peripheral controller thereon and being connected to the local bus, the third printed circuit board transmitting and receiving the plurality of first signals; wherein at least one of the first, second, and third printed circuit boards is replaceable with a corresponding fourth printed circuit board having a similar general function as the at least one printed circuit board being replaced; and the computer system is adapted to accommodate different local bus sizes corresponding to the microprocessor.
52. The computer system of claim 51, further including a peripheral bus on the circular backplane, wherein the third printed circuit board is connected to the peripheral bus to transmit and receive third predetermined signals.
72 -
53. The computer system of claim 51, further including a cleated printed circuit board mounted on one of the first, second, and third printed circuit boards.
54. A CPU printed circuit board, comprising: a first high-density connector system for transmitting first predetermined interface signals for a local bus, the first high-density connector system having at least 100 contacts per linear inch; a second high-density connector system for transmitting second predetermined interface signals for a memory bus, the second high-density connector system having at least 100 contacts per linear inch; a microprocessor capable of outputting data, address, and control signals; means for translating ones of the data, address, and control signals from the microprocessor to the first predetermined interface signals for the local bus; and means for translating ones of the data, address, and control signals from the microprocessor to the second predetermined interface signals for the memory bus.
55. The printed circuit board of claim 54, wherein the control signals include interrupt signals, and further including means for translating the control signals from the microprocessor to interrupt signals for the local bus.
56. A controller printed circuit board, comprising: a first high-density connector system for transmitting first predetermined interface signals for a local bus, the first high-density connector system having at least 100 contacts per linear inch; a second high-density connector system for transmitting second predetermined interface signals for a peripheral bus; a controller for a type of peripheral device, and for outputting a plurality of signals;
- 73 - means for translating ones of the plurality of signals from the controller to the first predetermined interface signals for the local bus; and means for translating ones of the plurality of signals from the controller to the second predetermined interface signals for the peripheral bus.
57. The computer system of claim 56, further including: a second controller for controlling a second type of peripheral device, and outputting a plurality of signals; and means for translating ones of the plurality of signals from the second controller to the second predetermined interface signals for the peripheral bus.
58. The computer system according to claim 1, wherein the first printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second microprocessor having a different architecture from the microprocessor of the first printed circuit board.
59. The computer system according to claim 58, wherein the second microprocessor has a corresponding data bus with a different number of data bits than the microprocessor of the first printed circuit board.
60. The computer system according to claim 58, wherein the second microprocessor has a corresponding address bus with a different number of address bits than the microprocessor of the first printed circuit board.
61. The computer system according to claim 58, wherein the second microprocessor has at least a different operating speed from the microprocessor of the first printed circuit board.
62. The computer system according to claim 58, wherein the second microprocessor has at least a different instruction set from the microprocessor of the first printed circuit board.
- 74 -
63. The computer system according to claim 1, wherein the second printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second memory having at least a different memory size from the memory of the second printed circuit board.
64. The computer system according to claim 1, wherein the second printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second memory having at least different memory read and write speeds from the memory of the second printed circuit board.
65. The computer system according to claim 1, wherein the second printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second memory having at least a different memory addressing scheme from the memory of the second printed circuit board.
66. The computer system according to claim 1, wherein the second printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second memory having a corresponding data bus width different from the memory of the second printed circuit board.
67. The computer system according to claim 1, wherein the third printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second peripheral controller having a different design from the peripheral controller of the third printed circuit board.
68. The computer system according to claim 14, wherein the first printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second microprocessor having a different architecture from the microprocessor of the first printed circuit board.
- 75
69. The computer system according to claim 68, wherein the second microprocessor has a corresponding data bus with a different number of data bits from the microprocessor of the first printed circuit board.
70. The computer system according to claim 68, wherein the second microprocessor has a corresponding address bus with a different number of address bits from the microprocessor of the first printed circuit board.
71. The computer system according to claim 68, wherein the second microprocessor has at least a different operating speed from the microprocessor of the first printed circuit board.
72. The computer system according to claim 68, wherein the second microprocessor has at least a different instruction set from the microprocessor of the first printed circuit board.
73. The computer system according to claim 14, wherein the second printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second memory having at least a different memory size from the memory of the second printed circuit board.
74. The computer system according to claim 14, wherein the second printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second memory having at least different memory read and write speeds from the memory of the second printed circuit board.
75. The computer system according to claim 14, wherein the second printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second memory having at least a different memory addressing scheme from the memory of the second printed circuit board.
76. The computer system according to claim 14, wherein the second printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board
- 76 - including a second memory having a corresponding data bus width different from the memory of the second printed circuit board.
77. The computer system according to claim 14, wherein the third printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second peripheral controller having a different design from the peripheral controller of the third printed circuit board.
78. The computer system according to claim 51, wherein the first printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second microprocessor having a different architecture from the microprocessor of the first printed circuit board.
79. The computer system according to claim 78, wherein the second microprocessor has a corresponding data bus with a different number of data bits from the microprocessor of the first printed circuit board.
80. The computer system according to claim 78, wherein the second microprocessor has a corresponding address bus with a different number of address bits from the microprocessor of the first printed circuit board.
81. The computer system according to claim 78, wherein the second microprocessor has at least a different operating speed from the microprocessor of the first printed circuit board.
82. The computer system according to claim 78, wherein the second microprocessor has at least a different instruction set from the microprocessor of the first printed circuit board.
83. The computer system according to claim 51, wherein the second printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second memory having at least a different memory size from the memory of the second printed circuit board.
- 77 -
84. The computer system according to claim 51, wherein the second printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second memory having at least different memory read and write speeds from the memory of the second printed circuit board.
85. The computer system according to claim 51, wherein the second printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second memory having at least a different memory addressing scheme from the memory of the second printed circuit board.
86. The computer system according to claim 51, wherein the second printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second memory having a corresponding data bus width different from the memory of the second printed circuit board.
87. The computer system according to claim 51, wherein the third printed circuit board is replaced with the fourth printed circuit board, the fourth printed circuit board including a second peripheral controller having a different design from the peripheral controller of the third printed circuit board.
88. The computer system according to claim 1, wherein a size of the local bus can be varied depending on which one of the first printed circuit board and the second printed circuit board is connected to the local bus and the memory bus.
89. The computer system according to claim 14, wherein a size of the local bus can be varied depending on which one of the first printed circuit board and the second printed circuit board is connected to the local bus and the memory bus.
90. The computer system according to claim 51, wherein a size of the local bus can be varied depending on which one of the first printed circuit board and the second printed circuit board is connected to the local bus and the memory bus.
- 78 -
PCT/US1995/002676 1994-03-11 1995-03-09 Modular architecture for high bandwidth computers WO1995024729A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
AU20937/95A AU2093795A (en) 1994-03-11 1995-03-09 Modular architecture for high bandwidth computers
JP52354395A JP3727062B2 (en) 1994-03-11 1995-03-09 Modular structure for high bandwidth computers
KR1019960705038A KR970701885A (en) 1994-03-11 1995-03-09 MODULAR ARCHITECTURE FOR HIGH BANDWIDTH COMPUTERS
DE69521685T DE69521685T2 (en) 1994-03-11 1995-03-09 MODULAR DESIGN FOR COMPUTERS WITH WIDE BANDWIDTH
EP95913540A EP0749600B1 (en) 1994-03-11 1995-03-09 Modular architecture for high bandwidth computers

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US20887794A 1994-03-11 1994-03-11
US08/208,877 1994-03-11

Publications (3)

Publication Number Publication Date
WO1995024729A2 WO1995024729A2 (en) 1995-09-14
WO1995024729A3 WO1995024729A3 (en) 1996-05-02
WO1995024729B1 true WO1995024729B1 (en) 1996-07-18

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PCT/US1995/002676 WO1995024729A2 (en) 1994-03-11 1995-03-09 Modular architecture for high bandwidth computers

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US (8) US5822551A (en)
EP (3) EP0977127A2 (en)
JP (1) JP3727062B2 (en)
KR (1) KR970701885A (en)
AU (1) AU2093795A (en)
DE (1) DE69521685T2 (en)
WO (1) WO1995024729A2 (en)

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