WO1995010807A1 - Methode de realisation d'une connexion en parallele et connexion en parallele associee - Google Patents

Methode de realisation d'une connexion en parallele et connexion en parallele associee Download PDF

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Publication number
WO1995010807A1
WO1995010807A1 PCT/FI1994/000460 FI9400460W WO9510807A1 WO 1995010807 A1 WO1995010807 A1 WO 1995010807A1 FI 9400460 W FI9400460 W FI 9400460W WO 9510807 A1 WO9510807 A1 WO 9510807A1
Authority
WO
WIPO (PCT)
Prior art keywords
register
parallel interface
address
data
bit
Prior art date
Application number
PCT/FI1994/000460
Other languages
English (en)
Inventor
Esko Rautanen
Olli Rissanen
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Priority to GB9607561A priority Critical patent/GB2298065B/en
Priority to DE4497672T priority patent/DE4497672T1/de
Priority to AU78151/94A priority patent/AU7815194A/en
Publication of WO1995010807A1 publication Critical patent/WO1995010807A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus

Definitions

  • the invention relates to a method according to the preamble of claim 1 for realizing a parallel interf ⁇ ace in a device that is connected to a microcontroller or microprocessor, and a parallel interface according to the preamble of attached claim 7.
  • the invention also relates to a use of such a parallel interface in a circuit connected to a microcontroller or micro ⁇ processor, and in a microcontroller itself.
  • a micro ⁇ controller is here a device that comprises at least a microprocessor and I/O interfaces.
  • a microprocessor in turn is here generally any device operated by an external or internal program.
  • the method and parallel interface according to the invention can be utilized e.g. in microcontrollers, ASICs (Application Specific Integrated Circuits), programmable logic networks, special parallel interface circuits, and circuit modules, e.g. in MCM modules (MultiChip Module).
  • Fig. 1 illustrates the operation of a conventional 8-bit parallel interface. For simplicity and clarity, the figure shows an interface which has outputs only and the contents of which cannot be read by a micro ⁇ controller.
  • the parallel interface comprises eight out ⁇ puts B7...B0. The states of the outputs are stored in flip-flops D7...D0 in the data register of the parallel interface.
  • the interface may be e.g. a parallel port of a microcontroller. Seen from the controller, the paral- lei interface is located in one and the same address, indicated by A.
  • the object of the present invention is to pro- vide a parallel interface in which such errors do not occur and which thus also facilitates the programming since the possibility of errors need not be taken into account.
  • This object is achieved with the method and parallel interface of the invention, the method being characterized by what is stated in the characterizing part of attached claim 1, and the interface being characterized by what is disclosed in the characterizing part of attached claim 7.
  • the idea of the invention is to spread the data bits of individual signal interfaces of a parallel interface to different addresses, and to provide, by means of separate control data, an arrangement that indicates the addresses in which the data bits appear. Memory needed by data bits, however, is not necessarily added.
  • the solution of the invention makes it possible to program the address of the parallel interface signals in the address space of the microcontroller signal-spe ⁇ cifically.
  • the program is also simplified and speeded up in respect of input signals, since when data is read from a certain address, only data associated with the use concerned - but no other information - is obtained.
  • the parallel interface according to the inven ⁇ tion can be applied to inputs and outputs and to bidirectional interfaces also.
  • the invention is the most advantageous when applied to outputs and to parallel interfaces in which there are both inputs and outputs in one and the same interface.
  • Fig. 1 shows a conventional 8-bit parallel interface
  • Fig. 2 shows the principle of an 8-bit parallel interface according to the invention in its first embodiment
  • FIG. 3 shows one way of using a parallel int ⁇ erface according to the invention
  • Fig. 4 shows an alternative way of use for the example shown in Fig. 3,
  • Fig. 5 shows a second embodiment of a parallel interface according to the invention
  • Fig. 6 shows one advantageous way of using the parallel interface according to the invention
  • Fig. 7 shows a second advantageous way of using a parallel interface according to the invention
  • Fig. 8 shows a third advantageous way of using a parallel interface according to the invention
  • Fig. 9 shows a fourth advantageous way of using a parallel interface according to the invention.
  • Fig. 2 illustrates the operation of a first embodiment of an 8-bit parallel interface according to the invention having programmable addresses.
  • an interface which contains outputs only and the contents of which cannot be read by a controller.
  • a register of a parallel interface appears in several, here nine, different addresses A...A+8.
  • addresses A...A+8 Of the registers, only the control register appearing in address A is in its entirety (or, to be precise, with respect to seven bits) an actual register; from the data registers, only a total of eight bits have actually been realized.
  • the contents of the control register determine which bit of a data register appears in which address.
  • the contents of a data register appear as signals B7...B0.
  • Data bit DO always appears in address A+l in bit D10 of data register DATAl.
  • a parallel interface is to be divided between three different addresses so that the state of signal BO is controlled from address A+l, the state of signals B2...B1 from address A+2, and the state of signals B7...B3 from address A+3.
  • Reference X in Fig. 3 indicates that this particular position in the register is a virtual position (the bit is insignific ⁇ ant) .
  • the byte written in the control register is here 0000101X (X, the least significant bit, may be either one).
  • the situation may be e.g. such that signals B7...B3 provide a (readable) device address, signals B2 and Bl provide a (writable) selec ⁇ tion for the operation mode of a circuit, e.g. a communications circuit, and signal BO provides a (writable) signal for initializing the I/O circuits.
  • signals B7...B3 provide a (readable) device address
  • signals B2 and Bl provide a (writable) selec ⁇ tion for the operation mode of a circuit, e.g. a communications circuit
  • signal BO provides a (writable) signal for initializing the I/O circuits.
  • control register is written in when the device is initialized, and the written data is not changed during the operation of the device. How ⁇ ever, there is no obstacle to using the possibility offered by the solution according to the invention, i.e. changing the addresses during the operation, if neces- sary. If one wants to ensure that the control is main ⁇ tained, the control can be updated from the program or parameter memory of the device at suitable intervals.
  • the interface can be programmed bit-by-bit (signal-interface-by-signal- interface) to be either an input or an output
  • an 8-bit register where each bit indicates whether the corre ⁇ sponding signal interface functions as an input or out- put
  • Fig. 4 illustrates an alternative like this. In other respects, the operation of the solution according to Fig. 4 corre ⁇ sponds to the solution of Fig. 3.
  • the data bits Di of the interface can naturally be directed to different addresses in many other ways also.
  • the above exemplary solution leads to a relatively simple device solution, particularly if the positions of the bits within the byte are not changed.
  • the control register located in a single address can be replaced by any other control arrangement that indicates where the data bits can be found.
  • One alternative is to provide a specific mask register M1...M8 for every data register DATAl...DATA8 in a predetermined memory address. In each mask register M1...M8 there is a mask bit M in those bit positions that do not contain data bits; in other words, the data bits can be found in those bit positions where there is no mask.
  • the use of mask registers requires more memory than the use of a separ ⁇ ate control register. Otherwise the mask registers are used in the same way as a control register; in other words, mask bits are written at the start-up of the device and the masks are not changed during the use unless this is considered particularly necessary.
  • a conventional parallel register with address A (Fig. 1) has several outputs for different purposes as disclosed above, they usually need to be controlled from different processes of the program of the controller or by order of different processes.
  • the changing of outputs is often critical in respect of time, whereby the changes are made in an interruption routine.
  • the following is a description of a situation that may seem rare but is in fact common.
  • Process P must not change the outputs controlled in routine KR, nor routine KR the outputs controlled in process P.
  • Process P is running, and the controller has just read the state of parallel interface B from the corresponding shadow register located in the RAM to its internal register, with the intension of providing interface B with new contents as described above. If an interruption K now occurs, interruption routine KR is started.
  • the interruption routine stores the contents of the internal registers of the controller in the stack and starts the program of routine KR. Outputs B7...B3 of B will be changed, routine KR reading the shadow register.
  • the routine provides, without interruptions, interface B with a new content and writes it in address A of B.
  • routine KR comes to an end, and the processing of process P continues.
  • the previously read value of the shadow register is restored from the stack, but it is now erroneous in respect of bits B7...B3, since interruption routine KR has changed them.
  • Process P provides interface B with a new value, and as it writes the new values in address A, it restores the old values to bits B7...B3.
  • the above-described malfunction can be prevent ⁇ ed in many different ways. For example, it is possible to prohibit interruptions when the value of parallel interface B is being changed.
  • the change of values of parallel interface B may be allowed for one function only, re-calling of the function being inhibited as the function is being processed.
  • all these solutions make programming more difficult and often cause timing-dependences that are difficult to solve, particularly if the parallel interface contains time-critical signals.
  • the program easily becomes more and more complicated and critical.
  • outputs B2...B0 are defined e.g. in address A+l, and outputs B7...B3 e.g. in address A+2.
  • the values of outputs B2.. ,B0 are now changed by writing new values in address A+l, and the values of outputs B7...B3 by writing new values in address A+2.
  • the solution of the invention is especially advantageous in ASICs.
  • Those parallel interface signals of an ASIC that have a completely predetermined use that is independent of the use of the circuit and the manner of using it are advantageously defined in fixed addresses in the ASIC, and the solution of the invention is not especially advantageous therein.
  • general purpose parallel interfaces located in the ASICs and not having a predetermined use are realized as programmable interfaces according to the invention. This broadens the range of use of ASICs. If an ASIC contains a processor interface, it is possible to save other circuits by the parallel interface realized in the ASIC; this means saving of both costs and, above all, surface area of the printed circuit board of the device to be implemented.
  • a parallel interface according to the invention it is particular ⁇ ly advantageous to add a parallel interface according to the invention to the ASIC - although the interface is not involved in the actual operation of the circuit in any way - if pins otherwise remain unused in the ASIC (usually there are such pins, since the package sizes typically grow in steps of 20-30 pins) .
  • the useability of the ASIC for different purposes can hereby be improved, since part of the circuit can be programmed to be suited for different purposes in different devices.
  • the universal applicability of an MCM module can also be increased in a corresponding manner by utilizing at least some of the pins that would otherwise remain unused.
  • Fig. 6 illustrates such an alternative, the pins of the basic use of an ASIC or MCM circuit 60 being indicated by BU. Some of these pins of the basic use have been used for connecting the circuit via address, data and control buses 61 to a processor or controller 62.
  • the extra pins AU of the circuit package have been provided with a parallel interface according to the invention
  • the universal applicability of the MCM module can also be increased by adding thereto a small ASIC that implements a programmable parallel interface, or a programmable logic circuit in which a parallel inter ⁇ face according to the invention has been realized.
  • This alternative is illustrated in Fig. 7, in which the pro- cessor environment implemented in the MCM module com ⁇ prises a processor 71, a memory unit 73 (data memory and program memory), I/O circuits 72 and a bus 74 connecting them.
  • a programmable logic circuit 75 provided with a parallel interface PI according to the invention has been connected, the circuit making it possible to apply the MCM module more widely to different purposes (different I/O functions required by different fields of use can be realized flexibly). If large numbers are manufactured, it is advantageous to realize the programmable logic circuit 75 as an ASIC.
  • microcontrollers have one or more parallel ports. Each 8- or 16-bit port is located in a certain address either in the memory or I/O space of the controller. If one or more parallel ports PI or P2 of this kind of microcontroller 80 are formed as a programmable parallel port according to the inven ⁇ tion in the manner illustrated in Fig. 8, some of the above problems complicating the programming of a con ⁇ troller can be eliminated. This also enables a still more flexible use of the already universally applicable microcontroller.
  • the solution of the invention can also be applied to any universally applicable I/O circuit 90 (Fig. 9) to which a microcontroller 92 is connected via a bus 91 and by which the number of parallel ports of the microcontroller is increased.
  • the parallel interfaces in such circuits are located in fixed addresses, but it is now possible to realize one or more parallel interfaces of an I/O circuit as a programmable parallel interface PI according to the invention, whereby each address contains a desired number of the interface signals.
  • the solution of the invention can also be applied to different special circuits, which now have a parallel interface in a fixed, unchangeable address of the address space. The use of the interfaces for various purposes again leads to the situation described above; this can be avoided by realizing the interface with programmable addresses in accordance with the present invention.
  • control bits may be located in more than one address.
  • control bits may be located in more than one address.
  • a microcontroller is mentioned in the attached claims, it is to be understood to encompass a microprocessor also.
  • a memory location refers to a combination of data bits located in one and the same address.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)

Abstract

L'invention porte sur une méthode de réalisation d'une interface parallèle dans un dispositif relié à un microcontrôleur, et sur l'interface parallèle associée. L'interface comprend plusieurs interfaces de signaux (B0 ... B7) en parallèle, et la valeur de chacun des signaux est exprimée par un bit de données correspondant (D0 ... D7) situé dans une mémoire telle qu'un registre. Afin d'éliminer les erreurs, les bits de données (D0 ... D7) des interfaces de signaux sont répartis entre les registres de données (DATA1 ... DATA8) se trouvant à différentes adresses (A+1 ... A+8), des données de commande (C0...C7; M) étant prévues dans au moins une adresse prédéterminée de commande afin d'indiquer à quelles adresses se trouvent les bits de données (D0 ... D7).
PCT/FI1994/000460 1993-10-13 1994-10-12 Methode de realisation d'une connexion en parallele et connexion en parallele associee WO1995010807A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB9607561A GB2298065B (en) 1993-10-13 1994-10-12 Method for realizing a parallel connection, and a parallel connection
DE4497672T DE4497672T1 (de) 1993-10-13 1994-10-12 Verfahren zur Verwirklichung einer Parallelschaltung und Parallelschaltung
AU78151/94A AU7815194A (en) 1993-10-13 1994-10-12 Method for realizing a parallel connection, and a parallel connection

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI934522A FI94189C (fi) 1993-10-13 1993-10-13 Menetelmä rinnakkaisliitännän toteuttamiseksi sekä rinnakkaisliitäntä
FI934522 1993-10-13

Publications (1)

Publication Number Publication Date
WO1995010807A1 true WO1995010807A1 (fr) 1995-04-20

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PCT/FI1994/000460 WO1995010807A1 (fr) 1993-10-13 1994-10-12 Methode de realisation d'une connexion en parallele et connexion en parallele associee

Country Status (5)

Country Link
AU (1) AU7815194A (fr)
DE (1) DE4497672T1 (fr)
FI (1) FI94189C (fr)
GB (1) GB2298065B (fr)
WO (1) WO1995010807A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0056008A2 (fr) * 1981-01-05 1982-07-14 Sperry Corporation Dispositif d'écriture en domaines de longueur variable dans des mots de mémoire
EP0507951A1 (fr) * 1990-09-18 1992-10-14 Fujitsu Limited Procede de commande exclusive pour memoire partagee

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0056008A2 (fr) * 1981-01-05 1982-07-14 Sperry Corporation Dispositif d'écriture en domaines de longueur variable dans des mots de mémoire
EP0507951A1 (fr) * 1990-09-18 1992-10-14 Fujitsu Limited Procede de commande exclusive pour memoire partagee

Also Published As

Publication number Publication date
FI94189B (fi) 1995-04-13
AU7815194A (en) 1995-05-04
GB2298065B (en) 1998-01-14
FI94189C (fi) 1995-07-25
GB9607561D0 (en) 1996-07-03
DE4497672T1 (de) 1996-10-17
FI934522A0 (fi) 1993-10-13
GB2298065A (en) 1996-08-21

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