WO1994029960A1 - Controlled semiconductor capacitors - Google Patents

Abstract

A controlled capacitor system, which includes a capacitor element (C1) and a forward-biased diode element (D2) connected in series with the capacitor element (C1). The system is such that the diode element (D2) has a capacitance which is less than the capacitance of the capacitance of the capacitor element (C1) when the diode element (D2) is under zero bias. The capacitance of the diode element (D2) is controlled by varying the forward current (I2) through the diode (D2). The forward current (I2) acting to control the capacitance of the diode element is selected such that the capacitance of the diode element (D2) is smaller than the capacitance of the capacitor element (C1) when the current (I2) through the diode element (D2) is below a minimum value. The capacitance of the diode element (D2) is bigger than the capacitance of the capacitor element (C1) when the current (I2) through the diode element (D2) exceeds a maximum value.

Description

CONTROLLED SEMICONDUCTOR CAPACITORS

FIELD AND BACKGROUND OF THE INVENTION

The present invention relates to semiconductor devices and, more particularly, to a new class of semiconductor devices known as "controlled" semiconductor capacitors (CC's), in which the capacitance can be varied using an external control agent such as current or a form of radiation, such as light.

Various attempts have been made to develop devices which include the high-speed control of a capacitance by an external source. To date, these attempts have been largely unsuccessful.

Well known in the art are varactors, in which the capacitance is controlled by a voltage. However, varactors provide only a partial solution since their basis of operation inherently restricts the range of the maximum to minimum capacitance ratios (C_max/C_min) obtainable in a narrow range of voltage changes, and their operating voltage is relatively low.

Also known are certain novel and rather exotic devices which are based on quantum well technologies. However, the performance of these devices also leaves much to be desired.

There is thus a widely recognized need for, and it would be highly advantageous to have, capacitors in which the capacitance can be changed over a wide range at a fixed applied voltage by the action of external factors, such as current or radiation, and the like, and which will feature performance which significantly exceeds that possible with presently known devices.

SUMMARY OF THE INVENTION

According to the present invention there is provided a controlled capacitor system, comprising: (a) a capacitor element; and (b) a diode element connected in series with the capacitor element, the diode element being forward-biased, the system being further characterized in that: (i) the diode element has a capacitance which is less than the capacitance of the capacitor element when the diode element is under zero bias; (ii) the capacitance of the diode element is controlled by varying the forward current through the diode element; and (iii) the forward current acting to control the capacitance of the diode element is selected such that the capacitance of the diode element is smaller than the capacitance of the capacitor element when the current through the diode element is below a minimum value; and (iv) the capacitance of the diode element is bigger than the capacitance of the capacitor element when the current through the diode element exceeds a maximum value.

According to further features in preferred embodiments of the invention described below, the diode element or capacitor is shunted by a device selected from the group consisting of a variable resistor, a reversebiased diode, a photodiode, a photoresistor and a radiation sensor.

According to still a further embodiment according to the present invention, the capacitor element is a reverse-biased diode.

According to features of a preferred embodiment of the present invention the diode element is a GaAs P⁺PiN diode fabricated on a P⁺ substrate having a carrier concentration in the i-region of less than 10¹²cm^-3.

The present invention successfully addresses the shortcomings of the presently known configurations by providing a controlled capacitor system which operates over a wide range of operating parameters and which features performance parameters which are significantly superior to those of presently known devices.

In principle, capacitance control can be effected using various combinations of traditional discrete elements such as semiconductor diodes arranged in suitable electrical circuits. However, the performance parameters of such devices, particularly in silicon, prevent a practical realization of such schemes or lead to schemes which are uneconomical. According to the present invention, controlled capacitors can be fabricated using various techniques and devices. Preferably, these include using GaAs PiN diodes having a near-fully compensated i-region of controllable width, either alone or in combination with high-voltage GaAs Schottky diodes.

It appears that the most effective use of GaAs is in the context of light- or other radiation-controlled capacitors, which can take advantage of the advantages of its direct zone structure. It should be noted, however, that the principles of design and operation presented here allow development of controlled capacitors based on other semiconductor materials, if their properties and the fabrication technology allow the realization of these principles.

Controlled capacitors according to the present invention represent a new class of semiconductor devices having a wide range of possible applications in both high-power and low-power electronics and electrical engineering.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:

FIG. 1a is a schematic depiction of a series connection of a constant capacitor C₁ and a variable capacitor C₂;

FIG. 1b is a representation of the dependence of the voltage on the capacitor over time. At time t1 a source acts (H>0) to influence the capacitor C₂; at t₂ the influence ends (H=0);

FIG. 2 is a the C-V curve of the scheme in Figure la, which includes a jump in the capacitance at voltage V₁, when the external source acts (H>0) to increase the capacitance C₂. The influence ends at V₂; FIG. 3a is a schematic depiction of a series connection of a capacitor C₁ and a forward-biased semiconductor diode D₂. C₁ is shunted with a variable resistor R₁;

FIG. 3b shows the equivalent circuit of Figure 3a: C_t-depletion capacitance of diode D₂. Both are functions of I₂, the current through D₂.

FIG. 4 features the calculated dependencies of the diffusion and depletion capacitances as well as the total capacitance as a function of the current through a GaAs and a Si diode;

FIG. 5 is a graphic illustration of the C-V characteristics of the circuit shown in Fig.3 for R₁=const and R₁=f(V);

FIG. 6a, 6b, 6c and 6d are graphic illustrations of the C-V characteristics of the circuit shown in Figure 3 for resistors R₁ with various I-V characteristics;

FIG. 7 is a schematic depiction of a hybrid, or non-integrated, or non-monolithic, construction based on a capacitor and a diode connection in series. A switch (K) is used to control the current through the diode;

FIG. 8 is a schematic depiction of a hybrid construction using a reverse-biased diode D₁ as a resistor R₁;

FIG. 9 is a schematic depiction of a construction in which the current through diode D₂ which is biased at a fixed voltage, is controlled by the action of an external factor (e.g. light) on the reverse biased diode D₁;

FIG. 10 is a schematic depiction of a hybrid construction used to control the current through diode D₂ by a separate source V₂;

FIG. 11 a shows two diodes connected in series in opposite directions to each other ("back-to-back");

FIG 11b shows the equivalent circuit of Figure 11a;

FIG. 12 is a graphic illustration of the C-V characteristics in a current controlled capacitor, or CCC, for two typical reverse I-V characteristics of a diode D₁: (1) a "soft" characteristic and (2) a "hard" characteristic;

FIG. 13 is a graphic illustration of the C-V characteristics dependence on light irradiation. The reverse I-V characteristic of diode D₁ is controlled by light irradiation. This is an embodiment of a light controlled capacitor or LCC. H = intensity of light;

FIG. 14 is a graphic illustration of the CCC C-V characteristics as a function of the capacitance characteristics of the reverse-biased diode D₁;

FIG. 15 shows an LCC construction variant, where diode D₁ is shunted by a photoresistor R_H1;

FIG. 16 is an LCC construction variant where diode D₁ is shunted by a photodiode D_H1;

FIG. 17 is a graphic illustration of the dependence of the C-V characteristics of the circuits shown in Figures 15 and 16 on light intensity (H);

FIG. 18 is a CCC construction variant, where it is possible to decrease the current through diode D₂ by a shunt resistor R₂ ;

FIG. 19 is an LCC construction variant, where it is possible to decrease the current through diode D₂ by a shunt photoresistor R_H2 ;

FIG. 20 is an LCC construction variant, where it is possible to decrease the current through diode D₂ by a shunt photodiode D_H2;

FIG. 21 is a graphic illustration of the C-V characteristics for the circuits shown in Figures 19 and 20 on light intensity (H);

FIG. 22 shows an electric field (E) distribution and depletion region propagation in a PiN structure with a near-fully compensated W_i-wide i¬region;

FIG. 23 shows the dependence of the depletion capacitance of the GaAs PiN structure under zero bias, C_t(0), on the net carrier concentration (N_d - N_a)_i in the i-region. x_i(0) is the depletion width under zero bias; FIG. 24 shows the experimentally determined dependence of the depletion capacitance at zero bias, C_t(0), on diode areas, for three GaAs PiN diode sets, each set having a different W_i;

FIG. 25 shows the experimentally determined dependence of the total GaAs PiN diode capacitance, C(V), on forward bias. (W_i⋍ 20μm, A = 0.3cm²);

FIG. 26 shows the calculated dependence of the total GaAs PiN diode capacitance, C(I), and its components on the forward current (for an area of 0.3cm²): 1 - diffusion capacitance, C_d; 2 - depletion capacitance C_t for the case when the i-region width W_i is greater than the depletion region width X_j(V); 3 - depletion capacitance for the case when W_i=20μm; 4 total capacitance for W_i > X_j(V); 5 - total capacitance for W_i = 20μm; 6 experimental C(I) dependence;

FIG. 27a shows experimental I-V characteristics of four capacitors (#31, 41, 52 and 54) with different R., of the reverse-biased diode D₁ (in this integrated, or monolithic, embodiment a Schottky diode, D₁, and a PiN diode, D₂, are fabricated on the same single crystal GaAs substrate);

FIG. 27b is an illustration of the dependence of V_min and ΔC/ΔV on R_d and shows experimental C-V curves of four capacitors (# 31, 41, 52 and 54). The figure shows clearly the increase in V_min and the decrease in ΔC/ΔV when R_d increases;

FIG. 28a shows experimental reverse I-V characteristics of diode D₁ (Schottky diode with area A. = 3 × 3mm²) without light irradiation ("dark") and with light irradiation ("light");

FIG. 28b shows experimental C-V characteristics of an integrated

LCC under illumination ("light") and without it ("dark"); in this integrated variant a Schottky diode D₁ and PiN diode D₂ are fabricated on the same single-crystal GaAs substrate;

FIG. 28c shows a more detailed view of the C-V characteristics of the same LCC around zero bias; FIG. 29a shows an integrated construction of a controlled capacitor: D₁ is a Schottky diode with full-area contact;

FIG. 29b shows an integrated construction of a controlled capacitor: D₁ is a Schottky diode with "windows" in the metal contact;

FIG. 30 shows experimentally determined C-V characteristics of an integrated GaAs LCC as shown in Figure 29a under illumination ("light") and without illumination ("dark"). The areas of the Schottky diode A₁ and the PiN diode A₂ are 3 × 3mm². W_i in D₂ is 20μm;

FIG. 31 shows experimentally determined C-V characteristics of an integrated GaAs LCC as shown in Figure 29a under pulse illumination ("light" and "dark") and without illumination ("dark"). D₁ and D₂ diode areas are 2 × 2mm², W_i in D₂ is 30μm;

FIG. 32a shows the experimentally determined I-V characteristics of a GaAs LCC with integrated construction (as in Figure 29a) under different illumination intensities. A₁ = A₂ = 3 × 3 mm²;

FIG. 32b shows the experimentally determined C-V characteristics of a GaAs LCC with integrated construction (as in Figure 29a) under different illumination intensities. A₁ = A₂ = 3 × 3 mm²;

FIG. 33a shows another possible integrated construction of a controlled capacitor. D₁ is a PN diode with full-area ohmic contact;

FIG. 33b shows another possible integrated construction of a controlled capacitor. D₁ is a PN diode with "windows" etched into the ohmic contact and the P-layer down to the N-layer;

FIG. 34 shows an integrated construction of a controlled capacitor which uses a transparent layer (in this case In_xO_y) as the Schottky barrier for diode D₁. A corner metal pad provides the ohmic contact to the transparent barrier;

FIG. 35 shows an integrated construction of a controlled capacitor with a PN heterojunction as diode D₁. A window is etched in the top metal contact to allow penetration of radiation; FIG. 36a shows an integrated construction of a controlled capacitor fabricated on a N⁺ substrate with an ohmic contact to the N-layer;

FIG. 36b shows an integrated construction of a controlled capacitor fabricated on a N⁺ substrate with a Schottky barrier to the N-layer;

FIG. 37a shows a matrix design for controlled capacitor arrays with

Schottky diodes as D₁. The top metal, or top metal and P-layer are etched in a "comb" form to allow penetration of radiation;

FIG. 37b shows a matrix design for controlled capacitor arrays with PN diodes as D₁. The top metal, or top metal and P-layer are etched in a "comb" form to allow penetration of radiation;

FIG. 38 shows a parallel connection of many arrays as in Figure 37 on a common metallic anode;

FIG. 39a and 39b show an inverted controlled capacitor construction, i.e., a design with a forward-biased Schottky diode as D₂, and a reverse-biased PiN diode as D₁;

FIG. 40 shows experimentally determined C-V characteristics of the inverted construction with a dot barrier contact to the low-doped N-layer of a GaAs PiN diode structure of 2 × 2 mm² area (A₂ « A₁) and W_i = 20μm;

FIG. 41 shows an inverted matrix construction with a reverse-biased common PiN diode D₁. (1) - "windows"; (2) - dielectric compound;

FIG.42a shows a hybrid construction, i.e., separate back-to-back D₁ and D₂ diodes, of a controlled capacitor comprising two PN diodes as D₁ and D₂ with equal or with different areas. In this illustration, the diodes are "glued" together by a conductive medium;

FIG. 42b shows a hybrid construction, i.e., separate back-to-back D₁ and D₂ diodes, of a controlled capacitor comprising a PN diode as D₁ and a PiN diode as D₂, the diodes may have equal or different areas. In this illustration, the diodes are "glued" together by a conductive medium; FIG. 43a shows a hybrid construction of a controlled capacitor including a reverse-biased Schottky diode and forward-biased PiN diode with equal or different areas, and with full-area Schottky contact.

FIG. 43b shows a hybrid construction of a controlled capacitor including a reverse-biased Schottky diode and forward-biased PiN diode with equal or different areas and with "windows" in the Schottky contact.

FIG. 44a shows a hybrid construction of a controlled capacitor including two back-to-back PiN diodes with equal or different areas; full¬area ohmic contact to the N-layer of the reverse-biased diode;

FIG. 44b shows a hybrid construction of a controlled capacitor including two back-to-back PiN diodes with equal or different areas and with "windows" in the ohmic contact and the N-layer of the reverse-biased diode;

FIG. 45a shows experimentally determined I-V characteristics of a GaAs Schottky diode of 3 × 3 mm² area with a comb-shaped barrier metallization of 0.04 cm² active area A₁ (area of Schottky barrier). H light intensity;

FIG. 45b shows experimentally determined C-V characteristics of a hybrid LCC composed of a Schottky diode as in Figure 44a, and of a GaAs PiN diode of 0.36 cm² area and W_i = 20μm: 1 - "dark" C-V of the LCC;

2 - "dark" C-V of the Schottky diode; 3 - the capacitance of the LCC is changing between (1) and (2) when illumination is switched on and off;

FIG. 46a shows the I-V characteristics of a similar GaAs Schottky diode to that of Figure 45a but with an active Schottky diode area of about 0.07 cm²;

FIG. 46b shows the C-V characteristics of a similar LCC to that of Figure 45b but with an active Schottky diode area of about 0.07 cm². As a result, the C_max values are also higher than in Figure 45;

FIG. 47a shows the parallel connection of many hybrid controlled capacitors on a common metal anode. D₁ - reverse-biased PiN diodes with a "comb" shape etched top contact and N-layer, D₂ - forward-biased PiN diodes;

FIG. 47b shows the parallel connection of many hybrid controlled capacitors on a common metal anode. D₁ - reverse-biased Schottky diodes with a "comb" shape etched metal barrier, D₂ - forward-biased PiN diodes;

FIG. 47c shows the parallel connection of many hybrid controlled capacitors on a common metal anode. Top view of the structures in Figures 47a and 47b;

FIG. 48 is a schematic depiction of the dependencies of the illumination, the current through diode D₁ and the capacitance with time;

FIG. 49 is a depiction of the time dependence of capacitance when the unloading time is determined mainly by τ_d;

FIG. 50a is a suggested scheme for a CCC-based alternating voltage¬to-alternating capacitance converter;

FIG. 50b shows the V(t) and C(t) dependencies of the scheme of

Figure 50a;

FIG. 51a depicts using an LCC to convert a radiation pulse into a capacitance pulse without a special receiver of radiation (D₁ is itself radiation sensitive);

FIG. 51b depicts using an LCC to convert a radiation pulse into a capacitance pulse with a special receiver of radiation (such as a photodiode, photoresistor, etc.);

FIG. 51c depicts the time dependence of the radiation and the capacitance using an LCC to convert a radiation pulse into a capacitance pulse;

FIG. 52 depicts the control of capacitance through the control of the charge in diode D₂ using a separate current source. DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention is of controlled semiconductor capacitors. Specifically, the present invention is of a family of capacitors whose capacitance can be changes quickly and effectively over wide ranges at a wide-ranging set of operating conditions.

The principles and operation of controlled capacitors according to the present invention may be better understood with reference to the drawings and the accompanying description.

Shown in Figure la. is a simple circuit which includes two capacitors. The total capacitance, C, of two capacitors C₁ and C₂ connected in series is given by:

1/C = 1/C₁ + 1/C₂ (1)

Capacitance C₂ can be quickly changed over a wide range of values using one or more influences or agencies. Assume, for the sake of exposition, that the range of variation of the capacitance C₂ is such that:

C₂ < C₁, whenever the influence is absent (or sufficiently weak) C₂ > C₁, whenever the influence is sufficiently intense.

Then, if the voltage on the capacitors increases with time as shown in Figure lb, and at a certain moment t₁ a source having an intensity H acts to influence the capacitor C₂, the C-V curve displays a jump of the capacitance at V = V₁ (Figure 2). If C₂ » C₁ then from Equation (1) one obtains that C_max→C₁. At the end of the influence (t₂) the capacitance returns to the initial value of C_min at V = V₂, and if C₂ « C₁, C_min→ C₂.

The above-described concept can be applied to the circuit of Figure 3a, which is shown equivalently in Figure 3b. The semiconductor diode D₂ in Figure 3a is forward-biased by the applied voltage and is connected in series with capacitor C₁. Capacitor C₁ is shunted by a variable resistivity element R₁. In such a circuit, when the leakage current of the capacitor is sufficiently small or negligible, the current across diode D₂ will be determined mainly by the applied voltage and by the resistivity R₁. A current controlled capacitor (CCC) according to the present invention causes the capacitance of diode D₂ to be regulated, or changed, by passing through the diode a forward current which is controlled by the resistivity R₁.

The operating principle of CCC's according to the present invention can be better understood with reference to Figure 3 and the accompanying description.

When the leakage current of the capacitor C₁ is zero, the current through diode D₂ is given by

I₂ = [V - V₂(I₂)]/R₁ (2) where V is the applied external bias, and V₂(I₂) is the forward voltage drop which is determined by the diode I-V characteristics. Remembering that the forward voltage drop on a PN junction or on a metal-semiconductor barrier does not exceed the contact potential ψ, which for most practical semiconductors does not exceed IV, then, when V » IV, the current through the diode is simply,

I₂⋍ V/R₁ (3)

The equivalent circuit of a PN junction diode is shown in Figure 3b. It is well known that a PN junction can be represented by two parallel capacitances, namely C_t, the "transition" or depletion region capacitance, and C_d, the diffusion capacitance. In surface-barrier devices in which the current is of majority carriers only, such as Schottky diodes, the diffusion capacitance is zero.

The capacitance of a PN diode can be controlled within a wide range by changing the injection of minority carriers with forward current (the diffusion capacitance), and by changing the depletion region width (the depletion capacitance) (Figure 4).

The diffusion capacitance of a diode D₂ is given by:

C_d = [A₂qτ/kT]_j0exp(qV₂/kT) = qτI₂/(kT) (4) where τ is the lifetime of the carriers, I₂ is the current across the diode, and A₂ is the PN junction area. This expression is valid if the ratio of the low-doped base thickness, W, to the diffusion length L is greater than 1, i.e., W/L>1. If W/L « 1, a correction factor of W/2L must be introduced, i.e.,

C_d = (qτI₂/kT)(W/2L) (5)

The limit value of C₂(I_lim) shown in Figure 5 and given in Equations (4) and (5) is determined by low or intermediate injection levels in the low-doped N region of the PN structure (in the case of a diode with an abrupt asymmetric PN junction, N_a[P] » N_d[N], where N_a and N_d are, respectively, the acceptor concentration in the P region and the donor concentration in the N region) or in the i-region of a PiN structure.

The limit value of the current density can be obtained from the conditions:

j_lim = (qD_p/L)p(0)_lim, if W/L»1, (6) and

j_lim = [P_avg(x)qW]/τ, if W/L<1 (7) where p(0) is the concentration of injected carriers on the N-side boundary of the PN junction, and p_avg(x) is the average concentration of injected carriers over the N-base. Assuming p(0)_lim = N_d, (or (N_d-N_a)_i in any i¬layer) and p_avg(x)_lim = N_d and inserting into Equations (6,7), one obtains:

j_Iim⋍qD_pN_d/L, if W/L>1 j_Iim⋍ qWN_d/τ, if W/L<1 (8)

Taking D_p⋍ 10cm²/sec, which is approximately the value of the diffusion coefficient of holes in low-doped Si and GaAs, τ⋍ 100ns and L⋍ 10^-3cm, one obtains for W > 20-30μm:

j_lim = 1.6×10^-2 A/cm² when N_d⋍ 10¹⁴cm³ j_lim = 1.6×10^-4 A/cm² when N_d⋍ 10¹²cm^-3 and for W⋍ 10μm:

j_lim = 1.6×10^-1 A/cm² when N_d = 10¹⁴cm^-3 j_lim = 1.6×10^-3 A/cm² when N_d = 10¹²cm^-3 Thus, for any combination of parameters within a wide range of W and N_d values, j_lim will vary between 0.1 and 160mA/cm². The calculation of C_d from Equations (4) and (5) is valid only in the region where the current I₂ is lower than I_lim, i.e., where,

I₂≤ A₂ × j_lim (9)

The depletion capacitance for an abrupt asymmetric PN junction (N_a » N_d) can be found from Equation (10):

C_t2 = A₂ × [∈∈₀qN_d/(2(ψ-V₂))]^0.5 (10) where ψ is the contact potential:

ψ = (kT/q)ln(N_aN_d/n_i ²) (11)

The forward voltage drop on diode D₂ is

V₂⋍ V_j = (kT/q)ln[(I₂/A₂)/j₀ + 1] (12) where V_j is the junction potential, and

j₀⋍ (qD_pP_n)/L = [q(D_p)^0.5n_i ²]/[(τ)^0.5N_d]

Figure 4 shows the diffusion and depletion capacitances, as well as the total capacitance (C₂) of a GaAs and a Si diode (N_d = 10¹⁴cm^-3, A₂ = 1cm²) plotted against the current through the diode. In a wide current range from 10^-11 to 10^-4A, the total diode capacitance is determined mainly by the depletion component and changes only slightly. Above current values of about 10^-4 A, the diffusion capacitance begins to dominate, and the total capacitance increases very quickly to the value corresponding to I_lim [C₂(I_lim)].

From Equations (1-12) one obtains the following system of equations describing the dependence of the capacitance on the voltage in the circuit shown in Figure 3 (if the current through the capacitor C₁ is zero):

1/C(V) = 1/C₁ + 1/[C_t2(I₂) + C_d2(I₂)] and (13)

I₂ = (V-V₂)/R₁⋍ V/R₁ A graphic illustration of the solution of system (13) for R₁ (V) = const and R₁ (V) = V^-n, is shown in Figure 5. Using it one can explain the operating principle of the current controlled capacitor shown in Figure 3. One can now determine the values of C_max and C_min and the corresponding values of I_max, I_min, V_max, V_min, (C_max)/( C_min) and ΔC/ΔV⋍ ( C_min- C_min)/(V_max-V_min) in Figure 5. I_min and I_max are obtained from generally accepted conditions:

C(V)_max = 0.9C₁

and

C(V)_min = 1.1C_t2(O) (14) where C_t2(O) is the capacitance of the diode D₂ at zero bias, i.e., when the current through the diode is zero, and C₁ is the capacitance of capacitor C₁. Inserting these conditions into the first equation of the Equation system (13) we obtain:

1/1.1C_t2(O) = 1/C₁ + 1/[C_t2(I_min + C_d2(I_min)]

1/0.9C₁ = 1/C₁ + 1/[C_t2(I_max + C_d2(I_max)] (15) I_min and I_max obtained from the solution of Equation system (15) are inserted into the second equation of Equation system (13) yielding C_min and V_max values:

V_max = R₁ × I_max

and (16)

V_{mi x} = R₁ × I_max

Using Equations (15) and (16) one can formulate the requirements for the parameters of diode D₂, capacitor C₁, and resistor R₁ (Figure 3) in order to obtain the optimal values of C_max/C_min, ΔC/ΔV, V_min and V_max.

Figure 6 presents qualitatively the C-V characteristics of the circuit shown in Figure 3 for resistors R₁ with various I-V characteristics. These characteristics are next examined in detail. The following points are to be noted. 1) R₁ = const (Figure 6a). The current through the diode is determined by the voltage V. This case is straightforward. The smaller the resistance R₁, the lower will be V_max and V_min, while the slope ΔC/ΔV will increase (Figure 5):

ΔC/ΔV = ( C_max- C_min)/(I_max-I_min)R₁ (17)

The limit value of C_max/C_min is given by:

(C_max/C_min)_lim→ C₁/C₂(O) (18)

2) V⋍ constant, while the resistivity of the diode is changed abruptly (Figure 6b). This case is realized when R₁ decreases abruptly because of the influence of external factors (e.g., a photoresistor under the influence of light, the breakdown of a dielectric upon reaching a critical field value, the avalanche breakdown of a PN junction, and the like). The C-V characteristics of such a case is shown in Figure 6b. When the external influence is absent (H = 0), the resistance R₁ is large, and the current through the diode, I₂, is lower than I_min over the entire voltage range. In this case the capacitance of the circuit in Figure 3 is voltage-independent and is determined by the value of the diode capacitance under zero bias. If now at some voltage V_H an external influence of sufficient intensity H_max is applied to the resistor R₁ (for example a photoresistor is illuminated), the resistance of R₁ will decrease abruptly, and the current through the diode will also increase abruptly to the I_max value. In this case a capacitance "jump" superimposed on the C(V) dependence will appear. The slope of the curve ΔC/ΔV is:

ΔC/ΔV⋍ (C_max-C_min)/[V₂(I_max - V₂(I_min)] (19) where V₂(I_max) and V₂(I_min) are the voltage drops across the diode, corresponding to I_max and I_min, respectively.

It is to be noted that in this example the ΔC/ΔV value can be rather large because the ΔV value can be a small fraction of a volt. 3) R₁≠ const (non-linear resistor)

(a) Here R₁ is voltage-dependent (R₁ ~ V^-n, where -1< n≤ ψ) and does not depend on external factors. The current through the diode in this case is I₂ ~ V⁽¹⁺ⁿ⁾ (R = const is a special case, when n = 0). As can be seen in Figure 6c, the threshold voltage and the slope ΔC/ΔV depend on the n value. In many applications, R₁ can be replaced by a reverse-biased diode.

(b) A "composite" case (Figure 6d) is obtained when R₁ depends on both the voltage (R - V^-n) and on the external factors (R ~ 1/H). Such a combined dependence, C(V,H), can be achieved by using as R₁ a diode connected in a reverse direction, with the I-V characteristics sensitive to the influence of external radiation.

In an embodiment shown in Figure 7, a switch can be used to control the current through diode D₂. By turning on and off a switch (K) one can control the capacitance of the circuit at a given voltage. It is necessary only that when the switch is "on" (position 2), I₂≥ I_max, and when it is "off (position 1), I₂ < I_min, that is, the leakage current of the capacitor C₁ is not zero.

Illustrated in Figure 8 is the use of a reverse-biased diode D₁ as a resistor R₁. The current through diode D₂ is now determined by the reverse

I-V characteristic of diode D₁. D₁ can be a PN diode or a surface-barrier diode (Schottky diode). The capacitance of D₁, C_D1, is added to the capacitance C₁:

C₁(V) = C₁ + C_D1(V) (20)

The reverse current through diode D₁ is:

I(V) = A₁ × j_v(V) × M(V) + I_s(V) (21) where, A₁ - the area of D₁;

j_v(V) - the volume component of the reverse current;

I_s(V) - the surface leakage current;

M(V) - the avalanche multiplication coefficient: M(V) = 1/[1-(V/V_BR)ⁿ] (22)

V_BR - avalanche breakdown voltage; and

n - coefficient determined by the semiconductor material and by the parameters of the rectifying element.

The calculation of the I-V dependence is rather difficult because of the uncertainties in some parameters and components of the reverse current, such as m and I_s. It is therefore easier in most cases to use the experimental reverse I-V characteristics for the design and calculation of the current-controlled capacitors.

Another way to control the current through the diode at a given voltage is to act with an external factor on the reverse part of the I-V characteristic of diode D₁ (Figure 9). The influencing factor may be visible light, infrared or ultraviolet radiation, X-ray or γ radiation, nuclear particle radiation, and the like. Each of these radiations influences the generation-recombination component of the reverse current, sometimes increasing it by many orders of magnitude. The practical implementation can be carried out by selecting an industrial diode or by designing a special diode which will satisfy the following requirements:

(1) the reverse current without external influence is lower than I^ over a wide range of applied voltages;

(2) the action of an external influence of intensity H has to increase the reverse current up to I_^; and

(3) a high sensitivity, i.e., a maximum value of (I_max-I_min)/H_max has to be obtained by the smallest possible H_^ value which corresponds to I_max

Figure 10 illustrates the regulation of the current through diode D₂ using a separate source (V₂). The control of the current through diode D₂ in the range from I_min to I_max, and consequently the control of C_min and C_max, is possible through the use of a separate source (V₂) with a voltage from zero to about IV. A controlled capacitor system according to the present invention is characterized in that:

1. The system includes a series connection of a forward-biased semiconductor diode and a capacitor.

2. The value of the capacitance of the capacitor connected in series with the diode exceeds the capacitance of the diode under zero bias, i.e., the "zero capacitance".

3. The capacitance of the diode is controlled by controlling the forward current through the diode.

4. The range of the forward current control is selected in such a way that if the current through the diode is less than I_min, the capacitance of the diode is lower than the capacitance of the capacitor connected in series, (C₂ < C₁), and if the current is higher than I_max the diode capacitance is higher than C₁, i.e., C₂ > C₁.

The connection of two diodes in series and in an opposite direction to each other ("back to back") and their equivalent circuit is illustrated in Figure 11. C_t1 is the depletion capacitance of the diode, and R- is the differential resistivity of the reverse I-V characteristic of this diode. An important point is that both C_t1 and R₁ are voltage-dependent. C_t2 and C_d2 are the depletion and diffusion capacitances, respectively, of diode D₂. The system of expressions used to describe the circuit is:

1/C(V) = 1/C_t1 + 1/(C_t2 + C_d2)

C_t1(V) = A₁(q∈∈₀N_d1/2[ψ₁ + (V-V₂)])^0.5

C_t2(V) = A₂[(q∈∈₀N_d2)/2(ψ₂ - V₂)]^0.5

ψ₁ = (kT/q)1n[N_a1N_d1/(n_i)²]

ψ₂ = (kT/q)1n[N_a2N_d2/(n_i)²] (23)

C_d2 = qτI/(kT)

V₂ = (kT/q)1n[(I/A₂)/j₀₂ + 1] j₀₂ = qD_pp_n/L = q(D_p)^0.5(n_i)²/[(τ)^0.5N_d2]

I = A₁ × j_v(V-V₂) + I_s

For simplification the assumption is made that V » V₂, so that

V-V₂⋍ V and ψ₁ + V - V₂⋍ V.

From the previous analysis it follows that the necessary

condition for obtaining the value of C_max at voltage V_max is that the capacitance of diode D₁ at V_max be greater than the capacitance of diode D₂ under zero bias (I = 0 or V₂ = 0) i.e.,

C_t1(V_max) > C_t2(O) (24)

If one sets a definite value for the term C_t1(V_max)/ C_t2(O), one can calculate certain diode parameters and obtain the voltage range. From system (23) one obtains:

C_t1(V_max)/ C_t2(O) = A₁/A₂ [N_d1 ѱ₂/(N_d2V_max)]^0.5 (25) where V_max is lower than the breakdown voltage of diode D₁, V_BR1, i.e., V_max < V_BR1. From Equation (25) one can reach some interesting conclusions. One can assume, for example, that V_max = 100V,

C_t1(100)/C_t2(0) = 10 and ψ₂⋍ 1. The maximum concentration N_dl can be obtained from the condition V_max < V_BR1. Calculations made using known expressions show that in this case N_d, ≤ (2-3) × 10¹⁵cm^-3. From Equation (25) it follows that if N_d1 = N_d2 then the ratio of the areas A₁/A₂ has to be about 100, i.e., the area of the PN junction of diode D₁ has to be about 100 times larger than that of diode D₂. The ratio will be smaller if N_d1 > N_d2, but there is a limit imposed by the fact that modern semiconductor technology permits production of low-doped Si and GaAs layers with a minimum concentration of about 10¹³-10¹⁴ cm^-3. For the "best" case when

N_d2⋍ 10¹³cm^-3, i.e., N_d1/ N_d2⋍ 100, the area ratio A₁/A₂ of diodes D₁ and

D₂ will be about 10.

This analysis shows that even the design of a circuit with a relatively low voltage of 100V and with a low effective ratio of diode areas of 10-100, stretches the ability of modern technology. To increase the voltage and to decrease the ratio A₁/A₂ it is necessary to decrease the donor concentration in the base regions of both diodes. For example, for A₁/A₂ = 10 and at V_max = 1000V, the concentrations N_d1 and N_d2 have to be 10¹⁴ and 10¹¹cm^-3, respectively.

An especially interesting case occurs when A₁/A₂ = 1. The calculation shows that at 100V (N_d1⋍ (2-3) × 10¹⁵cm^-3) the concentration N_d2⋍ (2-3) × 10¹¹cm^-3. The structure includes a series connection of a GaAs Schottky diode as D₁, and of a GaAs PiN diode as D₂. The donor concentration in the base region of the Schottky diode N_d, is about (2-3) × 10¹⁵cm^-3, and the concentration N,, in the i-region of the PiN diode is less than 5 × 10¹¹cm^-3.

Equation system (23) allows the calculation of the parameters of controlled capacitors and to design diodes for use as in such controlled capacitor devices. Figure 12 demonstrates an example of a grapho-analytic calculation of a C-V characteristic for two typical reverse I-V characteristics of a diode D₁: for a "soft" characteristic (1), and for a "hard" one (2), in which the I_mii, value is reached only at the start of the avalanche multiplication. V_min and the slope ΔC/ΔV are smaller for the diode with the "soft" I-V characteristic than for the "hard" one. It is clear from the previous analysis that the smaller the differential resistivity of the reverse I-V curve of diode D₁, the higher will be the slope ΔC/ΔV. The maximum slope can be obtained when the switching condition (i.e., when I = I_min), is reached at avalanche breakdown, where the slope of the I-V characteristic is maximum. The I_min value is the same for both the "soft" and the "hard" diodes D₁, because their V_min values coincide. This is clear and is a conclusion from the expressions describing the theoretical model of this capacitor. The I_^ values are different and I_max1 > I_max2. This is also in agreement with the model, but needs some qualitative explanation. The difference between the I_max values is due to the difference in the C_max values. This difference is due to the decrease of the capacitance of diode D₁ with increasing applied voltage. In Figure 12 one clearly sees that for C_t1 = const, C_max1 = C_max2 and I_max1 = I_max2. To increase C_max/C_min at a given voltage, the diode D₁ has to be chosen with some higher "zero capacitance" and also with a weaker dependence of C„ on V. At the same time I^ has to be lower than I_lim.

It is well known that the irradiation of a PN junction with visible light or with other kinds of radiation generates excess electron-hole pairs, the number of which, which can significantly exceed the equilibrium concentration, depends on the parameters of the radiation and of the PN junction. In a reverse-biased PN junction, radiation can increase the generation recombination current by many orders of magnitude.

This process makes it possible to design and fabricate a capacitor which is controlled by light or other forms of radiation. In fact, the result is still a current controlled capacitor, as described above, with the control current being changed through the agency of incident radiation. In the case of a current controlled capacitor described above the reverse current of diode D₁ was independent of all external influences except temperature and the "dark" I-V characteristics were completely determined by the construction and nature of the diode. In contrast, in the case of the light, or radiation, controlled capacitor, one can control the I-V characteristics of diode D₁ through a rather wide range by irradiation, and therefore control the capacitance of the device. The power of the radiation needed for the control is rather small.

Figure 13 illustrates the grapho-analytical calculation of the C(V) dependence on irradiation. C(V)_min is determined by the "dark" reverse I-V characteristics of diode D₁, and C(V)_max is determined by the reverse current of diode D₁ under irradiation. The more intense the radiation, the higher C(V)_max. For a sufficiently high intensity (high reverse current), the C_max value is, as in the case of current controlled capacitance, limited by the depletion capacitance of diode D₁ [C_t1(V)]. In alternative embodiments according to the present invention it is possible to fabricate hybrid devices which include two diode devices connected in series. In the construction of two diodes connected in series the control of the capacitance of diode D₂ is provided by the reverse I-V characteristics of diode D₁ (Figure 11a). The conditions C₁(O) » C₂(0) and I(V_min)₁≤ I_min.2 have to be fulfilled. The lower the reverse current of diode D₁, i.e., the higher its differential resistivity (ΔV/ΔI) and the higher

V_min. V_min is limited by the breakdown voltage of diode D₁: V_min≤ V_BR1.

As diodes D₁ and D₂, one could use, for example, the usual silicon diodes, but, as explained above, these diodes suffer from the drawback that a rather high ratio of areas A₁/A₂ (about 100 or higher) is required, and that they have rather high reverse currents. The high A₁/A₂ ratio requirement can be reduced by using as diode D₂ a GaAs PiN diode with a carrier concentration in the i-region which is much lower than that in the N region of diode D₁. In this case, both C_min and C_max/C_min can be changed by changing A₂ and/or the thickness of the i-region.

As diode D₁ one may use Schottky diodes, PN diodes or PiN diodes. Schottky diodes have a larger zero capacitance, but a rather low reverse voltage. For example, silicon Schottky diodes are mostly designed with reverse voltages below 60V. The reverse current of such diodes is rather high, about tens or hundreds of microamperes, which decreases V_min significantly, to a few volts or tenths of a volt, therefore making them unusable in certain applications.

More attractive is the use of GaAs Schottky diodes, which can now be fabricated with a reverse voltage of 200-300V and with reverse currents below one microampere. The common disadvantage of all Schottky diodes is a strong dependence of the capacitance of the reverse-biased diode on the applied voltage (Figure 14):

C(V)_D1⋍ C(O)_D1 V^-1/2 (26) Therefore, at an applied bias of only 100V the capacitance of a Schottky diode decreases by about 10 times from its zero-voltage value.

PN junction diodes can be fabricated with significantly higher reverse voltage and lower reverse currents than those of Schottky diodes. It is possible also to fabricate diodes with a linear doping profile and consequently with a weaker C(V) dependence (Figure 14):

C(V)_D1⋍ C(O)_D1 V^-1/3 (27)

The most promising device for use as diode D₁ is a GaAs PiN diode. In this case,

C(V)_D1⋍ C(O)_D1 V^-1/k (28) where k = 6-12 (Figure 14).

When a PiN diode is, in addition, used as diode D₂, the C_max/C_min value can be obtained from the relationship:

C_max/C_min⋍ C(O)_D1/C(O)_D2⋍ A_D1W_i2/A_D2W_il (29) and the C(O)_D1 and C(O)_D2 values from:

C(O)_D1 =∈∈_oA_D1/W_il (for GaAs C(O)_D1 = 10^-12A_D1/W_il)

C(O)_D2 =∈∈_oA_D2/W_i2 (for GaAs C(O)_D2 = 10^-12A_D2/W_i2)

where A_D1 and A_D2 are the areas of the PiN diodes, and W_i, and W_a are the thicknesses of their respective i-regions. A detailed model of a device with a GaAs PiN diode as diode D₂ is presented below.

The simple series connection of two diodes shown in Figure 11 does not allow the control of V_min because its value is determined mostly by the parameters of diodes D₁ and D₂ and, in particular, mainly by the reverse I-V characteristics of diode D₁. If the diodes are fabricated in a package which protects the rectifying elements from any external influence, the temperature will be the only factor which can influence V_min. It is well known that the reverse current grows exponentially with temperature, so the V_min stability will be determined mainly by the temperature stability of the reverse I-V characteristics of diode D₁. Much more attractive is the control of C(V) by external factors, for example, by light. Possible construction variants are shown in Figures 15 and 16, where the diode D₁ is shunted by a light sensor, for example, by a photoresistor or by a photodiode.

If one chooses diodes D₁ and D₂ and photoresistor R_H1 or photodiode

D_H1 so that without illumination the current through diode D₂ is lower than I_min over the entire voltage range, while under illumination the current is higher than I_min, then it is possible to control the capacitance of the circuit by illumination (Figure 17). By selecting the moment of the light impulse relative to the V(t) characteristic, and the intensity of illumination, one can control the V_min and C_max/C_min values.

As mentioned above, the main condition for V_min > 0 is that the value of the current through diode D₂ be lower than I_min at V_D1 < V_min. This condition is rather difficult to obtain in a reversely-biased diode D₁. If the reverse current of diode D₁ is higher than I_min, it is possible to change the current through D₂ by a shunt resistor R₂ (Figure 18), which is selected so that the current through D₂ up to an applied voltage V_min will be lower than I_min. A lower R₂ value leads to a smaller current through diode D₂ and to a higher V_min.

Using a photoresistor (R_H2) or a photodiode (D_H2) as a resistor R₂

(Figs. 19, 20), it is possible to control the C_max/C_min value by illumination. In this type of circuit, in contrast with that of Figure 17, an increase in the illumination intensity will decrease the current through diode D₂ and consequently the capacitance. If, without illumination, the current through D₂ is Imax and the capacitance is Cmax, then under illumination of an intensity H_max, the current through D₂ will decrease to l_min, and consequently C(O) will decrease to C_min (Figure 21).

In a preferred embodiment according to the present invention, a controlled capacitor is based on a GaAs PiN diode and a Schottky diode or, alternatively, on two GaAs PiN diodes. State-of-the-art technologies (MBE, MOCVD, and the like) make it possible to fabricate PiN silicon diodes having i-layer doping concentrations of not less than (1-5)×10¹³cm^-3, and GaAs diodes with a doping concentration of not less than 10¹⁴cm^-3 in an i-layer of a few microns in thickness.

It was shown above that the doping concentration is the main determinant of the C_min and C_max(V)/C_min(V) values. To achieve acceptable values of C_max/C_min in diodes having a relatively high carrier concentration in the low-doped region, a rather high ratio of junction cross-section areas A₁/A₂ of diodes D₁ and D₂ is required, which constitutes a major drawback in many applications.

In our copending PCT application (PCT/US93/xxxx), which is incorporated by reference in its entirety for all purposes as if fully set forth herein, is disclosed a novel GaAs PiN layer growth technology which makes it possible to fabricate diode structures having a carrier concentration in the i-region (N_d - N_a)_i of less than 5 × 10¹¹cm^-3. At the same time, the i-region thickness can be controlled from about 3 to 100μm. These structures open up new possibilities for the design of controlled capacitors according to the present invention.

A sketch of the electric field distribution and of the depletion layer propagation in a PiN structure with a near-fully compensated W_rwide ilayer is shown in Figure 22. If (N_d - N_a)_i is sufficiently small, the calculated thickness of the depletion region in the i-region, x_i, under zero bias is much larger than W_i. In this case the value of the capacitance C, under zero bias is determined mainly by W_i. The assumption is made that in these PiN structures the P-i and i-N junctions are abrupt and that N_a and N_d in the P and N regions, respectively, are much higher than (N_j- N_a)_i. These assumptions allow one to neglect the expansion of the depletion region into the P and N regions under reverse bias (x_P and x_N in Figure 22). Under small forward bias the calculated depletion width x_i(V₂) decreases (but still remains larger than W_i), however the changes are very small. From the forward bias value corresponding to x_i⋍ W_i, C_t begins to grow because the width of the depletion region is still not bound by the i-region. For this type of PiN diodes, C_t is given by Equation (30a,b):

C_t(V) = C_t(W_i) =∈∈_oA/W_i, when x_i(V) > W_i (30a) C_t(V) = C_t(x_i) =∈∈_oA/x_i(V), when x_i(V) < W_i (30b) where

x_i(V) = [2∈∈₀(Ψ-V)/q(N_d-N_a)_i]^0.5 (30c)

From Equations (30a-c) and experimental measurements of C_t(O), one can extract W_i and estimate the maximum (N_d-N_a)_i value. Figure 23 shows the dependence of C_t(O) on (N_d-N_a)_i, calculated by using Equations

(30b,c) at zero bias (V = 0) and at room temperature (T = 300K). The dotted lines show experimentally measured C_t(0) values of two diodes with different W_i (W_i,l ⋍ 70μm, W_i,2⋍ 17μm). This plot shows that the calculated x_i(O) values corresponding to the measured C_t(O) are close to the measured W_i values, and that the condition C_t(O)_exp = C_t(O)_calc will be fulfilled for (N_d-N_a)_i ⋍ 2.5 × 10¹¹cm^-3 for W_i,l and for about 4 × 10¹²cm^-3 for W_i,2.

Because (N_d-N_a)_i is, in principle, independent of W_i one can conclude that:

(1) for W_i, < W_i < W_i,2, (in the above case up to about 70μm) the maximum concentration in the i-region is below 5 × 10¹¹cm^-3;

(2) from Equations (30b,c) one obtains that x^O),,_^ ≥ 70μm for(N_d - NJ,.≤ 5 x 10ⁿcm-³;

(3) for all W_i≤ x_i(O)_max the W_i value can be obtained from the expression:

W_i⋍∈∈_oA/C_t (O)_exp (31)

Figure 24 illustrates the measured dependence of C_t(O) on PiN diode areas for three diode sets, each set having a different W_i. Within each set W_i is constant. The lines represent a regression fit according to the dependence C_t(O) ~ A (Equation 30a). Inserting the regression parameters into Equations (31) one obtains W_i values of 71, 27 and 17μm, which are close to thicknesses measured by other methods. This result supports the validity of both the condition x_i(O) > W_i and the assumption that (N_d-N_a)_i is independent of W_i.

A very important practical conclusion from these measurements is that the ability to grow thick (up to 100 μm) PiN layers with such a low (N_d - N_a)_i allows the fabrication of diodes with a relatively large (about lmm²) area but with a very small (1 pF and smaller) capacitance. This is very important for the design of high-frequency semiconductor capacitors, because one can use special high-frequency packages and thus easily avoid the normal stray capacitance due to connections. At the same time the fabrication technology of these small-capacitance structures is much easier than that in existing technologies for making low-capacitance silicon structures.

In an analogous way, the diffusion capacitance of a GaAs PiN structure is given by:

C_d = qτI/kT for W_i/L>1 (32a)

C_d = (qτl/kT) × W_i/2L for W_i/L « 1 (32b) where τ is the carrier lifetime, and L is the diffusion length. These equations are valid up to a maximum current density of about 10^-2A/cm² when (N_d - N_a)_i is about 5 × 10¹¹cm^-3.

The total capacitance of a diode is given by:

C(I) = C_t(V₂) + C_d(I) (33) where C_t(V₂) is the depletion capacitance under forward bias, Equations (30), and

V₂ = (kT/q) ln[(I/A)/j₀+1]

and

J_o⋍ q(Di)^0.5p_i/(τ_i)^0.5 where D_i, p_i and τ_i are, respectively, the diffusivity, equilibrium hole concentration and hole lifetime respectively in the i-layer.

Figure 25 shows the measured dependence of the total PiN diode capacitance C(I) on forward bias, and Figure 26 shows the calculated dependence of C(I) and its components on the forward current (for an area of 0.3cm²). The diffusion component C_d is given by curve 1; the depletion component C_t was calculated for two conditions: (a) - for W_i > x_i(V) (curve 2), and (b) - for W_i = 20μm (curve 3).

For condition (a), C(I) (curve 4) is determined mainly by C_t up to a certain current, and grows only slowly with increasing current. Above I = I_min(I⋍ 10^-6A), C(I) increases much faster, and the dependence becomes almost linear due to the dominance of C_d (curve 1). For condition (b) C_t is independent of the current (curve 3) up to ~10^-3A, and should be calculated from (30a); C(I) (curve 5) is then given by:

C(I) = C_t(W_i) + C_d(I) (34)

For illustration, curve 6 in Figure 26 shows the experimental C(I) dependence of a PiN structure with parameters similar to those used in the calculation. The curve was obtained by converting V values into I values using a measured I-V characteristic. There is an excellent fit with the theoretical "case (b)" curve.

Diode D₁ can be a diode with an abrupt PN junction, a linearly graded PN junction, a PiN diode or a Schottky diode. The total capacitance of the two diodes in series C(V) is calculated using Equations (23), (30) and (33). For W_i < x_i(V) (see Equation (34)),

1/C(V) = 1/C₁(V)+1/C₂(V) = l/C_tl(V)+1/[C_t2(W_i)+C_d2(I)] (35)

One can discuss as an example the calculation of the capacitance of a controlled capacitor consisting of a GaAs PiN diode D₂ and a reversely connected diode D₁.

1) Assuming as a main condition:

C_t1(V) = mC₂(O) where m > 1 (36a) In this case in Equation (35) C₂(0) = C_t2(W_i), i.e.,

C_t1(V) = mC_t2(W_i) (36b)

The multiplier m can be chosen arbitrarily starting with the suggested ratio C_max/C_min at a given bias. 2) C(V)_min is obtained from the condition that at I_min, C_d2 < C_t2, i.e.,

C_d2(I_min) = α × C_t2(W_i), where 0.2≤ α≤ 1 (37)

From Equations (35), (36b) and (37) it follows that:

C(V)_min = [m(1+α)/(1+α+m)]C_t2(W_i) (38) Taking m = 10 and α = 0.2 one obtains CO(V)_min = 1.1C_t2 (W_i).

3) I_min is obtained from Equation (37) by inserting the respective values of C_d2(I_min) and C_t2(W_i) into Equations (30a) and (32a):

qτI_min/kT = α (∈∈₀A₂)/W_i

or

I_min = α(kT/q)(∈∈₀ A₂)/(τW_i) (39)

Equation (39) shows that I_min decreases when τ and/or W_i increase. For a PiN diode with parameters: W_i = 20μm, τ = 150ns, A₂ = 0.1cm², m = 10 and α = 0.2, I_min = 1.6 × 10^-6A and C(V)_min = 60pF.

4) C(V)_max is determined by the condition that the total capacitance of diode D₂ has to be much greater than the depletion capacitance of diode D₁ at a given bias:

C_d2(I_max + C_t2(W_i) » C_t1(V), i.e.,

C_d2(I_max) + C_t2(W_i) = β C_t1(V), where β » 1 (40)

From Equations (35), (36b) and (40) one gets:

C(V)_max = [mβ/(1 + β)]C_t2(W_i) (41)

Assuming β = 10 and m = 10, one obtains C(V)_max⋍ 9C_t2(W_i), and for the above example C(V)_max⋍ 480pF. 5) I_max can be extracted from Equations (36b) and (40):

C_d2(I_max) + C_t2(W_i) = βmC_t2(W_i)

(qτI_max)/kT = (βm-1)C_t2(W_i)

I_max = (βm-1)(kT/q)(∈∈₀A₂)/τW_i and since βm»1

I_max⋍ βm(kT/q)(∈∈₀A₂)/τW_i (42)

By comparing Equations (39) and (42), it can be seen that I_max and I_min are related through α, β and m:

I_max = (βm/α) I_min (43) For α = 0.2, β = 10 and m = 10 and for the diode parameters chosen above, one gets I_max⋍ 10^-3A, and j_max = I_max/A₂⋍ 10^-2A/cm² which is below the j_lim value for the diffusion capacitance.

6) V_min and V_max are obtained from the reverse I-V characteristic of diode D₁, inserting the I_min and I_max values:

I_min = A₁ x j(V_min) (44a) I_max = A₁ x j(V_max) (44b)

Figure 27a shows examples of experimental I-V characteristics of different diodes D₁ with different values of differential resistivity R_d in the V_min - V_max range; Figure 27b shows the measured C-V characteristics of the same capacitors. The V_min value is dependent on the differential resistivity at V > V_min, and as a first approximation can be written:

V _min = V_max-(I_max-I_min)R_d (45)

From Equation (45) it follows that the smaller is R_d, the closer is V_min to V_max. Considering that I_max » I_min, one gets:

V_min = V_max-I_maxR_d (46) or:

ΔV = I_maxR_d (47)

Now

ΔC/ΔV = [C(V)_max - C(V)_min]/(V_max-V_min) (48) and using Equation (47)

ΔC/ΔV = [C(V)_max - C(V)_min]/I_maxR_d (49)

Equation (49) shows that the slope of the C(V) characteristic increases with decreasing R_d. It was mentioned above that it is possible to control the size of the reverse current in diode D₁ between I_min and I_max through the influence of radiation at V < V_min. In this case the reverse current will depend on the intensity and the energy of radiation, and on the design and parameters of D₁ (Figure 28).

As the source of radiation which leads to the growth of the reverse current by the generation of electron-hole pairs one can use visible infrared or ultraviolet light, γ- or X-rays, nuclear radiation, etc. Generation of electron-hole pairs, can also be induced by increasing the temperature of diode D₁. Controlled capacitors can therefore be very attractive candidates for sensors of radiation or temperature. From a radiation sensitivity viewpoint, the most effective controlled capacitors will be composed of diodes made from semiconductors with a direct zone structure, particularly GaAs.

7) The parameters of diode D₁ are obtainable from (see Equations (26),(27),(28)):

C_t1(V) = C_t1(0) × (V_max)^-1/k (50) where k = 2 for abrupt PN junctions, k = 3 for graded ones, and k > 3 for PiN structures.

Inserting the C_t1(V) value from Equations (36b) into Equation (50) one obtains the expected value of C_t1(0):

C_t1(0) = mC_t2(W_i) × (V_max)^1/k (51)

Equation (51) shows that the expected "zero" capacitance of diode D₁ increases when k decreases. If a PiN diode is used as diode D₁ then:

C_t1(0)⋍ C_t1(W_i,1) = (∈∈₀A₁)/W_i,1 (52) and combining Equations (51) and (52),

(A₁/A₂)(W_i,2/W_i,1) = m × (V_max)^1/k, where k⋍ 6-12 (53) When a Schottky diode or a diode with an abrupt PN junction is used as diode D₁,

C_t1(0)⋍ A₁[q∈∈₀N₁/(2ψ)]^0.5 (54) and from Equations (51) and (54),

A₁[q∈∈₀N₁/2ψ]^0.5 = (m∈∈₀A₂/W_i,1) × (V_max)1/k or

(A₁W_i/A₂) × [qN₁/(2∈∈₀ψ)]^0.5 = m × (V_max)^1/k (55)

The assumption is made in all the calculations that ψ = IV.

Equations (53) and (55) make it possible to calculate the parameters of diode D₁ (A₁, W_i,1, N₁), starting with the previously assumed or calculated parameters of diode D₂: W_i,2, A₂, m and V_max. During calculation one need merely keep the N, and W_i,l values in a range which guaranties that the breakdown voltage of diode D₁ is higher than V_max, i.e., V_BR,1≥ V_max. For our example, (D₁-Schottky diode; D₂-PiN diode with m = 10, W_i,2 = 20μm, A₂ = 0.1cm²) and for V_max = 100V, one obtains N₁ = 2 × 10¹⁵cm^-3 (V_BR⋍ 140V > V_max) and an area A₁⋍ 0.4cm².

Table 1 gives calculated parameters of a GaAs controlled capacitor composed of a Schottky diode under reverse bias as D₁, and of a PiN diode under forward bias as D₂, connected in series.

Table 1

Schottky diode (D₁) parameters

A₁ 0.1 cm²

C(O) 3900 pF

N_d 2 × 10¹⁵ cm^-3

I_mix 2 × 10^-6 A

I_max 10^-3 A

PiN diode (D₂) parameters

W_i 2 × 10^-3 cm

(N_d-N_a)_i < 2 × 10¹¹ cm^-3

A₂ 0.1 cm² C_t(W_i) 50 pF

Main parameters of the capacitor

C_min 60 pF

C_max 500 pF

C_max/C_min 8.3

V_max 50 V

Controlled capacitors according to the present invention may be fabricated in integrated form. The construction of such a controlled capacitor composed of a Schottky diode as diode D₁, and of a forward-biased PiN diode as a diode D₂ is illustrated in Figure 29. What follows is a brief description of the fabrication steps.

Metallic layers are deposited on an epitaxially grown P⁺PiN structure having a defined i-region thickness, creating an ohmic contact with a specific contact resistivity of about 10^-6 - 10^-7 ohm x cm² on the highly-doped P⁺ substrate, and a Schottky barrier on the low-doped (=* 5 x 10¹⁵cm^-3) N-layer. The breakdown voltage of such a Schottky barrier is about 40-70V. The Schottky barrier is reverse-biased and the PiN diode is forward-biased. The reverse current of the Schottky diode is composed of volume and surface components. The surface component can be reduced by special treatment and protection of the side surface.

The C_min value is controlled by the thickness of the i-region of the PiN diode and by the cross-section area (equal in both D₁ and D₂, i.e., A₁ = A₂). Figures 30-31 demonstrate experimental Schottky diode I-V and C-V characteristics of such structures having different W_i and A.

The light control can be provided by direct irradiation of the side surface of the Schottky diode. The current generated by light in the near-surface region is high enough for capacitance control. Figure 32(a) shows experimental C-V characteristics of a light controlled capacitor (LCC) under various light intensities (H₁ < H₂ < H₃). A regular microscope illumination lamp was used as a light source, and voltage changes led to different light intensities. Figure 32(b) shows the dependence of the reverse current of the Schottky diode on light intensity. To improve the light action effectiveness, light penetration through the Schottky barrier area is provided by etching the metallization, so that the contact has the shape of a metal grid or "fingers".

Another variant of an integrated controlled capacitor design is based on the P⁺PiNP⁺ structure shown in Figure 33, which includes a back-to-back connection of a P⁺N and a PiN diode. The P⁺N junction (D₁) can be made by an acceptor atom, such as Zn, diffusion into the N region of a GaAs P⁺PiN structure, or by the epitaxial growth of a PMayer, for example by methods such as LPE, CVD, MBE or MOCVD, on N. Using diffusion, it is possible to get a more linear junction with a higher breakdown voltage of diode D₁. Etching the metallization and the P-layer in D₁ to open windows will improve the efficiency of light control.

Instead of a PMayer in D₁, one can form a transparent, conductive, Schottky barrier, using oxides such as SnO_x, InO_x and In_xSn_y0₂ (Figure 34). This variant creates a Schottky diode (D₁) in reverse bias connected to the forward-biased PiN (D₂) diode. Another variant uses a PN heterojunction in D₁ (Figure 35). The use of a semiconductor with a wider band gap, such as GaAsP or GaAlAs, as the P-layer of diode D₁, widens the range of usable wavelengths and reduces the absorption in the P region, thereby improving the light sensitivity of the capacitor.

The controlled capacitor can also be fabricated on a N⁺ substrate (Figure 36). First, a PiN layered structure is grown, e.g., by LPE. Either an ohmic contact or a Schottky barrier is then deposited on the N-layer. In the first construction (Figure 36(a)), the characteristic of the capacitor is determined by the reverse I-V characteristics of the N⁺P junction. In the second (Figure 36(b)) the N⁺P (D/) and the Schottky (D₁") diodes are both reverse-biased, and connected in series, and therefore the voltage held by D₁' + D₁" is larger than in the first case (Figure 36(a)).

Controlled capacitors can also be designed in the form of a matrix arrangement, as shown in Figure 37. The structure is separated into elementary cells, each of which includes a forward-biased PiN diode in series with a reverse-biased Schottky diode (Figure 37(a)) or a reversebiased PN junction (Figure 37(b)). For light control, windows are etched in the metallization of each cell. In general, all the previously discussed variants (Figs. 29, 33-36) can be realized in a matrix form. The main advantage of such a form is the added possibility of controlling the capacitance of a separate cell, or of a group of cells, by appropriate irradiation.

A matrix form can also be used to obtain large values of capacitance (C_min). For this purpose the cells of the matrix must be connected in parallel with the common cathode. A further increase in the total capacitance may be achieved by the parallel connection of a number of matrices to a common metallic anode (Figure 38). In this way one can design a controlled capacitor having relatively high C_min and C_max.

One can also consider an inverted construction (Figure 39), i.e., a design having a forward-biased Schottky diode as D₂ and a reverse-biased PiN diode as D₁. From the previous analysis it follows that a condition for C_max/C_min. > 1 is that C_PiN(V) > C_Sch(0). For this construction a system of equations can be written in the form

C(V) = [C_PiN(W_i) × C_t,Sch(V₂)]/[C_PiN(W_i) + C_t,Sch(V₂)]

V₂ = (kT/q)ln[I_PiN/(j_o,SchA₂) + 1] (55)

I_PiN = A₁ × j₁(V)

This is in principle a different situation than the one encountered before where the capacitance of a forward-biased Schottky diode was controlled by the reverse current of a PiN diode. In this circuit, the diffusion capacitance is absent, and all C(V) changes are caused by the changes in the depletion capacitance of the forward-biased Schottky diode. The advantage of this circuit is high operation rates, because the relaxation time of the depletion capacitance is less than Ins, as shown below. In addition, V_min for this construction will be higher because of the high breakdown voltage of PiN diodes, and the reverse current can be significantly lower than I_min up to high biases.

One can estimate the ratio of the areas A₁/A₂. When

C_PiN⋍ (∈∈₀A₁)/W_i⋍ 10^-12A ₁/W_i

and

C_Seh(0) = A₂ (q∈∈₀N_d/2ψ)⁰-⁵ = 2.7 × 10^-12A ₂ (N_d)^0.5 and ψ=1 then

C_PiN/C_Sch(0) = 4 × 10³/[W_f(N/⁵] × A₁/A₂ (56)

The ratio C_PiN/C_Sch(0) increases with decreasing W_i and/or N_d, and by increasing A₁/A₂. Assuming C_PiN /C_Sch(O) = 10, N_d = 5 × 10¹⁵cm^-3 and W_i = 20μm, one obtains A₁/A₂⋍ 350, i.e., the area of the Schottky barrier has to be about 350 times smaller than that of the PiN diode. This result was obtained experimentally with a dot barrier contact to the low-doped (⋍ 5 × 10¹⁵cm^-3 ) N base of a PiN diode structure with an area of 3 × 3mm² (Figure 40).

One of the interesting applications of such a configuration is as a high-voltage, high speed, light-controlled capacitance matrix, the design of which is shown in Figure 41. The reverse-biased PiN structure is a common diode D₁ for hundreds of forward-biased Schottky diodes. Windows (1) through the N-layer are etched down to the i-region. Some windows are then filled by an opaque dielectric compound (2) to electrically isolate the diodes, and to protect the spaces between the matrix elements from light. The light absorbed in a window (1) generates electron-hole pairs in the i-region which leads to the growth of the reverse current I_rev of the PiN diode and consequently to the growth of the capacitance of the matrix cell through which the current is passed. If the "dark" reverse current of the PiN diode in the matrix is lower than I_min, then by irradiation of the same cell, it is possible to raise the capacitance of this cell up to the capacitance of the PiN structure, that is, up to the capacitance of the entire matrix. If the matrix (i.e., PiN diode) area is A; = 10cm², the area of a single cell (that is, a Schottky diode) has to be smaller than 1000mm²/350⋍ 3mm² (see calculation above). Starting with the dimensions given in Figure 41, one obtains A₂ = 0.75mm², C_Sch(0) ⋍ 150pF and C_Pin⋍ 5000pF, i.e., Cp_iN/C_Sch(O)⋍ 35.

The most difficult technological problem in the fabrication of such a matrix is to ensure the homogeneous distribution of the reverse current among all the cells, and to guarantee an I_rev value below I_min for each cell.

A hybrid design of a controlled capacitor (that is, separate back-to-back D₁ and D₂ diodes) is preferable when it is necessary to connect two diodes having different areas, or whenever it is impossible technologically to fulfill the I_mix and V_min conditions using an integrated design. A hybrid design also enables electrical connection to the "middle point" between the diodes, which can be useful for some applications, and/or connection of sensors or other current regulation elements for capacitance control. In a hybrid construction the elements can be connected by a conductive glue or by soldering. A few illustrative examples of CCC's and LCC's in a hybrid design are shown in Figures 42, 43 and 44.

Figure 45(a) shows the reverse I-V characteristics of a Schottky diode of 3x 3mm² area with a comb-shaped barrier metallization of an active area A₁ of 0.04cm². The base doping concentration is about (1-2) × 10¹⁶cm^-3 and the breakdown voltage about 30V. Light irradiation by a microscopic light source increases the "dark" reverse current by up to four orders of magnitude. Figure 45(b) shows the measured C-V characteristics of a hybrid LCC composed of this Schottky diode and of a PiN diode with a 0.36cm² area and W, = 20μm. Curve 1 is the "dark" C-V of the LCC, curve 2 is the "dark" C-V of the Schottky diode, and curve 3 shows how the LCC capacitance switches between these two when the light is switched on and off.

Figures 46(a) and 46(b) show I-V and C-V characteristics of a similar LCC, but having an active area of the Schottky diode of about 0.07cm², and therefore C_max values also higher than in Figure 45.

The hybrid construction is the only one possible for application in high power converters, where large capacitances have to be controlled at high voltages. In this case a number of capacitors are connected in parallel, as shown in Figure 47.

The dynamic characteristics of a controlled capacitor are determined mainly by the time constants of the loading and unloading of the various capacitances in the device. One can estimate the operation rate of a controlled capacitor composed of two "back to back" diodes connected in series. The time constant of such a capacitor is determined to a first approximation by two components: 1) τ_Ct,R⋍ RC_t - the loading (unloading) constant of the depletion region capacitance, where R is the series resistance of the contacts and of ohmic resistances of various regions of the structure; and 2) the loading (unloading) constant of the diffusion capacitance τ_d.

R can be written as

R⋍∑_k (ρ_kl_k/A_k) +∑_s (ρ_s/A_s) (57) where ρ_k represents the ohmic resistivities of the layers of the semiconductor structure, l_k represents their thicknesses, ρ_s is the specific contact resistivity [ohm × cm²], A_k are the areas of the layers and A_s are the areas of the contacts.

The τ_{Ct ,R} value for a GaAs PiN diode connected in series with a reverse-biased diode can be estimated from the following arguments. Assuming that: (1) diodes D₁ and D₂ have equal areas; and (2) contact resistivities can be neglected, one obtains: τ_Ct,R = R(C_max-C_min)⋍ mC(W_i)∑_k (ρ_k1_k/A)

or

τ_Ct,R⋍ (m∈∈₀/W_i)∑_k ρ_k1_k (58)

The time constant for a Schottky diode connected to a PiN diode in a integrated construction (Figure 29) is:

τ_Ct,R = m∈∈0/(W_iq)[1_N/(μ_Nn_N) + 1_P/(μ_pp_p)] (59)

Assuming that 1_N = 1_p = 100μm, n_N ⋍ p_p = 10¹⁵cm^-3, μ_n = 8000V/cm²s, μ_p = 400V/cm²s, m(V)⋍ 10 and W_i = 20μm one obtains τ_Ct,R ⋍ 10^-9s = 1ns. If diodes D₁ and D₂ have equal areas, from Equations (58) and (59) it follows that τ_Ct,R is independent of the diodes area.

τ_d can be obtained to a first approximation from:

W_i ²/(2D) |_Wi/L<1 ≤τ_d < τ_i |_Wi/I>1 (60) where τ_i is the carrier lifetime in the i-region of the PiN diode. Assuming that τ_i⋍ 150ns and W_i is in a range between 5 and 100μ, one obtains a τ_d value between 10 and 150ns. Comparing the two relaxation times (time constants) one sees that the relaxation of the diffusion capacitance is the slower process. The relaxation time depends also on the frequency of the controlling light source. This is shown qualitatively in Figure 48. The faster is the current reaction of diode D₁ to the irradiation change, the closer will be the relaxation time to the value determined by the time constant of the diffusion capacitance τ_d. From a maximum operation rate viewpoint, the requirement for the frequency of the light source, such as light diodes, lasers, and the like, can be formulated from the condition that the time constant of the light intensity rise τ_H (~t_H) be much smaller than τ_d (⋍t_d). If, for example, τ_H⋍ 0.1 τ_d, then Ins≤ τ_H≤ 15ns.

The energy accumulated in a capacitor by the charging is

ΔCxV72 [J]

where ΔC = C_max - C_min. The power returned to an external load R during unloading is:

P⋍ ΔCxV²/(4t_RC) where t_RC is the unloading time of the capacitor to an R, (t_RC⋍ RΔC + τ_d). If RΔC « τ_d, then the unloading time is determined mainly by τ_d (Figure 49). The limit power of the capacitor unloading is:

P_lim =ΔCxV²/4t_d (61)

The power averaged over a period (see Figure 49 ) is:

P_av = ΔCxV²/4T⋍ ΔC x (V²/4)f where f is the frequency and T is the period of the signal.

In the limit case T_min⋍ 2t_d, and

P_av,lim = ΔCxV²/8t_d = ΔC x (V²/4)f_max (62) where f_max⋍ 1/(2t_d). For t_d⋍ 100ns, f_max = 5MHz.

Devices according to the present invention may find application in a wide variety of applications, all of which are intended to fall within the scope of the present invention. Three possible areas of controlled capacitor applications are: (1) LCR contours and amplifiers; (2) sensors and detectors; and (3) power converters. Figure 50 demonstrates an idea for converting an alternating voltage into an alternating capacitance. Because

ΔC⋍ dC/dV x ΔV,

the higher the slope of the C-V characteristic dC/dV, the smaller has to be the ΔV value to obtain the expected ΔC.

ΔC_max = (C_max-C_min)⋍ dC/dV x ΔV_max

ΔC_max and dC/dV are the parameters of a controlled capacitor.

Figure 51 shows two different circuits using an LCC. The growth of the capacitance as a result of irradiation takes place practically under a constant bias on the controlled capacitor, because ΔV⋍ 0.2-0.4V. ΔC = C - C_min is proportional to H - H_min = ΔH, where H is the intensity of radiation. ΔC_max⋍ C_max - C_min ~ Δ H_max. The slope of a characteristic is dC/dV⋍ ΔC/ΔV ~ ΔH

(dC/dV)_max⋍C_max/ ΔV ~ ΔH_max

In an experimental GaAs LCC the ΔC/ΔV value reaches 2000pF/V (Figure 28c). In the construction demonstrated in Figure 51b, a photodiode, photoresistor, and the like, can be used as the receiver of radiation. The criterion for diode D₂ to be used as a receiver is that the current through the diode without irradiation has to be below I_min, while under irradiation it must reach I_max at some defined intensity H_max. It is also possible to control the capacitance by controlling the charge in diode

D₂ using a separate current source V, as shown in Figure 52. ΔC ~ V;

ΔC_max = (C_max-C_min) ⋍ ΔV'_max. The maximum frequency will be determined by the relaxation time of the diffusion capacitance (τ_d) of diode D₂, and is in the range of 5-20 MHz.

For power electronics applications the preferred embodiments of controlled capacitors appear to be the light controlled capacitors. The main factors determining the usefulness of these capacitors in power electronics are power and voltage. The maximum of average power is given by

Equations (62).

For GaAs PiN diodes, f_max = 5-20MHz, and for f_max = 5MHz one obtains:

P_av,max⋍ 10⁶ΔCxV² (63)

One can use converters as an example of a power system and separate all converters into three groups, first by operation voltage, and then by converted power.

In the case of low-voltage (up to 50V) and low-power (up to 5W) applications, the ΔC value obtained from Equation (63) for 5W and 50V is ΔC = 2000pF. For this voltage/power range the recommended design is the integrated one (Figure 29). The area of such a structure will be about 0.3-0.5cm². The hybrid construction of a GaAs Schottky diode with a reverse voltage above 50V in series with a PiN diode (Figure 43) is also a candidate.

For intermediate power (10-100W), the area of controlled capacitors in this power range has to be between 1-10cm². Intermediate power converters can be fabricated using a parallel connection of structures with areas of 0.3-0.5cm² in an integrated or in a hybrid design (Figures 38, 47).

For high power (above 100W) applications the application of low-voltage capacitors is not advantageous from an economic point of view.

In the case of intermediate-voltage (50-200V) and low-power (up to 10W) applications, a hybrid construction, composed of a high-voltage (up to 200V) Schottky diode and a PiN diode, or of two PiN diodes with different areas and different thicknesses of i-region is the most advantageous. For an applied voltage of 200V and 10W, Equation (63) gives ΔC = 250pF. For a "two PiN diode" design one can calculate the parameters of diode D₁ and see that to obtain the reverse voltage of 200V, an i-region of about 5μm is needed. Assuming the "zero" capacitance of such a diode is about 500pF, one obtains for a bias of 200V ΔC⋍ 250pF and an area of about 0.25cm², i.e., the capacitor needed for 10W power conversion will have an area of about 5 × 5mm.

For intermediate power (10-200 W) capacitors can be made by parallel connection of an appropriate number of low-power capacitors. For example, for 200 W conversion a parallel connection of about 20 10W capacitors is required.

For conversion of power above 200W the application of capacitors of this voltage range is not advantageous at this time.

In the case of high-voltage (200-1000V) and intermediate-power

(about 200 W) applications, for example 1000V, 200W, the ΔC⋍ 200pF. Such a controlled capacitor can be realized through the connection of two

PiN diodes, with diode D₁ parameters of W_i⋍ 20μm (required for reverse bias of 1000V) and A₁⋍ 0.5cm².

For high power (1kW and above) applications converters can be made by parallel connection of hybrid capacitors designed for 200W. For example, for conversion of 10KW, a about 50 elements have to be connected, each with an area of 0.5cm². The total area of such a capacitor will be about 25cm², rather small for this power conversion.

From a "specific power" point of view, that is, for the maximum power converted by one cm² of area, the most advantageous controlled capacitors are high voltage capacitors, because the increase of applied voltage increases the converted power significantly but does not require a significant increase in the area. For example, a capacitor designed for 2KV has about the same dimensions as a 1KV controlled capacitor, but the converted power can reach about 40KW as compared to 10kW. While the invention has been described with respect to a limited number of embodiments, it will be appreciated that many variations, modifications and other applications of the invention may be made.

Claims

WHAT IS CLAIMED IS:

1. A controlled capacitor system, comprising:

(a) a capacitor element; and

(b) a diode element connected in series with the capacitor element, said diode element being forward-biased, the system being further characterized in that:

(i) said diode element has a capacitance which is less than the capacitance of said capacitor element when said diode element is under zero bias;

(ii) the capacitance of said diode element is controlled by varying the forward current through said diode element; and

(iii) the forward current acting to control the capacitance of said diode element is selected such that the capacitance of said diode element is smaller than the capacitance of said capacitor element when the current through said diode element is below a minimum value; and

(iv) the capacitance of said diode element is bigger than the capacitance of said capacitor element when the current through said diode element exceeds a maximum value.

2. A system as in claim 1 wherein said capacitor element is shunted by a device selected from the group consisting of a variable resistor, a reverse-biased diode, a photodiode, a photoresistor and a radiation sensor.

3. A system as in claim 1 wherein said diode element is shunted by a device selected from the group consisting of a variable resistor, a reverse-biased diode, a photodiode, a photoresistor and a radiation sensor.

4. A system as in claim 1 wherein said diode element is shunted by an independent power source.

5. A system as in claim 1 wherein said capacitor element is a reverse-biased diode.

6. A system as in claim 5 wherein said diode element is shunted by a device selected from the group consisting of a variable resistor, a reverse-biased diode, a photodiode, a photoresistor and a radiation sensor.

7. A system as in claim 5 wherein said reverse-biased diode is shunted by a device selected from the group consisting of a variable resistor, a reverse-biased diode, a photodiode, a photoresistor and a radiation sensor.

8. A system as in claim 5 wherein said diode element is shunted by an independent power source.

9. A system as in claim 1 wherein said diode element is a GaAs P⁺PiN diode fabricated on a P⁺ substrate having a carrier concentration in the i-region of less than 10¹²cm^-3.

10. A system as in claim 5 wherein said diode element is a GaAs P⁺PiN diode fabricated on a P⁺ substrate having a carrier concentration in the i-region of less than 10¹²cm^-3.

11. A system as in claim 5 wherein said reverse-biased diode is selected from the group consisting of a Schottky diode and a PN junction diode.

12. A system as in claim 10 wherein said reverse-biased diode is a GaAs P⁺PiN diode with full-area ohmic contact to the N-layer.

13. A system as in claim 10 wherein said reverse-biased diode is a GaAs P⁺PiN diode with an ohmic contact to the N-layer which includes windows in said ohmic contact and in said N-layer down to the i-layer.

14. A system as in claim 5 wherein said reverse-biased diode is a GaAs Schottky diode with full-area contact to the N-layer and said diode element is a GaAs P⁺PiN diode, said reverse-biased diode and said diode element being integrally formed in a single crystal.

15. A system as in claim 5 wherein said reverse-biased diode is a GaAs Schottky diode with contact to the N-layer which includes windows in said Schottky contact and said diode element is a GaAs P⁺PiN diode, said reverse-biased diode and said diode element being integrally formed in a single crystal.

16. A system as in claim 5 wherein said reverse-biased diode is a PN diode with full-area contact to the P-layer and said diode element is a GaAs P⁺PiN diode, said reverse-biased diode and said diode element being integrally formed in a single crystal.

17. A system as in claim 5 wherein said reverse-biased diode is a PN diode with contact to the P-layer which includes windows into said contact and into said P-layer down to said adjoining N-layer, and said diode element is a GaAs P⁺PiN diode, said reverse-biased diode and said diode element being integrally formed in a single crystal.

18. A system as in claim 14 wherein said Schottky diode includes a barrier which is transparent.

19. A system as in claim 16 wherein said reverse-biased diode is a PN heterojunction.

20. A system as in claim 5 wherein said diode element is a GaAs PiN structure grown on a N⁺ substrate and having an ohmic contact to the N-layer, said reverse-biased diode being the N⁺P junction, where said N⁺ portion of said N⁺P junction is said N⁺ substrate, with said reverse-biased diode and said diode element being integrally formed in a single crystal.

21. A system as in claim 5 wherein said diode element is a GaAs PiN structure grown on an N⁺ substrate and having a Schottky barrier with the N-layer, said reverse-biased diode being the N⁺P junction and Schottky barrier, with said reverse-biased diode and said diode element being integrally formed in a single crystal.

22. A system as in claim 5 wherein a plurality of the systems of claim 15 are grown on a single P⁺ substrate so as to be separated from each other by etching down to the P-layer, so as to form an integrated matrix of controlled capacitors.

23. A system as in claim 5 wherein a plurality of the systems of claim 17 are grown on a single P⁺ substrate so as to be separated from each other by etching down to the P-layer of said P⁺PiN diode, so as to form an integrated matrix of controlled capacitors.

24. A system as in claim 5 wherein said reverse-biased diode is a GaAs P⁺PiN diode, said reverse-biased diode being fabricated by growing a GaAs PiN structure on a P⁺ substrate, and wherein said diode element is a Schottky barrier to the N-layer, the cross sectional area of said Schottky barrier being smaller than that of the P⁺PiN diode.

25. A system as in claim 5 wherein a plurality of the structures of claim 24 are grown on a single P⁺ substrate and are separated from each other by etching down to the i-layer of the P⁺PiN structure and Schottky diode having windows in said Schottky barrier and N-layer down to said i-layer.