WO1994023444A3 - Procede de liaison de tranches par oxydation - Google Patents

Procede de liaison de tranches par oxydation Download PDF

Info

Publication number
WO1994023444A3
WO1994023444A3 PCT/US1994/003855 US9403855W WO9423444A3 WO 1994023444 A3 WO1994023444 A3 WO 1994023444A3 US 9403855 W US9403855 W US 9403855W WO 9423444 A3 WO9423444 A3 WO 9423444A3
Authority
WO
WIPO (PCT)
Prior art keywords
bonding
wafers
silicon
bonded
bonding liquid
Prior art date
Application number
PCT/US1994/003855
Other languages
English (en)
Other versions
WO1994023444A2 (fr
Inventor
Jack H Linn
Robert K Lowry
George V Rouse
James F Buller
Original Assignee
Harris Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harris Corp filed Critical Harris Corp
Publication of WO1994023444A2 publication Critical patent/WO1994023444A2/fr
Publication of WO1994023444A3 publication Critical patent/WO1994023444A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)

Abstract

Liaison de tranches à basse température qui utilise un matériau de réaction chimique entre des tranches afin de former une zone de liaison entre deux tranches. Selon certains exemples, des tranches de silicium sont utilisées avec un liquide de liaison oxydant le silicium qui permet également l'introduction de dopants d'insensibilité aux rayonnements et de dopants électriquement actifs en tant que constituants du liquide de liaison. Des tranches de silicium peuvent également être utilisées avec des réactifs solides qui comportent des couches déposées de métal et de polysilicium pour former des zones de liaison siliciée. Des oxydants tels que l'acide nitrique peuvent être utilisés dans le liquide de liaison et un liquide de liaison peut être utilisé en combinaison avec un réactif de liaison solide. Des couches diélectriques sur des tranches de silicium peuvent être utilisées lorsque du silicium supplémentaire est présent pour les réactions de liaison. Des circuits intégrés fabriqués à partir de tranches liées de ce type peuvent comporter des couches enterrées, des dopants d'insensibilité aux rayonnements et des résistances enterrées.
PCT/US1994/003855 1993-04-02 1994-04-01 Procede de liaison de tranches par oxydation WO1994023444A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US042,340 1979-05-25
US4234093A 1993-04-02 1993-04-02

Publications (2)

Publication Number Publication Date
WO1994023444A2 WO1994023444A2 (fr) 1994-10-13
WO1994023444A3 true WO1994023444A3 (fr) 1995-01-12

Family

ID=21921344

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1994/003855 WO1994023444A2 (fr) 1993-04-02 1994-04-01 Procede de liaison de tranches par oxydation

Country Status (1)

Country Link
WO (1) WO1994023444A2 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2726935B1 (fr) * 1994-11-10 1996-12-13 Commissariat Energie Atomique Dispositif a memoire non-volatile electriquement effacable et procede de realisation d'un tel dispositif
US6362075B1 (en) 1999-06-30 2002-03-26 Harris Corporation Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide
JP4030257B2 (ja) * 2000-08-14 2008-01-09 株式会社ルネサステクノロジ 半導体集積回路装置
US7075103B2 (en) 2003-12-19 2006-07-11 General Electric Company Multilayer device and method of making
JP6427589B2 (ja) 2014-02-14 2018-11-21 アーベーベー・シュバイツ・アーゲー ２つの補助エミッタ導体経路を有する半導体モジュール
CN107004578B (zh) 2014-09-15 2020-01-24 Abb瑞士股份有限公司 用于制造包括薄半导体晶圆的半导体器件的方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60121715A (ja) * 1983-12-06 1985-06-29 Toshiba Corp 半導体ウエハの接合方法
EP0238066A2 (fr) * 1986-03-18 1987-09-23 Fujitsu Limited Procédé pour effectuer l'adhésion entre des disques de silicium ou de dioxyde de silicium
EP0256397A1 (fr) * 1986-07-31 1988-02-24 Hitachi, Ltd. Dispositif semi-conducteur ayant une couche enterrée
EP0441270A2 (fr) * 1990-02-07 1991-08-14 Harris Corporation Soudage de plaquettes utilisant de la vapeur oxydante piégée
GB2242313A (en) * 1990-03-21 1991-09-25 Bosch Gmbh Robert Process for producing multilayer silicon structures
US5183769A (en) * 1991-05-06 1993-02-02 Motorola, Inc. Vertical current flow semiconductor device utilizing wafer bonding

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60121715A (ja) * 1983-12-06 1985-06-29 Toshiba Corp 半導体ウエハの接合方法
EP0238066A2 (fr) * 1986-03-18 1987-09-23 Fujitsu Limited Procédé pour effectuer l'adhésion entre des disques de silicium ou de dioxyde de silicium
EP0256397A1 (fr) * 1986-07-31 1988-02-24 Hitachi, Ltd. Dispositif semi-conducteur ayant une couche enterrée
EP0441270A2 (fr) * 1990-02-07 1991-08-14 Harris Corporation Soudage de plaquettes utilisant de la vapeur oxydante piégée
GB2242313A (en) * 1990-03-21 1991-09-25 Bosch Gmbh Robert Process for producing multilayer silicon structures
US5183769A (en) * 1991-05-06 1993-02-02 Motorola, Inc. Vertical current flow semiconductor device utilizing wafer bonding

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
A. FUKURODA ET AL.: "Si WAFER BONDING WITH Ta SILICIDE FORMATIONl1693", JAPANESE JOURNAL OF APPLIED PHYSICS., vol. 30, no. 10A, 1 October 1991 (1991-10-01), TOKYO JP, pages L1693 - L1695 *
B. MÜLLER ET AL.: "TENSILE STRENGTH CHARACTERIZATION OF LOW-TEMPERATURE FUSION-BONDED SILICON WAFERS", JOURNAL OF MICROMECHANICS & MICROENGINEERING, vol. 1, no. 3, 1991, NEW-YORK, pages 161 - 166 *
D.J. GODBEY ET AL.: "FABRICATION OF BOND AND ETCH BACK SILICON ON INSULATOR USING A STRAINED Si0.7Ge0.3 LAYER AS AN ETCH STOP.", JOURNAL OF THE ELECTROCHEMICAL SOCIETY, vol. 137, no. 10, October 1990 (1990-10-01), MANCHESTER, NEW HAMPSHIRE US, pages 3219 - 3223 *
E.V. ASTROVA ET AL.: "THE NATURE OF THE P-TYPE LAYER FORMED IN THE INTERFACE REGION OF SEMICONDUCTING WAFERS DURING SOLIS-PHASE DIRECT BONDING OF SILICON", SOVIET TECHNICAL PHYSICS LETTERS, vol. 18, no. 7, July 1992 (1992-07-01), NEW YORK US, pages 457 - 458 *
G.P. IMTHURN ET AL.: "BONDED SILICON-ON-SAPPHIRE WAFERS AND DEVICES", JOURNAL OF APPLIED PHYSICS., vol. 72, no. 6, 15 September 1992 (1992-09-15), NEW YORK US, pages 2526 - 2527 *
PATENT ABSTRACTS OF JAPAN vol. 9, no. 277 (E - 355) 6 November 1985 (1985-11-06) *

Also Published As

Publication number Publication date
WO1994023444A2 (fr) 1994-10-13

Similar Documents

Publication Publication Date Title
US5849627A (en) Bonded wafer processing with oxidative bonding
US5362667A (en) Bonded wafer processing
EP0637065A3 (fr) Planarisation mécano-chimique de rainures plates sur substrates semi-conducteur.
EP0840366A3 (fr) Méthode de fabrication d'une couche de silica dopée par phosphore
EP0342796A3 (fr) Transistor à couche mince
EP0738009A3 (fr) Dispositif semi-conducteur avec un condensateur
EP0335741A3 (fr) Substrat semiconducteur avec isolation diélectrique
TW358992B (en) Semiconductor device and method of fabricating the same
EP0821417A3 (fr) Semi-conducteur thermoélectrique et procédé de fabrication
EP0110997A4 (fr) Dispositif a semi-conducteurs.
EP1119038A3 (fr) Procédé de fabrication d'un dispositif semi-conducteur
EP0670592A3 (fr) Dispositifs semi-conducteurs et leur fabrication utilisant la dépendance cristalline du dopage quant à l'orientation.
EP0463165A4 (en) Device and method of manufacturing the same; and semiconductor device and method of manufacturing the same
WO1994023444A3 (fr) Procede de liaison de tranches par oxydation
EP1039531A3 (fr) Interconnexion dans un dispositif semiconducteur et sa méthode de fabrication
TW365068B (en) Semiconductor device and its manufacturing method
JPS6472557A (en) Image sensor
EP1130628A4 (fr) Dispositif semi-conducteur et son procede de fabrication
WO1996013858A3 (fr) Dispositif a semi-conducteurs integre pour micro-ondes avec un composant actif et un composant passif
EP0195460A3 (fr) Circuit intégré à semi-conducteur ayant une région d'isolation
EP0561167A3 (fr) Méthode et structure d'un petit semi-conducteur
IE822988L (en) Multilayer electrode of a semiconductor device
EP1150354A4 (fr) Condensateur et son procede de fabrication
EP0324555A3 (fr) Substrat pour IC hybride, IC hybride utilisant ce substrat et son application
KR960035758A (ko) 실리콘 단결정 웨이퍼 및 그의 표면의 열산화방법

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): CA JP

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): CA JP

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: CA

122 Ep: pct application non-entry in european phase