WO1994006210A1 - Elaboration de circuits integres a puces multiples utilisant le multiplexage temporel - Google Patents

Elaboration de circuits integres a puces multiples utilisant le multiplexage temporel Download PDF

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Publication number
WO1994006210A1
WO1994006210A1 PCT/US1992/007299 US9207299W WO9406210A1 WO 1994006210 A1 WO1994006210 A1 WO 1994006210A1 US 9207299 W US9207299 W US 9207299W WO 9406210 A1 WO9406210 A1 WO 9406210A1
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Prior art keywords
module
shift register
chip
chips
multichip
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PCT/US1992/007299
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English (en)
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Prabhakar Goel
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Prabhakar Goel
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Publication date
Application filed by Prabhakar Goel filed Critical Prabhakar Goel
Priority to AU25611/92A priority Critical patent/AU2561192A/en
Priority to PCT/US1992/007299 priority patent/WO1994006210A1/fr
Publication of WO1994006210A1 publication Critical patent/WO1994006210A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/22—Means for limiting or controlling the pin/gate ratio
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Definitions

  • This invention pertains to the field of designing circuits having a plurality of integrated circuit (i.e.) chips, said design using techniques of TDM (time division multiplexing) .
  • TDM time division multiplexing
  • U.S. patent 5,036,473 uses dedicated FPGA' s solely to determine what active FPGA' s get connected to which others.
  • the reference discloses the use of software to drive and observe signals, but does not disclose the use of shift registers or TDM.
  • U.S. patent 5,109,353 discloses an array of programmable gate elements for emulating electronic circuits and systems. It does not disclose the use of shift registers or TDM.
  • the present invention is a multichip integrated circuit module (4) comprising at least two integrated circuit chips (1) .
  • the first chip (1) has at least one output shift register (9) .
  • the second chip (1) has at least one input shift register (7) .
  • Interconnections (19) couple the output register (s) (9) and the input shift register(s) (7) .
  • Means (15) are provided for loading data in parallel to the output shift register (s) (9) .
  • Means (17) are provided for sequentially shifting data through the output shift register (s) (9) over the interconnections (19) and into the input shift register (s) (7) .
  • Figure 1 is a sketch of an embodiment of the present invention in which an integrated circuit chip 1 uses at least one input shift register 7 and one output shift register 9.
  • Figure 2 is a sketch showing how the techniques of the present invention reduce the number of interconnection wires 19.among chips 1.
  • Figure 3 is a sketch of an embodiment of the present invention in which the number of stages 24 in an input shift register 7 and output shift register 9 can be reduced by one.
  • Figure 4 is a sketch of a chip 1 using tri-state output drivers 21.
  • Figure 5 is a sketch of an embodiment of the present invention in which two output shift registers 9 are used in conjunction with a single output driver 21.
  • Figure 6 is a sketch showing a plurality of tri-state output drivers 21, each having a common gating signal 23.
  • Figure 7 is a sketch showing how a single output shift register 9 can be used when the output drivers 21 have a common gating signal 23.
  • Figure 8 is a sketch showing the use of bi-directional pins and a plurality of tri-state output drivers 21 having a common gating signal 23.
  • Figure 9 is a sketch showing how a single bi-directional pin 25 can be used when a plurality of tri-state output drivers 21 have a common gating signal 23.
  • Figure 10 shows a chip 1 having a plurality of bi-directional pins 25, each coupled to an output driver 21 that has a different gating signal.
  • Figure 11 shows a single pin 25 equivalent to the embodiment depicted in Figure 10.
  • Figure 12 shows an embodiment of the present invention in which asynchronous logic 18 is employed.
  • Figure 13 shows an embodiment of the present invention in which a plurality of output shift registers 9 are daisy chained together.
  • Figure 14 shows an embodiment of the present invention in which a plurality of test shift registers 12 are multiplexed together.
  • FIG. 15 shows an embodiment of the present invention in which the TDM sequence must be applied twice
  • FIG 16 shows an embodiment of the present invention in which an interconnect 19 couples two chips 1.
  • Figure 17 shows how the interconnect 19 of Figure 16 can be reconfigured by reprogramming the first chip 1(1) .
  • Figure 18 shows a single interconnect 19 coupling four chips 1.
  • Figure 19 shows how the interconnect 19 of Figure 18 can be reprogrammed by reprogramming the source chip 1(1) .
  • Figure 20 shows an embodiment of the present invention in which an interconnect wire 19 couples two chips 1.
  • Figure 21 shows how the interconnect 19 of Figure 20 can be reprogrammed by adding a new signal S3 to the source chip 1(1) .
  • Figure 22 shows an embodiment of the present invention in which the number of stages 24 in an input shift register 7 can be reduced by one.
  • a major purpose of this invention is to increase the effective number of input/output (I/O) pins 3,5 on integrated circuit chips 1 within a module 4 that comprises a plurality of said chips 1.
  • the invention can be thought of as creating a number of virtual I/O pins 3,5 that is greater than the number of actual pins 3,5.
  • the invention also eases pressures on the system designer when the number of interconnect wires 19 on the module 4 is limited. Further, the invention enhances the reconfigurability of signal flow across chips 1.
  • the module 4 can be a production module, in which the chips 1 are executable and application-ready.
  • module 4 can be a prototype module, in which the chips 1 are experimented with by the designer to create a system design. Changes in such a prototyping environment are typically done by a combination of hardware and software changes .
  • module 4 can contain some production chips 1 and some programmable chips 1.
  • Chips 1 are any chips for which the user has control over the contents, such as FPGA' s (field programmable gate arrays) , non-field-programmable gate arrays, custom i.c.'s, semi-custom i.c.'s (application specific integrated circuits), and standard cell i.c.'s. FPGA' s are normally preferable, because of their flexibility.
  • FPGA' s field programmable gate arrays
  • non-field-programmable gate arrays custom i.c.'s
  • custom i.c.'s custom i.c.'s
  • semi-custom i.c.'s application specific integrated circuits
  • standard cell i.c.'s standard cell i.c.'s.
  • FPGA' s are normally preferable, because of their flexibility.
  • the present invention makes use of techniques of TDM
  • N is any positive integer greater than or equal to 2, and could be typically between 2 and 5.
  • N is the same for all shift registers 7,9 on a chip 1. If N were not the same, a separate shift clock 17 would be needed for each different value of N. In the chip 1 illustrated in Figure 1, the value of N is the same, and therefore there is but one shift clock 17.
  • Each chip 1 can have a plurality of input pins 3 and a different number of output pins 5.
  • the different chips 1 on a module 4 can have different numbers of input pins 3 and output pins 5.
  • the individual stages 24 of the shift registers 7,9 can be, for example, flip-flops, edge triggered latches, and pairs of polarity hold latches . When polarity hold latches are used, a pair of shift clocks 17 is required for use with the corresponding shift register 7,9.
  • the shift register 9 attached to an output pin 5 is referred to as an output shift register (OSR) 9, and functions as N virtual output pins 5.
  • N internal signals from within the chip 1 can be loaded into the OSR 9 in parallel by means of activating a parallel load clock 15 associated with the OSR 9. These signals are then serially shifted out of the OSR 9 over the corresponding output pin 5 using the shift clock 17 associated with said OSR 9. The signals travel over interconnection wires 19 to other chips 1 that need to receive the signals.
  • the shift register 7 attached to an input pin 3 is referred to as an input shift register (ISR) 7, and functions as N virtual input pins 3. It can receive serially N signals from a board interconnect 19 through the associated input pin 3 by means of the shift clock 17 that is connected to said ISR 7. The received signals can then simultaneously be applied inside the chip 1 using their stored states within the stages of the ISR 7. No special clock is needed to unload the signals from the ISR 7, because once these signals are in the ISR 7, they are visible to the logic within the chip 1.
  • ISR input shift register
  • a single parallel load clock 15 and a single shift clock 17 are used for all the ISR' s 7 and OSR' s 9 on the board 4.
  • the OSR' s 9, ISR' s 7, and attendant parallel load and shift clocks 15, 17 are customized within peripheral regions of the gate arrays 1.
  • the OSR' s 9 and ISR' s 7 are fabricated from logic normally present on the gate arrays 1.
  • Figure 2 illustrates how the invention minimizes th number of interconnect wires 19 among chips 1,2 and minimizes the number of I/O pins 3,5 within a chip 1.
  • Figure 2 illustrates the interconnections of OSR 9 within a source chip 1 and three ISR' s 7 residing within three target (sink) chips 1.
  • the target chips 1 could be identical or different in a hardware sense.
  • a single interconnect wire 19 couples the chips 1.
  • Three signals SI, S2, and S3 from the source chip 1 are conveyed to the three sink chips 1. If the TDM and shift register technique were not used, three interconnects 19 would be required.
  • the interconnect wire 19 can be thought of as a TDM bus which bundles in the time domain the three signals SI, S2 and S3. Said TDM bus 19 is visible to all three sink chips 1.
  • the TDM process described herein is transparent to the intended logic design. This transparency can be achieved in different ways, depending upon the degree of transparency needed. For example, if all chips 1 on the module 4 are synchronously clocked (which is preferable) , the following two-step TDM process can be used, at a safe time after the application of each pulse from the system clock (not illustrated) .
  • the safe time is that amount of time needed for all of the signals in the logic to achieve a steady state, i.e., when the intended design has been programmed into the chips 1.
  • Step 1 The parallel load clock 15 (which is preferably a single clock applied to all output shift registers 9 on the board 4) is applied to effect a parallel capture of signals into all of the OSR' s 9 on all the chips 1.
  • Step 2 Using the shift clock 17 (preferably a single clock used by all the ISR' s 7 and OSR' s 9 on all the chips 1), the contents of all of the OSR' s 9 are shifted into the target ISR' s 7 via the interconnects 19. This shifting process involves N applications of shift clock 17 to all of the chips 1.
  • the shift clock 17 preferably a single clock used by all the ISR' s 7 and OSR' s 9 on all the chips 1
  • I/O pins are bi-directional pins 25 (see Figure 8) . Such bi-directional pins 25 could be left unmodified. Signals involving such pins 25 are not affected by the above two steps.
  • Inputs 3 that receive direct clock signals (as opposed to data signals) do not require the use of an ISR 7. Such would be undesirable, because it would cause the clock to jiggle.
  • output pins 5 that carry clock signals going to other chips 1 do not require the use of OSR' s 9. Clock signals cannot be transferred across chips 1 using TDM without significant impact to the intended logic. As such, it is not desirable to use such techniques for I/O pins 3,5 that carry clock signals.
  • FIG 12 shows that if the logic being prototyped is asynchronous, an additional latch 29 is needed for each ISR 7 stage 24 that drives a piece of asynchronous logic 18.
  • a latch 29 is a voltage level or logic level sensitive latch that receives its data from an ISR 7 stage output and is clocked by yet another clock called the P clock 27.
  • P clock 27 is shared among all chips 1 that have asynchronous logic.
  • the function of this added latch 29 is to screen the shifting of the ISR 7 from the asynchronous logic 18.
  • P clock 27 is pulsed once after the completion of the two usual TDM steps, described earlier, that are used to effectuate the transfer of signals across chip 1 boundaries using TDM.
  • some of the stages 24 of the ISR 7 can drive synchronous logic 16, and others of the stages 24 can drive asynchronous logic 18.
  • multiple OSR' s 9 can be connected into one daisy-chained composite "test shift register” (TSR) 12 on each chip 1 to facilitate the observation of the captured signals externally by shifting out the TSR 12. All of the observation can be performed at the output of pin 5 (M) . These observed signals can be used for debugging the prototype hardware, depending upon the availability of extra board 4 logic and pins 3,5. The contents of the TSR 12 can then be reloaded from the output 5 (M) of the TSR 12 to the shift register data input 3 on the same chip 1 if it is desired to continue with the operation of the hardware.
  • TSR test shift register
  • a preferred way of accomplishing this reloading is to make a connection on the chip 1 itself from output 5 (M) to input 3, thereby creating a circular shift register.
  • the set of TSR' s 12 can be multiplexed to be observable at the output 10 of the board 4 as illustrated in Figure 14.
  • Multiplexer select signals 14 control the selection of the individual TSPs. 12 outputs by multiplexer 8.
  • the input to all the TSR' s 12 is injected via board input 6.
  • the scheme depicted in Figure 14 is useful when there are more chip output pins 5 that the designer wants to observe than there are available board output pins 10. Since the OSR' s 9 are usable for debugging purposes, the designer can choose to provide extra, initially unused, stages 24 within some OSR' s 9. These stages 24 are then available to be used for observing internal signals that the hardware designer may not have thought about earlier, for example, by changing the programming on the chip 1 to look at these stages 24.
  • FIG. 14 shows a module 4 with a number of FPGA' s 1 and set up for using TDM. To achieve a reprogrammable board 4, it is required that one must able to reprogram both the logic on the chips 1 as well as the interconnects 19. The on-chip logic is already rather reprogrammable through the use of the FPGA' s 1. To reprogram the interconnects 19, an FPGA 1 can be used as a programmable interconnect chip as in U.S.
  • Figure 16 shows three signals, SI, S2, S3, TDM' ed between chips 1(1) and 1(2) .
  • the manner in which the three signals SI, S2, S3 connect can be changed, as shown in Figure 17.
  • the connections 19 between the two chips 1 have been rewired.
  • Figure 18 shows four chips 1 with signals SI, S2, S3 connected as shown.
  • signal S3 crossing between chips 1(1) and chips 1(4) is changed to S4.
  • Figure 20 two interconnected chips 1 are shown.
  • Figure 21 shows how a signal can be added to the interconnect 19 just by reprogramming the individual chip 1(1) and not touching the interconnect 19.
  • chip 1 being able to reprogram a number of signals that are TDM'ed across to other chips 1.
  • Traditional techniques limit the reprogramability to a single signal.
  • the total number of signals that can be moved across the chip 1 boundaries is predetermined.
  • the total number of signals movable is N multiplied by the number of unique interconnect wires 19 on the board 4. It is apparent that by increasing N, a capacity greater than what is initially needed for the total number of signals can be achieved.
  • the additional capability is usable for greater flexibility in reconfiguring the interconnects 19. Theoretically, it is possible to accomplish all interconnections between any two chips 1 by using two interconnect wires 19 between them: one to carry signals flowing in one direction, and the second to carry signals flowing in the opposition direction. In this extreme situation of maximum multiplexing, the shift registers 7,9 must have an N greater than or equal to the larger of the number of the input signals and the number of the output signals on any single chip 1. (One signal is associated with each stage 24 of a shift register 7,9.)
  • ISR' s 7 and OSR' s 9 need not be placed on all qualifying I/O pins 3,5. Instead, if there are insufficient resources on the chip 1, the ISR' s and OSR' s 7,9 may be deployed only on enough I/O pins 3,5 to allow adequate signal flow through the chips 1. It should be noted that an interconnect 19 must have either ISR' s 7 and OSR' s 9 on all terminals of that interconnect 19, or else must have no ISR' s 7 or OSR' s 9 at all.
  • the chips 1 are FPGA's
  • Figure 22 shows an optimized version of the scheme in Figure 2.
  • the contents of the OSR 9 can be made observable, while reducing the number of stages 24 in an ISR 7 by one.
  • the state of the last stage 24 of an OSR 9 is used as a substitute for the eliminated stage 24 of an ISR 7.
  • the number of stages 24 needed in an ISR 7 and OSR 9 can be reduced by one, corresponding to the stage 24 the system designer does not need to observe. This reduction is achieved by using the scheme depicted in Figure 3.
  • Figure 3 shows how N equals 2 can provide the capability to multiplex three signals across a single interconnect 19.
  • the final state of the interconnect 19 after application of the TDM sequence is used as one of the multiplexed signals for the sink chip 1(2) .
  • the scheme depicted in Figure 2 does not have the sink chips 1 dependent upon the final state of the interconnect 19, but only on the states of the ISR's 7.
  • the scheme depicted in Figure 1 uses ISR' s 7 and OSR' s 9 to multiplex signals across chip 1 boundaries.
  • Such a TDM sequence serves to transfer signals once across an interconnect 19.
  • the TDM sequence needs to be repeated.
  • the total number of TDM sequence applications required is equal to the number of distinct board level interconnect wires 19 that are included in the logic path.
  • Figure 15 shows a logic path of combinational logic 22 that spans two board level interconnect wires 19(1) and 19(2) . There are no latches other than ISR's 7 and OSR' s 9 in the path.
  • the TDM sequence needs to be applied twice to move the signal through the three chips 1.
  • ISR's 7 and OSR' s 9 force the use of TDM.
  • the signal from chip 1(1) to chip 1(2) to chip 1(3) would flow without any clocking.
  • the techniques of the present invention can be extended to bi-directional pins 25 and/or three state output drivers 21. (See Figure 4) .
  • Such a driver 21 typically has outputs of logical zero, logical one, and high impedance.
  • Buses 19 generally employ tri-state drivers 21 to allow multiple source chips 1 onto a single wire. Such buses 19 are intended by the designer to achieve efficient interconnects between a multitude of source chips 1 and some number of sink chips 1.
  • one source chip output driver 21 is active while others are in a high impedance state, so that one source chip output driver 21 is driving all receivers in the bus 19.
  • the architecture shown in Figure 1 cannot be employed directly in such a case.
  • Figure 4 shows N output pins 5, with a tri-state driver 21 on each pin 5.
  • the OSR 9 scheme of Figure 1 will not work here, because the high impedance state cannot be transmitted via an OSR 9 and an ISR 7. Instead, the scheme shown in Figure 5 needs to be employed. It should be noted that this scheme uses two OSR' s 9 instead of one: the first OSR 9(1) to capture the N gating signals and the second OSR 9(2) to capture the N data signals.
  • Output driver 21 sees the corresponding gate-data combination as the OSR' s 9 are shifted out.
  • output pin 5 sees the gated output from output driver 21.
  • the generated TDM sequence of signals on output pin 5 combines with similarly generated TDM sequences from other output pins 5 that are connected with this first output pin 5.
  • Figure 6 shows N output pins 5 with high impedance drivers 21 that share a common output gating signal 23. Signal 23 either produces a high impedance on the outputs of drivers 21 or else transmits the input signals to the outputs.
  • Figure 7 shows a corresponding single pin architecture that avoids the use of two OSR' s 9 but still places output driver 21 between the single OSR 9 and the output pin 5. The use of two OSR' s 9 is avoided because of the presence of the common gating signal 23.
  • Figure 8 shows a typical N bi-directional pin 25 configuration with a common output gating signal 23.
  • the same pin 25 is used to both output a signal from the chip 1 as well as to receive signals from the outside.
  • the scheme of Figure 9 is employed.
  • the architecture of Figure 7 is used to feed the outputs of the N drivers 21, and a single ISR 7 is used for the N input signals as in the Figure 1 embodiment .
  • Figure 10 shows N bi-directional pins 25, each with a different gating output signal.
  • the single-pin 25 architecture equivalent for TDM of the N signals uses the scheme shown in Figure 11.
  • the architecture of Figure 5 is employed for the N output drivers 21, and a single ISR 7 is applied to the N input signals as in the Figure 1 embodiment.
  • Personalization instructions are injected into module 4, e.g., by techniques described in U.S. patent 5,109,353 cited above. More than one logic design can be introduced into the module 4 by different personalization instructions.
  • Software that is intended to provide automatic or interactive partitioning of the intended system design, such as Concept Silicon from InCA cited above, can exploit the knowledge of the existence of
  • ISR' s 7 and OSR' s 9 to help pack more logic into each of the programmable chips 1 and/or to minimize the number of interconnection wires 19.
  • the software is executed on a computer external to module 4, e.g., a workstation.
  • the software can be standalone (not physically coupled to module 4) software that exploits the hardware architecture of the module 4 as introduced by the invention.
  • the benefit of minimizing the number of chips 1 is obvious.
  • the benefit of minimizing the number of interconnects 19 is significant. If the prototype board 4 is intended to utilize Aptix-type programmable interconnect chips, minimizing the number of interconnects 19 will reduce the number of Aptix components needed to achieve programmable interconnects. Either the software is told the number of virtual I/O's 3,5 rather than the actual number; or else the software is told all about the ISR's 7 and OSR' s 9 so that it will take this information into account when it does the partitioning. The programmable interconnect chip does not always need to be changed.
  • ISR's 7 and/or OSR' s 9 are placed on the chips 1 to which the programmable interconnect chip is connected, thereby enhancing the programmable interconnect chip.
  • Combining the use of the present invention with the use of one or more programmable interconnect chips can allow the board 4 designer the flexibility of creating additional interconnects 19 among chips 1.
  • Programmable interconnect chips are used to interconnect among two or more I/O pins 3,5. These I/O pins 3,5 could also have ISR's 7 and OSR' s 9 on board the chip 1, thus providing a greatly increased number of programmable interconnects.
  • the configuration of the prototype board 4 is changed by a combination of hardware and software.
  • interconnects 19 are reprogrammed, FPGA' s and/or programmable interconnect chips 1 are reprogrammed, FPGA' s 1 are added or subtracted, and connections are obliterated using lasers.
  • software changes software other than the partitioning software is used to, e.g., reprogram the Aptix chip(s) 1.

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Abstract

Dans un module (4) de circuits intégrés à puces multiples, le nombre de broches effectives d'entrée/sortie (respectivement 3, 5) est augmenté au moyen de techniques du multiplexage temporel. Une première puce (1) présente au moins un registre de décalage d'entrée (7). Une seconde puce (1) présente au moins un registre de décalage d'entrée (7). Des fils métalliques d'interconnexion (19) relient les registres de décalage de sortie (9) et les registres de décalage d'entrée (7). Des moyens (15) sont prévus pour charger des données en parallèle dans les registres de décalage de sortie (9). Des moyens (17) sont prévus pour décaler séquentiellement les données par les registres de décalage de sortie (9) via les interconnexions (19), et vers les registres de décalage d'entrée (7). On décrit des modes de réalisation de l'invention pour une utilisation avec des broches bi-directionnelles (25), des circuits d'attaque de sortie à trois états (21) et une logique asynchrone (18).
PCT/US1992/007299 1992-08-28 1992-08-28 Elaboration de circuits integres a puces multiples utilisant le multiplexage temporel WO1994006210A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU25611/92A AU2561192A (en) 1992-08-28 1992-08-28 Multichip ic design using tdm
PCT/US1992/007299 WO1994006210A1 (fr) 1992-08-28 1992-08-28 Elaboration de circuits integres a puces multiples utilisant le multiplexage temporel

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US6817001B1 (en) 2002-03-20 2004-11-09 Kudlugi Muralidhar R Functional verification of logic and memory circuits with multiple asynchronous domains
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