WO1994000900A1 - Systeme de maintien independant du courant de niveau logique et de la tension - Google Patents

Systeme de maintien independant du courant de niveau logique et de la tension Download PDF

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Publication number
WO1994000900A1
WO1994000900A1 PCT/US1993/005979 US9305979W WO9400900A1 WO 1994000900 A1 WO1994000900 A1 WO 1994000900A1 US 9305979 W US9305979 W US 9305979W WO 9400900 A1 WO9400900 A1 WO 9400900A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
restraint
conduction path
upstream
distribution system
Prior art date
Application number
PCT/US1993/005979
Other languages
English (en)
Inventor
Jerry R. Baack
Andy A. Haun
Original Assignee
Square D Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Square D Company filed Critical Square D Company
Priority to EP93915453A priority Critical patent/EP0600076A1/fr
Priority to AU45433/93A priority patent/AU4543393A/en
Priority to JP6502544A priority patent/JPH06509938A/ja
Publication of WO1994000900A1 publication Critical patent/WO1994000900A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/26—Sectionalised protection of cable or line systems, e.g. for disconnecting a section on which a short-circuit, earth fault, or arc discharge has occured
    • H02H7/261—Sectionalised protection of cable or line systems, e.g. for disconnecting a section on which a short-circuit, earth fault, or arc discharge has occured involving signal transmission between at least two stations
    • H02H7/262—Sectionalised protection of cable or line systems, e.g. for disconnecting a section on which a short-circuit, earth fault, or arc discharge has occured involving signal transmission between at least two stations involving transmissions of switching or blocking orders
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H1/00—Details of emergency protective circuit arrangements
    • H02H1/06—Arrangements for supplying operative power
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H03K17/08142—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches

Definitions

  • This invention relates generally to electrical distribution systems of the type having a plurality of circuit breakers spaced upstream and downstream along the stream of the distribution system from a power supply source to a plurality of separate loads. More par- ticularly, the present invention relates to an improved logic level current and voltage independent restraint system for use in such type of electrical distribution system for generating an output drive signal which is independent of an output driver circuit.
  • the electrical distribution system would include an upstream protective device (i.e., main circuit breaker) located close to the power source and capable of interrupting all of the electrical loads served by the power source.
  • the upstream protective device is succeeded by a plurality of down ⁇ stream protective devices (i.e., branch circuit breakers) of successively lesser interrupting capability.
  • Each of the corresponding downstream protective devices is cap ⁇ able of interrupting the respective electrical load that it is designed to protect.
  • the coordination of the delay times among the main, tie and branch circuit breakers for various types of faults so as to isolate only the fault condition is achieved by control or restraint signals from a restraint system.
  • a downstream circuit breaker detects a fault it sends an active state restraint signal to one or more upstream circuit breakers instructing such upstream circuit breaker(s) to carry out a selected or programmable time delay.
  • the upstream circuit breaker(s) do not receive a signal to delay or restrain from a downstream circuit breaker, they will operate immediately upon sensing the fault condition since the programmed trip delay setting will be ignored.
  • FIG. 1 A prior art restraint system for communication with other circuit breakers in the same electrical distribu- tion system is shown in Figure 1 which includes a single output driver device in the form of an N-channel field- effect transistor 2.
  • An upstream restraint signal is generated at the source electrode of the transistor 2 and is connected to a plurality of restraint loads 4 via an output terminal 6.
  • the restraint signal is used to provide information on short circuit or ground fault con ⁇ dition to an increased number of upstream circuit breakers. Since the restraint loads 4 are defined by any number of upstream circuit breakers, this load will be increasingly varied at different times.
  • the amount of drive current available at the source electrode is known to be determined by the gate-to-source voltage V GS .
  • the up ⁇ stream restraint signal is generated at the emitter of the transistor 2a and is connected to the plurality of restraint loads 4 via the output terminal 6. Again, the amount of output drive available at the emitter is known to be limited to the DC current gain of the transistor 2a multiplied by its base current. Thus, when the restraint loads are increased the voltage at the output terminal 6 will likewise be decreased to a level below that which is required for an active state restraint signal.
  • the present in ⁇ vention represents an improvement over the prior art restraint systems of Figures 1 and 2.
  • the logic level current and voltage independent restraint system of the instant invention includes an output driver circuit formed of a first transistor, a second transistor and a load resistor.
  • the present invention is concerned with the provision of a logic level current and voltage restraint system used in an electrical distribution system of the type having a plurality of circuit breakers spaced upstream and down ⁇ stream along the stream of the distribution system from a power source to a plurality of separate restraint loads.
  • the restraint system generates an upstream restraint signal which is independent of an output driver circuit.
  • the restraint system includes a logic control circuit and an output driver circuit.
  • the logic control circuit is responsive to downstream logic signals for generating an upstream logic restraint signal.
  • the output driver circuit is formed of a first transistor, a second transistor, and a load resistor.
  • the first transistor has one of its conduction path electrodes connected to a power supply voltage via the load resistor and its other one of its conduction path electrodes connected to a ground potential.
  • the first transistor has its control electrode connected to receive the upstream logic restraint signal.
  • the second transistor has one of its conduction path electrodes con ⁇ nected also to the power supply voltage and its other one of its conduction path electrodes coupled to an output drive terminal for generating the upstream restraint signal.
  • the second transistor has its control electrode connected to the junction of the load resistor and the one conduction path electrode of the first transistor. A plurality of separate restraint loads are connected to the output terminal.
  • Figure 1 is a circuit diagram of a prior art restraint system utilizing a single field-effect transistor
  • Figure 2 is a schematic diagram of another prior art restraint system utilizing a single bipolar transistor
  • FIG. 3 is a circuit diagram of a restraint system, constructed in accordance with the principles of the present invention.
  • FIG. 3 a circuit diagram of a logic level current and voltage independent restraint system 10 for use in communicating with other circuit breakers in an elec ⁇ trical distribution system, which is constructed in ac ⁇ cordance with the principles of the present invention.
  • the restraint system 10 includes a logic level output control circuit 12 and an output driver circuit 14.
  • the restraint system is designed to provide an output drive or restraint output signal RS on an output drive terminal 16 which is independent of the drive voltage and current characteristics of the output driver circuit 14.
  • the restraint output signal RS provides an active or inactive information state of downstream restraint signals relating to short circuit or ground fault conditions.
  • the output terminal 16 is connected to a plurality of separate restraint loads 18 which is variable and is formed by any multiple number of upstream circuit breakers.
  • the logic level output control circuit 12 receives a plurality of downstream logic signals Dl, D2, ...Dn on respective input terminals 20a, 20b, ...20n for indicat ⁇ ing the active or inactive information state of corre ⁇ sponding downstream restraint signals. Each of the logic signals Dl through Dn may be at a high or low logic r level.
  • the control circuit 12 generates on output terminal 2 an upstream logic restraint signal UR based upon the downstream logic signals.
  • the active state of the upstream logic restraint signal UR is a high logic level, and the inactive state corresponds to a low logic level. Normally, the upstream logic restraint signal UR is inactive or restraint off (low logic level) .
  • the output driver circuit 14 includes an N-channel field-effect transistor Ql, a P-channel field-effect transistor Q2, a first resistor Rl, and a second resistor
  • the N-channel transistor Ql has its gate electrode connected to the output terminal 22 of the control circuit 12 for receiving the upstream logic restraint signal UR.
  • the drain electrode of the transistor Ql is connected to one end of the resistor Rl and to the gate of the P-channel transistor Q2.
  • the other end of the first resistor Rl is connected to a power supply potential or voltage Vdd, which is typically at +5.0 volts.
  • the source electrode of the transistor Ql is connected to a ground potential GND.
  • the source electrode of the P-channel transistor Q2 is also connected to the power supply voltage Vdd.
  • the drain electrode of the transistor Q2 is connected to one end of the second resistor R2.
  • the other end of the second resistor R2 is connected to the output drive terminal 16 for generating the restraint output signal RS.
  • the gate of the N-channel transistor Ql Under normal operating conditions (i.e., restraint off), the gate of the N-channel transistor Ql will be at the low logic level. Thus, the transistor Ql will be turned off which, in turn, renders the transistor Q2 to be non-conductive. Consequently, the restraint output signal RS on the output drive terminal 16 will be in the inactive state.
  • the upstream logic restraint signal UR is at the high logic level in response to one or more of the downstream logic signals being in the active state indi- eating a short circuit or ground fault condition in cor ⁇ responding downstream circuit breakers the transistor Ql will be turned on when its gate voltage exceeds the gate- source voltage threshold.
  • the gate electrode of the P-channel transistor Q2 will be pulled towards the ground potential, thereby causing the transistor Q2 to be rendered conductive.
  • drive current will now be supplied from the power supply voltage through the source-drain conduction path and the second resistor R2 to the restraint loads 18.
  • the restraint loads 18 are increased due to an increase in the number of upstream circuit breakers connected to the output terminal 16, the conduction state of the transistor Q2 will not be affected by the increased current drain on the restraint output signal RS in the active state since the gate-to-source voltage V GS is determined by the voltage drop across the first resistor Rl, which is independent of the restraint loads.
  • the amount of current which is available to drive the restraint loads 18 will now be determined by the selection of the value of the resistor R2.
  • the resistor R2 and the restraint loads 18 form essentially a voltage divider for the power supply voltage Vdd. It can be seen that this resistor R2 serves as a current-limiting resistor so as to protect the output driver circuit 14 against short circuit conditions.
  • the present invention provides an improved logic level current and voltage independent restraint system for generating an upstream restraint signal which is independent of an output driver circuit.
  • the instant restraint system includes an output driver circuit which is formed of a first transistor, a second transistor, and a load resistor.

Landscapes

  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

Un système de maintien, qui est indépendant du courant de niveau logique et de la tension, permet de produire un signal d'attaque de sortie indépendant d'un circuit d'attaque de sortie. Il comprend un circuit de commande de sortie de niveau logique (12) et un circuit d'attaque de sortie (14). Celui-ci est constitué d'un premier transistor (Q1), d'un second transistor (Q2) et d'une résistance de charge (R1).
PCT/US1993/005979 1992-06-19 1993-06-17 Systeme de maintien independant du courant de niveau logique et de la tension WO1994000900A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP93915453A EP0600076A1 (fr) 1992-06-19 1993-06-17 Systeme de maintien independant du courant de niveau logique et de la tension
AU45433/93A AU4543393A (en) 1992-06-19 1993-06-17 Logic level current and voltage independent restraint system
JP6502544A JPH06509938A (ja) 1992-06-19 1993-06-17 論理レベルの電流および電圧に独立な抑制システム

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US90144892A 1992-06-19 1992-06-19
US07/901,448 1992-06-19

Publications (1)

Publication Number Publication Date
WO1994000900A1 true WO1994000900A1 (fr) 1994-01-06

Family

ID=25414216

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1993/005979 WO1994000900A1 (fr) 1992-06-19 1993-06-17 Systeme de maintien independant du courant de niveau logique et de la tension

Country Status (6)

Country Link
EP (1) EP0600076A1 (fr)
JP (1) JPH06509938A (fr)
AU (1) AU4543393A (fr)
CA (1) CA2115569A1 (fr)
MX (1) MX9303736A (fr)
WO (1) WO1994000900A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104269833A (zh) * 2014-07-11 2015-01-07 天津大学 一种含dg配电网保护方案

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3571608A (en) * 1969-04-04 1971-03-23 Honeywell Inc Protective circuit
JPH02135918A (ja) * 1988-11-17 1990-05-24 Hitachi Ltd ｐ型半導体を用いたハイサイドスイツチの駆動回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3571608A (en) * 1969-04-04 1971-03-23 Honeywell Inc Protective circuit
JPH02135918A (ja) * 1988-11-17 1990-05-24 Hitachi Ltd ｐ型半導体を用いたハイサイドスイツチの駆動回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104269833A (zh) * 2014-07-11 2015-01-07 天津大学 一种含dg配电网保护方案
CN104269833B (zh) * 2014-07-11 2017-02-15 天津大学 一种含dg配电网保护方案

Also Published As

Publication number Publication date
EP0600076A1 (fr) 1994-06-08
MX9303736A (es) 1994-01-31
JPH06509938A (ja) 1994-11-02
AU4543393A (en) 1994-01-24
CA2115569A1 (fr) 1994-01-06

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