WO1993026046A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
WO1993026046A1
WO1993026046A1 PCT/JP1993/000794 JP9300794W WO9326046A1 WO 1993026046 A1 WO1993026046 A1 WO 1993026046A1 JP 9300794 W JP9300794 W JP 9300794W WO 9326046 A1 WO9326046 A1 WO 9326046A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor
semiconductor device
layer
transparent conductive
lower electrode
Prior art date
Application number
PCT/JP1993/000794
Other languages
French (fr)
Japanese (ja)
Inventor
Sin-Ichiro Kurata
Kenji Kobayashi
Tomoyoshi Zenki
Original Assignee
Kanegafuchi Kagaku Kogyo Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP4181852A external-priority patent/JPH05347398A/en
Priority claimed from JP4188718A external-priority patent/JPH066514A/en
Priority claimed from JP4197622A external-priority patent/JPH0621425A/en
Priority claimed from JP4197624A external-priority patent/JPH0621484A/en
Priority claimed from JP4197621A external-priority patent/JPH0621424A/en
Priority claimed from JP4197623A external-priority patent/JPH0621426A/en
Application filed by Kanegafuchi Kagaku Kogyo Kabushiki Kaisha filed Critical Kanegafuchi Kagaku Kogyo Kabushiki Kaisha
Priority to EP19930913518 priority Critical patent/EP0601200A4/en
Publication of WO1993026046A1 publication Critical patent/WO1993026046A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14643Photodiode arrays; MOS imagers

Definitions

  • the present invention relates to a semiconductor device, and more particularly, to a switching element such as a diode formed on a substrate such as glass, an optical sensor element composed of a photoelectric conversion element and a switching element, and a facsimile and image sensor.
  • the present invention relates to a semiconductor device such as a document reading device used in an image reading unit for inputting image information in a scanner or the like.
  • a conventional document reading apparatus 1 has a glass substrate 2 on which a photodiode 3 as a photoelectric conversion element, a blocking diode 4 as a switching element, and electricity from a photodiode 3 are arranged.
  • C 2.... C "and is to be constituted by forming.
  • the photodiode 3 and the blocking diode 4 are composed of opaque lower electrodes 3a and 4a, both made of metal, semiconductor layers 3b and 4b of amorphous silicon made of amorphous silicon, and IT0 ( Indi um Tin Oxi de) transparent upper electrode 3 c made of, 4 c is also P is configured by sequentially deposited, photodiode 3 and the blocking diode 4 is covered by a transparent interlayer insulating film 5 made of SiO This interlayer insulating film 5 Are connected in series by the connection wiring 7 via the contact hole 6 formed at the reverse polarity.
  • the lower electrode 3a constituting the photodiode 3 is connected to the channel wirings CLC S ....
  • the upper electrode 4c of the blocking diode 4 is transparent because it is deposited at the same time as the upper electrode 3c of the photodiode 3 to simplify the manufacturing process. there because it is.
  • these photodiode 3 and the blocking diode 4 in a one-dimensional as shown in the second 0 Figure is mx n number sequence, m-number of blocks beta every n,. beta 2. ... ⁇ , the anode electrode of the blocking diode 4 is connected in common within the block ⁇ B 2 .'... B m , and the anode electrode of the photodiode 3 is connected to the channel wiring CC 2 .... by C pleasant Blocks B and B 2 .... ⁇ , which are relatively connected at the same position.
  • These blocking diode 4 follower Toda Iodo 3 blocks beta which are necessary in order to sequentially select each. B 2 .... B m.
  • the document reading device 1 is intended to operate in a charge accumulation mode, as shown in Taimuchiya one bets second 1 view, the drive pulse Vp ,. Vp 2 .... Vp ra is plotted click 8 1. 8 2. ... applied in cycle T every B m .
  • the drive pulses Vp ,. Vp 2 .... Vpr are applied, the blocking diode 4 in the block ⁇ ,. ⁇ 2 .... B m becomes forward-biased and the photodiode 3 Is reverse biased. Therefore, the parallel capacitance of the photodiode 3 is charged quickly. This state is a reading state. Meanwhile, when the drive pulse Vp ,. Vp 2 .... Vp m is not applied, the block ' ⁇ ,.
  • each block ⁇ , .B 2 ..., B m repeats the reading state at time t and the accumulation state at time T-t.
  • the output current lout,. Iout 2 .... Iout representscorresponding to the amount of light incident during the accumulation state up to that point is the channel.
  • Wiring C then flows out through C 2 .... C n , and these output currents lout, Iout 2 .... Iout n are amplified and integrated by an external signal processing circuit, and then output in time series
  • the output current lout flows out of the first block B, Iout 2 .... lout n , and then the first block B, is in the accumulation state.
  • is second block B 2 to the becomes a read state, the output current lout ,. Iout 2 .... Iout flows out it from the second block B 2.
  • the second pro click beta 2 becomes read state the output current lout ,. Iout 2 .... Io ut n reverse current than the normal Ir ,. Ir 2 .... Ir "minute only decreases, and et to the third block B 3 which flows when the output current lout ,. Iout 2 .... Iout n that should not flow flows to the amount corresponding reverse reverse current ⁇ . Ir 2 .... Ir n when it is read state.
  • the present inventors generally improve the switching speed by reducing the reverse current associated with a switching element such as a blocking diode and an optical sensor element including the same, and improve the accuracy of the optical sensor element.
  • a switching element such as a blocking diode and an optical sensor element including the same
  • intensive research has been conducted to reduce reversal afterimages and to enable higher-speed reading.
  • the present invention has been achieved. Disclosure of the invention
  • the gist of the semiconductor device according to the present invention is to provide a semiconductor device including one or more semiconductor elements having a switching function and configured by sequentially stacking a lower electrode, a semiconductor layer, and an upper m-pole.
  • the lower electrode and At least one of the upper electrode and the upper electrode may be formed of one or more conductive layers, and at least the conductive layer in contact with the semiconductor layer may be formed of a transparent conductive layer.
  • one or a plurality of optical sensor elements configured by serially connecting the semiconductor element having the switching function and a photoelectric conversion element in which a lower electrode, a semiconductor layer, and an upper electrode are sequentially stacked are provided. It is here.
  • a semiconductor element having the switching function and an optical sensor element configured by serially connecting a photoelectric conversion element in which a lower electrode, a semiconductor layer, and an upper electrode are sequentially stacked are connected to a primary element.
  • a plurality of optical sensor elements are originally arranged and divided into a plurality of blocks by a certain number, and one of these optical sensor elements is commonly connected in the block, and the other is relatively connected between the blocks by channel wiring. That is, they are commonly connected to each other at the same position.
  • At least one of a lower electrode and an upper electrode of the semiconductor device is provided with at least one semiconductor element having the switching function, and the semiconductor element includes a transparent conductive layer. It is in.
  • the transparent conductive layer of the semiconductor element is made of ITO.
  • At least one or more semiconductor elements having the switching function wherein at least a semiconductor layer in contact with the transparent conductive layer among semiconductor layers of the semiconductor element is a p-type. It is a semiconductor layer.
  • the semiconductor layer of the device consists of amorphous silicon hydride deposited continuously by plasma CVD and has a pin structure.
  • the semiconductor element having the switching function and the photoelectric conversion element each have a diode characteristic, and are connected in series with each other by force source electrodes.
  • the semiconductor device having the switching function and the respective lower electrode, semiconductor layer, and upper electrode constituting the photoelectric conversion element are simultaneously deposited.
  • a semiconductor device provided with one or a plurality of optical sensor elements configured by connecting the semiconductor element having the switching function and the photoelectric conversion element in series At least one of the lower electrode and the upper electrode to be disposed is constituted by a transparent conductive layer at least in contact with the semiconductor layer.
  • the lower electrode or the upper electrode or both of them consist of one or more conductive layers, and at least the conductive layer in contact with the semiconductor layer is made of ITO or the like.
  • an interface between the semiconductor layer and the transparent conductive layer is formed. It is considered that a barrier such as a potential level and a trap level generated by diffusing the material constituting the transparent conductive layer into the semiconductor layer are formed at this interface. Therefore, even when the voltage applied to the semiconductor device is changed from the forward bias to the reverse bias, most of the carriers injected during the forward bias are considered to be blocked by the barrier. As a result, it is presumed that the reverse current is rapidly converged, and its peak value is also reduced, thereby improving the switching speed.
  • the lower electrode or the upper electrode or both of them are composed of one or more conductive layers.
  • the conductive layer in contact with the semiconductor layer is made of a transparent conductive layer such as ITO, and is transparent, light leaking from the periphery passes through the lower electrode and upper electrode and enters the semiconductor layer. I do.
  • the recombination level in the semiconductor layer is increased, and the recombination speed is increased. Therefore, even when the voltage applied to the semiconductor device is changed from the forward bias to the reverse bias, it is considered that the carriers injected at the time of the forward bias quickly disappear by recombination. As a result, it is presumed that the reverse current is rapidly converged, and the peak value is also reduced, so that the switching speed is improved.
  • a semiconductor device such as an optical sensor element composed of a semiconductor element having such a switching function and a photoelectric conversion element
  • a lower electrode or an upper electrode or both of the semiconductor elements having a switching function are formed.
  • a semiconductor device such as a document reading device provided with a semiconductor element having the switching function and a photoelectric conversion element
  • the lower electrode or the upper electrode, or both of them, which constitute the semiconductor element having the switching function is formed of one layer or two layers.
  • At least the conductive layer in contact with the semiconductor layer is composed of a transparent conductive layer such as ITO. Therefore, the semiconductor element having the switching function performs the above-described estimated operation.
  • the reverse current is rapidly converged, and the peak value is reduced, so that the switching speed of the switching element is improved.
  • a semiconductor device such as a document reading device has a reverse image lag. The signal readout speed is greatly increased.
  • FIG. 1 is a schematic cross-sectional view showing one embodiment of a switching element which is a semiconductor device according to the present invention.
  • FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, and FIG. 7 is a schematic cross-sectional view showing another embodiment of a switching element which is a semiconductor device according to the present invention.
  • FIG. 8 is a schematic cross-sectional view showing one embodiment of an optical sensor element which is a semiconductor device according to the present invention.
  • FIGS. 9 (a) and 9 (b) show the operation of the optical sensor element shown in FIG.
  • FIG. 6 is a circuit diagram for explaining the operation of the embodiment.
  • FIGS. 10, 11, and 12 are schematic cross-sectional views showing other embodiments of the optical sensor element which is the semiconductor device according to the present invention.
  • FIG. 13 is a schematic cross-sectional view showing one embodiment of a document reading apparatus which is a semiconductor device according to the present invention
  • FIG. 14 is a partial plan view of the document reading apparatus shown in FIG.
  • FIG. 15 shows the results of a comparative experiment conducted to confirm the effect of the present invention, and is a graph showing the output voltage of an original manuscript reading apparatus actually manufactured.
  • FIG. 16, FIG. 17, and FIG. 18 are all schematic cross-sectional views showing another embodiment of the document reading apparatus which is a semiconductor device according to the present invention.
  • FIG. 19 is a schematic sectional view showing an example of a document reading apparatus which is a conventional semiconductor device.
  • FIG. 20 is a circuit diagram of the document reading apparatus shown in FIG.
  • FIG. 21 is a time chart for explaining the operation of the original reading apparatus shown in FIGS. 19 and 20.
  • the semiconductor device according to the present invention has a switching function.
  • a description will be given using a switching element as a semiconductor element as an example.
  • a switching element 10 includes a transparent lower electrode 14 made of ITO (Indium Tin Oxide) and an amorphous silicon on a substrate 12 made of glass or the like.
  • a semiconductor layer 16 made of such as above and an upper electrode 18 are formed.
  • the semiconductor layer 16 includes, in order from the substrate 12 side, a p-type amorphous silicon layer 16 a in which holes serve as majority carriers, an i-type amorphous silicon layer 16 b in which an intrinsic semiconductor is provided, and a large number of carriers.
  • An n-type amorphous silicon layer 16 c is laminated to form a pin structure.
  • a transparent conductive film (14) such as ITO is formed on the substrate 12 by a vacuum evaporation method using electron beam resistance heating or a sputtering method using DC or RF. ) Is deposited. Further, a p-type amorphous silicon film (16a), an i-type amorphous silicon film (16b), and an n-type amorphous silicon film (16c) are formed thereon by a plasma CVD method or the like. Deposits continuously. Then, a transparent conductive film (18) such as ITO is deposited thereon again by a vacuum evaporation method or a sputtering method. The thickness of each of these transparent conductive films (14, 18) is preferably about several hundreds to several thousand A, but is appropriately determined in consideration of the performance of the deposited amorphous silicon film and the characteristics of the transparent conductive films. It is what is done.
  • the lower electrode 14, the semiconductor layer 16, and the upper electrode 18 are formed by sequentially patterning these films.
  • a resist solution is first applied on the uppermost transparent conductive film (18), pre-baked, and then a mask with a predetermined pattern is used. Exposure is performed, followed by development and post baking. If ITO is used as the transparent conductive film, the transparent conductive film is etched with a mixed solution of salt and nitric acid to form the upper electrode 18. Form.
  • the amorphous silicon films (16a, 16b, 16c) are etched using a parallel plate type etching apparatus.
  • the switch Yanba 1 0 - was evacuated to 3 Torr or less, introducing a CF 4 gas and 0 2 gas, 1 3. 5 6 MH z height while maintaining further pressure 5.
  • 0 P a A power of 0.1 to 0.7 W / cm 2 is supplied to the electrodes using a frequency power supply.
  • the amorphous silicon film is etched to form the semiconductor layer 16.
  • the lowermost transparent conductive film (14) is patterned by photolithography or the like in the same manner as the above-mentioned uppermost transparent conductive film (18).
  • the switching element 10 including the lower electrode 14, the semiconductor layer 16 and the upper electrode 18 is manufactured.
  • the method of forming the lower electrode 14, the semiconductor layer 16, and the upper electrode 18 by photolithography has been exemplified.
  • a film is formed in an unnecessary portion from the beginning by a mask method or the like.
  • the manufacturing method is not limited at all, for example, it may be formed so as not to be deposited.
  • the lower electrode 14 and the upper electrode 18 are formed of a transparent conductive layer, and the semiconductor layer 16 and the lower electrode 14 and the upper electrode 18 which are transparent conductive layers, particularly the lower electrode 14 are formed.
  • An interface is formed at the junction. It is considered that a potential barrier and a barrier such as a trap level formed by diffusing the material constituting the transparent conductive layer into the semiconductor layer 16 are formed at this interface. Therefore, even when the voltage applied to the switching element is changed from a forward bias to a reverse bias, most of the carriers injected during the forward bias are considered to be blocked by this barrier. Thus, reverse current 1 0 - 5 to be made to converge on the order of 1 0 _ 6 seconds, and the peak value becomes small, it is estimated that the switching speed is improved. Therefore, if this switching element 10 is used in a document reading device, a more accurate signal output can be obtained, and the signal reading speed can be further improved. It is also possible to increase the speed.
  • the lower electrode 14 and the upper electrode 18 are transparent, and light leakage from the surroundings penetrates these to the semiconductor layer 16. Incident. As a result, a large number of trap levels exist in the semiconductor layer 16 made of amorphous silicon, and when light enters the semiconductor layer 16, these trap levels change and the recombination level changes. It is expected to increase. Therefore, the recombination speed is increased, and even when the voltage applied to the switching element 10 is changed from the forward bias to the reverse bias, the carriers injected at the time of the forward bias are considered to be quickly lost by the recombination. . Thus, reverse current 1 0-1 0 - allowed to converge on the order of 6 seconds, and the peak value becomes small, it is estimated that Suitsuchingu speed is improved.
  • a transparent lower electrode 14 made of ITO or the like, a semiconductor layer 20 made only of an i-type amorphous silicon layer, and a metal A switching element 24 formed by forming an opaque upper electrode 22 may be used.
  • this switching element 24 a short-circuit barrier is formed at the interface between the i-type amorphous silicon layer (20) and the lower electrode 14, and the switching element 24 is operated in the same manner as described above.
  • a transparent lower electrode 14 made of ITO or the like, a type amorphous silicon layer 26a and an i-type amorphous silicon layer 26b are formed on a substrate 12 made of glass or the like.
  • the switching element 28 may be configured by forming a stacked semiconductor layer 26 and an opaque upper electrode 22 made of metal or the like.
  • the semiconductor layer is pi It may be structured.
  • a switching element 34 formed by forming a semiconductor layer 32 formed by laminating the layers 32b and an opaque upper electrode 22 made of metal or the like may be used.
  • the switching element 34 is of a metal-insulator-semiconductor (MIS) type, and the semiconductor layer 32 is deposited on the lower electrode 14 via a thin insulating layer 30.
  • MIS metal-insulator-semiconductor
  • the semiconductor layer may be deposited indirectly instead of directly on the lower electrode, and the same applies to other layers.
  • the electrode to be made transparent may be the lower electrode or the upper electrode, or both may be made transparent. That is, it is only necessary that at least one of the lower electrode and the upper electrode is transparent.
  • the lower electrode or the upper electrode or both electrodes of the switching element which is the semiconductor device according to the present invention, comprises one or more metal layers and a transparent conductive layer deposited on the metal layers. May be used.
  • the switching element 36 has a lower electrode 38 having a two-layer structure, a semiconductor layer 16 made of amorphous silicon or the like, and an upper electrode 18 formed on a substrate 12. It is configured.
  • the lower electrode 38 of this two-layer structure is composed of a metal layer 38a made of chromium Cr or the like and a transparent conductive layer 38b made of ITO or the like deposited on the metal layer 38a.
  • the semiconductor layer 16 may have either a pin structure or a nip structure. From the substrate 12 side, a p-type amorphous silicon layer 16a in which holes serve as majority carriers and an i-type amorphous layer serving as an intrinsic semiconductor are provided.
  • a pin structure in which a base silicon layer 16b and an n-type amorphous silicon layer 16c in which a large number of electrons are carried is preferably stacked.
  • a metal film such as chromium Cr (38 a) is formed on the substrate 12 by a vacuum evaporation method using an electron beam or resistance heating, or a sputtering method using DC or RF. Is deposited.
  • a transparent conductive film (38b) such as ITO is deposited thereon by a vacuum evaporation method or a sputtering method.
  • a p-type amorphous silicon film, an i-type amorphous silicon film, and an n-type amorphous silicon film are successively deposited, and a conductive film is deposited thereon.
  • the upper conductive film, the amorphous silicon film composed of three layers, and the lower transparent conductive film are patterned into a predetermined shape in order, and the upper electrode 18, the semiconductor layer 16, and the lower electrode 38 are patterned. And a transparent conductive layer 38b as a part.
  • the metal film is again patterned into another predetermined shape by photolithography or the like, thereby forming a metal layer 38a that is a part of the lower electrode 38.
  • a switching element 36 composed of the lower electrode 38, the semiconductor layer 16 and the upper electrode 18 is manufactured.
  • the amorphous silicon film is deposited after the metal film (38a) and the transparent conductive film (38b) are deposited in a blanket state, but before the amorphous silicon film is deposited, the transparent silicon film is deposited.
  • the transparent conductive layer 38b may be formed by patterning only the conductive film first. In this case, after forming the upper electrode 18 and the semiconductor layer 16 and then patterning the metal film in a blanket state to form the metal layer 38a, the same configuration as the switching element 36 described above can be obtained. Becomes Further, the deposition of the metal layer and the transparent conductive layer may be performed continuously without breaking the vacuum, or may be performed once by breaking the vacuum.
  • the method of patterning mainly by photolithography has been exemplified, but a film may be formed by using a mask method or the like so that a film is not deposited on unnecessary portions from the beginning. It is not limited at all.
  • the lower electrode 38 is composed of a metal layer 38a and a transparent conductive layer 38b, and an interface is formed at the junction between the semiconductor layer 16 and the transparent conductive layer 38b. ing. Therefore, this switching element 36 is operated in the same manner as the above-mentioned switching element. As a result, the reverse current is caused to converge on the order of 1 0-1 0 6 seconds, and the peak value becomes small, the switching speed is improved. Therefore, if this switching element 36 is used in a document reading device, a more accurate signal output can be obtained, and the signal reading speed can be further increased.
  • a switching element 40 comprises a lower electrode 3 composed of a metal layer 38 a and a transparent conductive layer 38 b on a substrate 12 such as a glass. 8, a semiconductor layer 26 formed by laminating a p-type amorphous silicon layer 26a and an i-type amorphous silicon layer 26b, and an opaque upper electrode 22 formed of metal or the like.
  • the semiconductor layer may have a pi structure, that is, as is clear from this example.
  • a reverse current generated in the switching element may be prevented by forming an interface with the transparent conductive layer in the semiconductor layer constituting the switching element.
  • a lower electrode 3.8 composed of a metal layer 38a and a transparent conductive layer 38b and a p-type amorphous silicon layer 42 are formed on a substrate 12 made of glass or the like.
  • a switching element 46 composed of a semiconductor layer 42 formed by laminating a and an i-type amorphous silicon layer 42 b, an insulating layer 44, and an opaque upper electrode 22 made of metal or the like. May be.
  • the switching element 46 is of the MIS type, and the upper electrode 22 made of metal is deposited on the semiconductor layer 42 via the insulating layer 44.
  • the upper electrode may be deposited on the semiconductor layer indirectly instead of directly.
  • the metal layer 38a and the transparent conductive layer 38b constituting the lower electrode 38 have different shapes, but may have the same shape.
  • various configurations can be appropriately adopted without any explanation.
  • an optical sensor element 48 comprises a substrate 12 made of glass or the like, a photo diode 50 as a photoelectric conversion element, and a blocking diode 52 as a switching element. Are formed. Both the photodiode 50 and the blocking diode 52 have a transparent lower electrode 50a, 52a made of ITO (Indium Tin Oxide) or the like and a pin structure made of amorphous silicon or the like. Semiconductor layers 5Ob and 52b and transparent upper electrodes 50c and 52c made of ITO or the like are sequentially deposited.
  • the greatest feature of the present embodiment is that the lower electrode 52a constituting the blocking diode 52 is transparent.
  • photodiodes 5 0 and blocking die O over de 5 2 is covered with Si O x or SiN transparent interlayer insulating film made of such x 5 4, contactor formed in the interlayer insulating film 4 of this Tohoru 5 6 are connected in series by the connection wiring 58 with opposite polarities. That is, the photodiode 50 and the blocking diode 5 are connected by the cuff electrodes.
  • a transparent conductive film (50a) such as ITO is formed on the substrate 12 by an electron beam, a vacuum deposition method using resistance heating, or a sputtering method using DC or RF. , 52 a) I do.
  • a transparent conductive film such as ITO
  • I do For example when depositing I TO film by DC sputtering method, first set the substrate 1 2 Chiyanba in one, evacuating the chamber in one to 1 0 one 5 Torr or less. Then, while holding the substrate 1 2 1 0 0 to 25 0 ° C, and pressure 0. 1 ⁇ 1. 0 P a, argon gas and oxygen gas under DC power 0.. 1 to 1. 0 cm 2 Is introduced at a fixed rate. Thereby, an ITO film can be deposited on the substrate 12.
  • the thickness of the transparent conductive film is appropriately determined in consideration of the performance of the amorphous silicon film deposited thereon and the characteristics of the transparent conductive film. The degree is preferred.
  • a p-type amorphous silicon film with many holes as carriers an i-type amorphous silicon film as an intrinsic semiconductor, and an n-type amorphous silicon film with many electrons as carriers by plasma CVD. are continuously deposited.
  • a transparent conductive film such as ITO is deposited thereon again by a vacuum deposition method or a sputtering method in the same manner as the lowermost transparent conductive film described above.
  • the thickness of the transparent conductive film is appropriately determined in consideration of the performance of the amorphous silicon film, the characteristics of the transparent conductive film, and the like, and is preferably about several hundred to several thousand A. If so, about 600 A is preferable.
  • these films are sequentially patterned to form lower electrodes 50a and 52a, semiconductor layers 50b and 52b, and upper electrodes 50c and 52c.
  • a resist solution is first applied to the uppermost transparent conductive film, prebaked, and then exposed using a mask engraved with a predetermined pattern. Further, development and postbaking are performed. If ITO is used for the transparent conductive film, the transparent conductive film is etched with a mixed solution of hydrochloric acid and nitric acid to form upper electrodes 50c and 5.2c. Next, the amorphous silicon film is etched using a parallel plate type etching apparatus. Sand Chi, after evacuating the chamber one to 1 0- 3 Torr or less, introducing a CF 4 gas and 0 2 gas, 1 3. 5 6 MH z while maintaining further pressure to 5.
  • An electric power of 0.1 to 0.7 W./cm 2 is supplied to the electrodes using a high frequency power supply. This allows the amorphous silicon film to be etched to form the semiconductor layers 50b and 52b. Further, after the resist used for patterning is once removed, the lowermost transparent conductive film is patterned by photolithography or the like in the same manner as the uppermost transparent conductive film described above, and the lower electrodes 50a and 52a are formed. , A photodiode 50 and a blocking diode 52 can be formed.
  • SiO x and SiN x are deposited on the photo diode 50 and the blocking diode 52 by a thermal CVD method, a normal pressure CVD method, a plasma CVD method, a sputtering method, or the like.
  • An interlayer insulating film 54 is formed by patterning into a predetermined shape by photolithography or the like.
  • a plasma CVD method the inside of the chamber is evacuated to 10 to 2 Torr or less, the substrate 12 is heated and maintained at a predetermined temperature, and then silane gas of 20 to 60 sccm is added. Nitrogen oxide gas is introduced at 150 to 3 Osccm and maintained at a pressure of 0.3 to 1.2 Torr.
  • a power of 0.01 to 0.5 W / cm 2 is supplied to the electrode facing the substrate 12 using a high-frequency power supply of 13.6 MHz.
  • the power to be supplied depends on the structure of the device and the quality of the film to be deposited.
  • a parallel plate type etching device can be used.
  • the silicon oxide film can be patterned, and the interlayer insulating film 54 can be formed.
  • the contact hole 56 on the photodiode 50 and the blocking diode 52 may be formed at this time.
  • a metal such as Cr, Ni, Pd, Ti, Mo, Ta, Al or the like is formed on these in a single layer or a multilayer by a vacuum deposition method or a sputtering method. Deposits 500 A thick Cr and 1.5 am Al in two layers. Next, this is patterned into a predetermined shape by a photolithography method or the like, and a connection wiring 58 is formed. As a result, the upper electrodes 50 c 52 c are electrically connected to each other through the connection wiring 58, and the optical sensor element 48 composed of the photodiode 50 and the blocking diode 52 is manufactured. Become.
  • connection wiring 58 is a two-layer film of A1 and Cr
  • the etching of A1 may be performed with a mixed solution of phosphoric acid, nitric acid, and acetic acid, while the etching of Cr is performed using ceric ammonium nitrate. Just do it.
  • These materials are not limited to metal as long as they can be electrically connected, and are not particularly limited.
  • a method of patterning mainly by photolithography has been described as an example, but a manufacturing method such as forming a film such that a film is not deposited on unnecessary portions from the beginning by a mask method or the like may be used. Is not limited at all.
  • the anode electrode (lower electrode 52a) of the blocking diode 52 has a positive potential Vp with respect to the anode electrode (lower electrode 50a) of the photodiode 50.
  • the blocking diode 52 becomes forward-biased, and the photodiode 50 becomes reverse-biased.
  • the parallel capacitance 60 of the photodiode 50 is charged, and the potential at the connection between the photodiode 50 and the blocking diode 52 increases.
  • the anode electrode of the blocking diode 52 is grounded, the blocking diode 52 becomes reverse-biased.
  • the parallel capacitance 60 of the photodiode 50 is discharged by the photocurrent Ip generated there. Thereafter, when the anode electrode of the blocking diode 52 is again set to the positive potential Vp, the blocking diode 52 becomes forward-biased and The parallel capacitance 60 of the diode 50 is charged again.
  • the charging current flowing at this time corresponds to the photocurrent IP and flows as an output current. Therefore, if this output current is detected, the amount of light incident on the photodiode 50 will be detected.
  • the blocking diode 52 since the lower electrode 52 a and the upper electrode 52 c of the blocking diode 52 are formed of a transparent conductive layer, the semiconductor layer 52 b and the lower electrode 52 a that is a transparent conductive layer are formed. An interface is formed at the junction with the upper electrode 52c. Therefore, it is considered that the blocking diode 52 as a switching element is operated in the same manner as described above. Thus, reverse current 1 0 - 5 are made to converge at ⁇ 1 0 seconds order one, and also decreases the peak value. Therefore, an accurate signal output can be obtained from the optical sensor element 48, and the switching speed can be improved. Furthermore, if this optical sensor element 48 is used in a document reading device, a more accurate signal output can be obtained, and the signal reading speed can be further increased.
  • optical sensor element As described above, one embodiment of the optical sensor element according to the present invention has been described in detail. However, the optical sensor element to which the present invention is applied is not limited to the above-described embodiment, but may be implemented in other aspects. is there.
  • the upper electrode 50 c constituting the photodiode 50 and the upper electrode 52 c constituting the blocking diode 52 are connected by the connection wiring 58.
  • the lower electrode 62 constituting the photodiode 50 and the lower electrode 62 constituting the blocking diode 52 are common.
  • the optical sensor element 64 may be configured such that the photodiode 50 and the blocking diode 52 are connected in series by 2.
  • the lower electrode 62 may be formed of a transparent conductive layer such as ITO.
  • the upper electrode 50 c of the photodiode 50 and the blocking diode 52 The upper electrode 52 c may be extracted to the outside by the lead wirings 66 and 68, respectively.
  • the photodiode 50 and the blocking diode 52 are connected by anode electrodes and are connected in series with opposite polarities.
  • the lower electrodes 50a and 52a and the semiconductor layers 5Ob and 5b constituting the photodiode 50 and the blocking diode 52 are formed for reasons such as simplification of the manufacturing process. 2b and the upper electrodes 50c and 52c are deposited simultaneously and are made of the same material, respectively, but the upper electrode 50C constituting the photodiode 50 'must be transparent. However, the upper electrode 52 c constituting the blocking diode 52 need not be transparent. In addition, the lower electrode 50a constituting the photodiode 50 may not be transparent, and at least the lower electrode 52a constituting the blocking diode (switching element) 52 may be transparent. ,
  • the electrode may be composed of one or more metal layers and a transparent conductive layer deposited on the metal layer.
  • an optical sensor element 70 has a photo diode 72 as a photoelectric conversion element on a substrate 12 made of glass or the like, similarly to the above-described embodiment. And a blocking diode 74 serving as a switching element.
  • Both the photodiode 72 and the blocking diode 74 are composed of a lower electrode 72 a, .74 a having a two-layer structure and a semiconductor layer 72 b, 74 having a Pin structure made of amorphous silicon or the like. b and IT 0 (Ind i um T in Oxide) and a transparent upper electrode 7 2. C, 74 c are sequentially deposited. Lower electrode 74 a blocking die O over de 74, the metal layer 74 a made of chrome Cr, and the metal layer 74 a, is composed of such a composed a transparent conductive layer 74 a 2 Metropolitan I TO deposited on I have.
  • the photodiode 72 and flop locking die O over de 74 SiO x or SiN X, such as a transparent interlayer insulating film 54 made of The connection is made in series by the connection wiring 58 through the contact hole 56 formed in the interlayer insulating film 54 with the opposite polarities.
  • a metal film such as chromium Cr is deposited on the substrate 12 by a vacuum evaporation method using electron beam resistance heating or a sputtering method using DC or RF.
  • a transparent conductive film such as ITO is deposited thereon by a vacuum evaporation method or a sputtering method.
  • the substrate 12 is set in the first chamber, and the inside of the first chamber is evacuated to less than 10 5 ⁇ . after, while maintaining the substrate 1 2 1 0 0- 25 0 ° C, pressure 0. 1 ⁇ 1. 0 P a, under DC power 0. 1 ⁇ OWZcm 2, argon gas and oxygen gas It is performed by introducing at a fixed rate and sequentially depositing a metal film and a transparent conductive film.
  • an amorphous silicon film is deposited in the order of P-type, i-type, and n-type, and then a transparent conductive film such as ITO is deposited.
  • the thickness of each of the metal film and the transparent conductive film is preferably about several hundred to several thousand A, but is appropriately determined in consideration of the characteristics of these films and the performance of the amorphous silicon film. is there.
  • the thickness of the metal film is preferably about 150 to 200 A, and the thickness of the transparent conductive film is lower (72 a 2, It is preferable that 74 a 2 ) be about 1200 A and the upper layer (72 c, 74 c) be about 600 A.
  • the upper transparent conductive film, the three-layer amorphous silicon film, and the lower transparent conductive film are patterned into a predetermined shape in order, and the upper electrodes 72 c and 7 are formed. 4 and c, to form the semiconductor layer 7 2 b, 7 4 b, and a lower portion electrode 7 2 a, 7 4 transparent conductive layer is part of a 7 2 a 2, 7 4 a 2.
  • the metal film is again patterned into another predetermined shape by photolithography or the like, and the metal layer which is a part of the lower electrodes 72 a and 74 a is formed. 7 2 a,, 7 4 a, are formed.
  • etching may be performed using, for example, a second cellium nitrate ammonium nitrate.
  • an interlayer insulating film 54 and a contact hole 56 are formed on the photo diode 72 and the blocking diode 74 in the same manner as in the above-described embodiment, and a metal is simply formed thereon. After being deposited in layers or multilayers, it is patterned and the connection wiring 58 is formed. As a result, the upper electrodes 72 c and 74 c are electrically connected to each other by the connection wiring 58, and the optical sensor element 70 composed of the photodiode 72 and the blocking diode 74 is manufactured. Become.
  • the amorphous silicon film is deposited after the metal film and the transparent conductive film are deposited in a blanket state, but before depositing the amorphous silicon film, only the transparent conductive film is first patterned to form a transparent film.
  • conductive layer 7 2 a 2, 7 4 a 2 may be formed of.
  • the blanket state metal film is patterned to form the metal layers 72a, 74a.
  • metal layer and transparent conductive The deposition with the layer may be performed continuously without breaking the vacuum or may be performed discontinuously once the vacuum is broken.
  • the method of patterning mainly by photolithography has been exemplified, but a film may be formed by preventing the film from being deposited on unnecessary portions from the beginning by a mask method or the like. It is not limited at all.
  • optical sensor element 70 The operation of the optical sensor element 70 is the same as the operation of the optical sensor element 48 described above, and a description thereof will be omitted.
  • connection wiring 58 as shown in FIG. 12, as shown in FIG. 12, a lower electrode 76 forming a photodiode 72 and a lower electrode 76 forming a blocking diode 74.
  • the lower electrode 76 may be used as an optical sensor element 78 in which the photodiode 72 and the blocking diode 74 are connected. In this case, the metal layer
  • the transparent conductive layers 8 2 and 8 4 are sequentially deposited to form the lower electrode 76, so that an interface is formed at the junction between the semiconductor layer 74 b and the transparent conductive layer 84.
  • the upper electrode 72 c of the photo diode 72 and the upper electrode 74 c of the blocking diode 74 can be taken out to the outside by the lead wirings 86, 88 via the contact holes 56, respectively. You should.
  • the photo diode 72 and the blocking diode 74 are connected between the anode electrodes and are connected in series with opposite polarities.
  • the metal layer 7 2 a,, 7 4 a ,, 8 0 and the transparent conductive layer 7 2 a 2, 7 4 a 2, 8 2, but with a 8 4 different shapes, Same — may be shaped.
  • the photodiodes 72 and the blocking diodes 74 are formed for reasons such as simplification of the manufacturing process.
  • the lower electrodes 72a and 74a, the semiconductor layers 72b and 74b, and the upper electrodes 72c and 74c are simultaneously deposited, and are made of the same material.
  • the upper electrode 72c constituting the photodiode 72 must be transparent, but the upper electrode 74c constituting the blocking diode 74 need not be transparent.
  • the lower electrode 72 a constituting the photo diode 72 does not need to be composed of the metal layer and the transparent conductive layer, and at least the lower electrode 72 a constituting the blocking diode (switching element) 74.
  • the reverse current generated in the switching element may be prevented by forming an interface with the transparent conductive layer in the semiconductor layer constituting the switching element.
  • the present invention may be further applied to a document reading apparatus.
  • an embodiment in which the present invention is applied to a document reading apparatus will be described in detail with reference to the drawings.
  • an original reading device 90 includes a photodiode 92 as a photoelectric conversion element and a switching element on a substrate 12 made of glass or the like.
  • a photodiode 92 as a photoelectric conversion element and a switching element on a substrate 12 made of glass or the like.
  • there flops locking diode 9 4 photodiode 9 Chiyan'ne Le wiring C for reading an electrical signal from the 2,. C 2.... C "and is to be constituted by forming. in this case the, full
  • the photodiode 92 and the blocking diode 94 constitute an optical sensor element.
  • photodiodes 9 2 and flop locking da I O over de 9 4 is covered with SiO x or transparent interlayer made of a SiN x insulating film 9 6, contactors Tohoru 9 formed in the interlayer insulating film 9 6 This They are connected in series with opposite polarities by a connection wiring 100 via 8. That is, the photodiode 92 and the blocking diode 94 are connected by the cathode electrodes. On the other hand, the lower electrode 92 a of the photodiode 92 is connected to the channel wirings C. C 2 ... C via contact holes 102 formed in the interlayer insulating film 96. Further, the entirety is covered with a protective film 104.
  • these photodiodes 92 and blocking diodes 94 are arranged in mxn units in one dimension, and are divided into m blocks ⁇ , .B 2 ... B m every n units. have been, ⁇ Roh one cathode electrode of blocking diode 9 4 proc B,. B 2 .... are connected in common in a B m, follower Toda Iodo 9 2 ⁇ Roh once electrode channel interconnection C, . C 2 .... C n Niyotsu Te block B,. B 2 .... are in between those in the same relative position between B m are connected to the Common.
  • the method for manufacturing a document reading apparatus 9 like the production method of the aforementioned light sensor element, after first depositing a transparent conductive film such as I TO and Sn0 2 on the substrate 1 2, this above, the amorphous silicon film a p-type, i-type, continuously deposited in the order of n-type, further on this is deposited a transparent conductive film such as an I T0 and Sn0 2.
  • the thickness of the uppermost transparent conductive film is preferably about several hundred to several thousand A, but is appropriately determined in consideration of the performance of the amorphous silicon film, the characteristics of the transparent conductive film, and the like.
  • the lowermost transparent conductive film is also patterned by photolithography or the like.
  • a photodiode 92 and a blocking diode 94 are formed.
  • an interlayer insulating film 9 6 is patterned into a predetermined shape, such as by which the follower tri lithography method I do. That is, a contact hole 98 is formed on the photo diode 92 and the blocking diode 94, and a contact hole 102 is formed on the lower electrode 92a. In the region where the extraction electrode 106 is formed on the electrode 94a, the interlayer insulating film 96 is removed.
  • connection wiring 100 and the channel wiring C and C 2 ... C are deposited thereon by a vacuum evaporation method, a sputtering method, or the like.
  • the connection wiring 100 and the channel wiring C and C 2 ... C are formed by patterning into a predetermined shape by, for example, the upper electrode 9 2 c, 9 4 with c and line 1 0 0 and are electrically connected via a contactor Tohoru 9 8, the lower portion electrode 9 2 a and the channel line CC 2 .... C "and are contactor Tohoru 1 0 2 electrically.
  • these materials are not particularly limited, for example, they may not be metals as long as they can be electrically connected.
  • silicon oxide, silicon nitride, tantalum oxide, etc. are deposited on the entire surface by plasma CVD, sputtering, or the like, and are patterned into a predetermined shape by photolithography to obtain the extraction electrode 1.
  • a protective film 104 is formed so as to cover all regions except for the extraction electrodes (not shown) of the channel wirings C 6 and C 2 .. C 2 .. C Economics. diode 9 2, blocking diode 9 4, channel wiring C].
  • the lower electrode 94a of the blocking diode 94 which is a switching element, is made of a transparent conductive layer, the semiconductor layer 94b and the lower electrode 94a are joined. An interface is formed in the part. It is considered that a potential barrier and a barrier such as a trap level formed by the substance of the lower electrode 94a constituting the transparent conductive layer being diffused into the semiconductor layer 94b are formed at this interface. Therefore, the block ⁇ ,. B 2... . B ra is reverse current flows immediately after switched from the read state to the storage state Ir
  • the switching speed of the blocking diode 120 is improved, and the reversal afterimage is greatly reduced, so that an accurate signal output can be obtained.
  • the lower electrode 94a of the blocking diode 94 which is a switching element, is made of a transparent conductive layer, so that it is possible to reduce power consumption.
  • Light leakage Ngudaiodo 9 4 of the semiconductor layer 9 4 also causes the recombination rate recombination level is increased is increased by entering the b and considered Erareru.
  • the original reading apparatus according to the present invention was manufactured by the following method.
  • Substrate 1 and 2 are made of Corning Co., Ltd. Al-free glass (# 7005)
  • an ITO film having a thickness of 1200 A was deposited on the substrate 12 by a DC sputtering method. That is, set the substrate 1 2 Chiyanba in one, was evacuated and the chamber in one to 1 0- 5 Torr or less, and holds the substrate 1 2 1 0 0-2 5 0 hands, pressure 0. 1 to 1.0 Pa, DC power 0.1 to 1.0 W / cm 2 , by introducing argon gas and oxygen gas at a constant rate, the ITO film on the substrate 12 was deposited.
  • a p-type amorphous silicon film having a thickness of 500 to 300 A, an i-type amorphous silicon film having a thickness of 700 to 1200 A, and a An n-type amorphous silicon film having a thickness of about 300 A was sequentially deposited. Then, a .1TO film having a thickness of 600 A was deposited thereon again in the same manner as the ITO film.
  • the uppermost ITO film and the three-layer amorphous silicon film are patterned by photolithography to form upper electrodes 92c, 94c and semiconductor layers 92b, 94b. did.
  • a resist solution is applied on the uppermost ITO film, pre-baked, exposed using a mask engraved with a predetermined pattern, and further developed and boost-baked.
  • the amorphous silicon film was etched using a parallel plate type etching apparatus.
  • the chamber one 1 0 - was evacuated to 3 Torr or less, introducing a CF 4 gas and 0 2 gas, a high frequency power source 1 3.
  • the numbers of the photodiodes 92 and the blocking diodes 94 are assumed to be 1728, respectively, and these are divided into 56 blocks every 32. Minutes. Further, as shown in FIG. 14, the size of the photodiode 92 was set to 105 zm ⁇ 125 ⁇ m, and the size of the booking diode 94 was set to 33 mx 33 zm.
  • a silicon oxide film having a thickness of 1.5 ⁇ m was deposited on the photodiode 92 and the blocking diode 94 by a plasma CVD method. That is, after evacuating the inside of the chamber one to 1 0- 2 Torr or less, and heating and holding the substrate 1 2 to a predetermined temperature, silane gas 2 Less than six 0 seem and, nitrous oxide gas 1 5 0 to 3 0 O sccm , And maintained at a pressure of 0.3 to 1.2 Torr (here, nitrogen gas may be introduced if necessary). After that, wait for the pressure to stabilize, and then supply electric power of 0.01 to 0.5 W / cm 2 to the electrode facing the substrate 12 using a high-frequency power supply of 13.56 MHz. A silicon oxide film was deposited. Next, the resultant was patterned into a predetermined shape by photolithography to form an interlayer insulating film 96. Here, a parallel plate type etching apparatus was used for the etching.
  • two layers of Cr and A1 are deposited on these by the sputtering method, patterned into a predetermined shape by the photolithography method, and the connection wiring 100 and the channel wirings C, C 2 .. .. to form a C n and the lead electrode 1 0 6.
  • the thickness of Cr was 500 A
  • the thickness of A1 was 1.5.
  • the etching of A1 was performed with a mixture of phosphoric acid, hydrochloric acid, nitric acid and acetic acid, and the etching of Cr was performed with a second cell ammonium nitrate.
  • a 5,000 A thick silicon nitride film was deposited on all of them by plasma CVD. That is, after evacuating the inside of the chamber one to 1 0 _ 2 Torr or less, and heating and holding the substrate 1 2 to a predetermined temperature, introducing the silane gas 2 0 to 6 0 sccm, ammonia gas 1 5 0 ⁇ 3 0 0 sccm , 0.3-1.
  • the pressure was maintained at Torr (here, hydrogen gas or nitrogen gas may be introduced as necessary). After that, wait for the pressure to stabilize, and then use a high frequency power supply of 13.56 MHz to apply a voltage of 0.01 to 0 to the electrode facing the substrate 12. A power of 5 WZcm 2 was supplied to deposit a silicon nitride film. Next, the resultant was patterned into a predetermined shape by photolithography to form a protective film 104. A parallel plate type etching apparatus was used for the etching here.
  • a manuscript reading apparatus different from the above-described embodiment 1 only in the material of the lower electrodes 92a and 94a was manufactured. That is, instead of the above-mentioned ITO film, a chromium film having a thickness of 1500 to 2000 persons is deposited by the sputtering method, and this is patterned by the photolithography method. Opaque lower electrodes 92a and 94a were formed.
  • a driving circuit and a signal processing circuit were connected to the first embodiment and the first comparative example, and the frequency of the clock pulse was set to 500 kHz, the reading speed was set to 5 msec Zline, and the color was changed from white to black.
  • the document to be read was illuminated with an illumination of 20 lux and read.
  • an output voltage Vout as shown in FIG. 15 was obtained from the signal processing circuit.
  • the solid line indicates the output voltage Vout of the example
  • the dotted line indicates the output voltage Vout of the comparative example.
  • the inverted image Vr appears in the output voltage Vout immediately after reading white, which causes black read immediately after reading white to be blacker than normal black.
  • the reversal afterimage Vr of Example 1 was smaller than the reversal afterimage Vr of Comparative Example 1, and the convergence time was shorter. Table 1 summarizes the results.
  • the output voltage V out corresponding to white was 160 to 180 mV.
  • the upper electrode 92c constituting the photodiode 92 and the upper electrode 94c constituting the blocking diode 94 are connected by the connection wiring 100.
  • the lower electrode 108 forming the photodiode 92 and the lower electrode 108 forming the blocking diode 94 are common, and the lower electrode 108
  • the document reading device 110 may be a device in which the photodiode 92 and the blocking diode 94 are connected to each other.
  • the lower electrode 108 is formed of ITO or the like.
  • the upper electrode 92 c of the photodiode 92 is taken out by a lead wire 112 through a contact hole 98 formed in the interlayer insulating film 96, and the channel wire CC is connected through a contact hole 102. 2 ... C selfish, and the upper electrode 94 c of the blocking diode 94 is drawn out to the outside by a lead wire 114 through a contact hole 98.
  • the photodiode 92 and the blocking diode 94 are connected by the same anode electrode, and are connected in series with opposite polarities.
  • the anode electrodes or Chikarasoichido electrode flop locking die O over de 9 4 proc B,. B 2... . are connected in common in a B m, Follower Todaio de 9 2 ⁇ Roh once electrode or Chikarasoichi de electrode channel wiring d. C s.... Block BB 2 by C n.... Relatively same position between B m Although they are connected to each other, the arrangement of the photodiode and the blocking diode is reversed, and the anode electrode or force electrode of the photodiode is connected in common in the block, and the blocking diode is connected.
  • Anode electrodes or force source electrodes may be connected to each other at a relatively same position between blocks by channel wiring. That is, a plurality of optical sensor elements, each composed of a photodiode (photoelectric conversion element) and a blocking diode (switching element), are arranged one-dimensionally, and are divided into a plurality of blocks every fixed number. It is only necessary that one of these optical sensor elements is commonly connected in the block, and that the other is commonly connected by the channel wiring to those at relatively the same position between the blocks.
  • the lower electrodes 92 a and 94 a and the semiconductor layer 92 b constituting the photodiode 92 and the blocking diode 94 are formed for reasons such as simplification of the manufacturing process.
  • 94 b and the upper electrodes 92 c, 94 c are deposited simultaneously, so they are each composed of the same material, but the upper electrode 92 c constituting the photodiode 92 is formed.
  • the lower electrode 92 a constituting the photodiode 92 may not be transparent, and at least the lower electrode 94 a constituting the blocking diode (switching element) 94 may be transparent.
  • the original reading apparatus which is the semiconductor device according to the present invention has the lower electrode of the blocking diode 94 which is the switching element constituting the original reading apparatus constituted by at least the transparent conductive layer.
  • the document reading apparatus according to the present invention at least a switching element is configured.
  • the lower electrode may be composed of at least one metal layer and a transparent conductive layer deposited on the metal layer.
  • the original reading apparatus 1 16 includes a photodiode 1 18 as a photoelectric conversion element on a substrate 12 made of glass or the like.
  • a flop locking diode 1 2 0 is Suitsuchingu element, photodiode 1 1 8 and the channel line C ,. C 2 .... C of order to read out the electric signals from has to be constituted by forming .
  • an optical sensor element is constituted by the photodiode 118 and the blocking diode 120.
  • Each of the photodiode 118 and the blocking diode 120 has a lower electrode 118 a, 120 a having a two-layer structure, and a semiconductor layer 118 b having a pin structure made of amorphous silicon or the like.
  • 120b and transparent upper electrodes 118c, 120c made of ITO (Indium Tin Oxide) or the like are sequentially deposited.
  • These lower electrode 1 1 8 a, 1 2 0 a is, Cr, Ni, Pd, Ti , Mo, Ta, and the like Al metal layer 1 1 8 a,, 1 2 0 a, a, I TO, Sn0 2 , and a Ti0 2 transparent conductive layer made of a 1 1 8 a 2, 1 2 0 a 2 Prefecture.
  • the photodiode 118 and the blocking diode 120 are covered with a transparent interlayer insulating film 96 as in the above-described embodiment, and the contact holes formed in the interlayer insulating film 96 are formed. They are connected in series with opposite polarities by connecting wires 100 through 98.
  • Other configurations are the same as those of the above-described embodiment.
  • a metal film such as Cr, Ni, Pd, Ti, Mo, Ta, or Al is deposited on the substrate 12 by a vacuum deposition method using an electron beam or resistance heating, or a sputtering method using DC or RF. Then on this, it deposits a transparent conductive film such as ITO or Sn0 2 by vacuum deposition Yasu sputtering method. Further, an amorphous silicon film is successively deposited thereon in the order of p-type, i-type, and n-type, and a transparent conductive film is further deposited thereon.
  • the thickness of the metal film and the transparent conductive film is preferably about several hundreds to several thousand A, but is appropriately determined in consideration of the characteristics of these films and the performance of the amorphous silicon film.
  • the upper transparent conductive film, the three-layer amorphous silicon film, and the lower transparent conductive film are patterned into a predetermined shape by photolithography or the like, and then the metal film is patterned into another predetermined shape.
  • a photodiode 118 and a blocking diode 120 are formed.
  • an interlayer insulating film 9 6 by patterning into a predetermined shape Form.
  • contact holes 98 and 102 are formed at predetermined positions on the photodiode 118, the blocking diode 120 and the metal layer 118a, and the metal layer 120a is formed.
  • the interlayer insulating film 96 is removed.
  • the transparent conductive film alone is first patterned.
  • the transparent conductive layers 1 18 a 2 and 120 a 2 may be formed in advance.
  • the metal film in the blanket state is patterned to form the metal layer 118a. ,, 120 a.
  • the configuration is the same as that of the original reading device 1 16 described above.
  • the deposition of the metal layer and the transparent conductive layer may be performed continuously without breaking the vacuum, or may be performed discontinuously once the vacuum is broken.
  • a method of patterning mainly by photolithography has been described as an example, but a film may be formed by using a mask method or the like so that a film is not deposited on unnecessary portions from the beginning. Is not limited at all.
  • the lower electrode 120 a is composed of the metal layer 120 a and the transparent conductive layer 120 a 2 , the semiconductor layer 120 b and the transparent conductive layer interface is formed at the junction of the 1 2 0 a 2.
  • This is interfacial potential barrier and is considered to Baria such as a transparent conductive layer 1 2 0 a 2 trap level substance constituting occurs diffused into the semiconductor layer 1 2 0 b a is formed. Therefore, it is considered that the same operation as that of the above-described original reading apparatus 90 is performed, and as a result, the same effect is obtained.
  • Example 2 In order to confirm such effects, a document reading apparatus according to the present example was manufactured, and a comparative experiment was performed with Comparative Example 1 described above.
  • Example 2
  • the document reading apparatus according to the present example was manufactured by the following method.
  • the substrate 12 is made of Al-free glass (# 7509) manufactured by Koingen Co., Ltd.
  • the substrate 12 is placed on the substrate 12 by the DC sputtering method.
  • An A thick chromium film was deposited, followed by a 600 A thick ITO film.
  • it sets the substrate 1 2 Chiyanba in one, after evacuating the inside of the Chiyanba until 1 0 _ 5 Torr or less, and holds the substrate 1 2 1 0 0 ⁇ 2 5 0 ° C , Chromium film and ITO film by introducing argon gas and oxygen gas at a constant rate under pressure 0.1 to 0 Pa, DC power 0.1 to 1. OW / cm 2 And were sequentially deposited. Further, as in Example 1, an amorphous silicon film was deposited thereon in the order of p-type, i-type, and n-type, and an ITO film was further deposited thereon.
  • the upper ITO film, the three-layer amorphous silicon film, and the lower ITO film were patterned into a predetermined shape, and the upper electrodes 118 c and 120 c were formed. and the semiconductor layer 1 1 8 b, 1 2 0 b, to form the lower electrode 1 1 8 a, 1 2 0 a is part transparent conductive layer 1 1 8 a 2 of, 1 2 0 a 2.
  • the lower electrode 1 1 8 a, 1 2 0 a is part transparent conductive layer 1 1 8 a 2 of, 1 2 0 a 2, the upper electrode 1 1 8 c, 1 2 0 c and the semiconductor layer 1 1 .
  • the underlying ITO film was etched using a mixture of hydrochloric acid and nitric acid. Then, after removing the resist used for patterning, the chromium film is patterned into a predetermined shape by photolithography, and the metal layer 118 a, which is a part of the lower electrodes 118 a and 120 a, is formed. ,, 120 a, are formed.
  • the second chromium ammonium nitrate was used for etching the chromium film.
  • the photodiodes 118 and the blocking diodes 120 were formed in the same number, configuration, and size as in Example 1. So Thereafter, in the same manner as in Example 1, the interlayer insulating film 96, the connection wiring 100, and the protective film 104 were formed, and a document reading apparatus was manufactured.
  • the original reading device includes an upper electrode 118 c constituting the photodiode 118 and an upper electrode 1 constituting the blocking diode 120.
  • 20 c is connected by connection wiring 100, and as shown in FIG. 18, the lower electrode 122 constituting the photodiode 118 and the blocking diode 120 are connected to each other.
  • the lower electrode 1 2 2 is common, and the lower electrode 1 2 2 connects the photodiode 118 and the blocking diode 120 to the original reading device 1. 2 4 is acceptable.
  • the metal layer 1 26 and the transparent conductive layer 1 28 are sequentially deposited to form the lower electrode 122, and the semiconductor layers 1 18 b and 120 b and the transparent conductive layer 1 2 8 It is configured so that an interface with is formed.
  • the upper electrode 1 18 c of the photodiode 1 18 is taken out by the lead-out wiring 130 via the contact hole 98 and the channel wiring C,. C 2 ... via the contact hole 102.
  • the upper electrode 120c of the blocking diode 120 is configured to be taken out to the outside through the contact hole 98 by the lead wiring 132.
  • the photodiode 118 and the blocking diode 120 are connected by the anode electrodes, and are connected in series with opposite polarities.
  • the anode electrode or Chikarasoichido electrode flop locking die O over de 1 2 0 are connected to a common within to proc B B 2 .... B m, Anodo the photodiode 1 1 8
  • the electrode or force cathode electrode are connected with each other being in the same relative position between the blocks ⁇ ,. B 2 .... B m by channel wiring d. Cs .... C n
  • the Photo Invert the arrangement of the diode and the blocking diode connect the anode electrode or the force electrode of the photodiode in the block, and connect the anode electrode or the force electrode of the blocking diode.
  • the electrodes may be connected to each other at relatively the same position between blocks by channel wiring.
  • a plurality of photosensor elements each composed of a photodiode (photoelectric conversion element) and a blocking diode (switching element), are arranged one-dimensionally, and are divided into a plurality of blocks every fixed number. Therefore, it is only necessary that one of these optical sensor elements is commonly connected in the block and that the other is commonly connected by the channel wiring at the relatively same position between the blocks. .
  • the lower electrodes 1 18a and 120 a of the photodiodes 118 and the blocking diodes 120 are formed for reasons such as simplification of the manufacturing process.
  • the semiconductor layers 1 18 b, 12 O b and The upper electrodes 1 18 c and 120 c are respectively deposited simultaneously and are made of the same material, respectively, but the upper electrodes 1 18 c constituting the photodiode 118 are formed.
  • the lower electrode 118a constituting the photodiode 118 does not need to be composed of a metal layer and a transparent conductive layer, and at least a blocking diode (switching element) 120 is required.
  • lower electrode 1 2 0 a power constituting, metallic layer 1 2 0 a and may be composed of a transparent conductive layer 1 2 0 a 2 Prefecture. That is, in the present invention, a reverse current generated in the switching element may be prevented by forming an interface between the semiconductor layer constituting the switching element and the transparent conductive layer.
  • the number of metal layers may be one, but may be two or more. ⁇
  • the semiconductor devices according to the present invention are stacked mainly in the order of pins from the substrate 12 side.
  • the semiconductor devices may be stacked in the order of nip and have a niP structure.
  • the lower electrode or the upper electrode formed of the transparent conductive layer and the P layer of the semiconductor layer are in contact with each other.
  • ni-type, pi-type, pn-type, MIS-type, hetero-junction-type, homo-junction-type, Schottky barrier-type, or a combination of these are deposited in a single layer or multilayer. May be done.
  • amorphous silicon constituting the semiconductor layer includes other materials such as amorphous silicon hydride a-Si: H, amorphous silicon carbide a-SiC: H, and amorphous silicon nitride.
  • simple amorphous silicon a-Si is preferred, but amorphous silicon-based semiconductors composed of alloys of silicon and other elements such as carbon, germanium, and tin, or amorphous or microcrystals may be deposited. These structures are not limited at all.
  • the semiconductor layer to which the present invention is applied is not limited to amorphous or microcrystal, but may be a single crystal.
  • the photoelectric conversion element is not limited to a photovoltaic element such as a photodiode, but may be, for example, a photoconductive element.
  • the present invention can be implemented in various modified, modified, and modified embodiments based on the knowledge of those skilled in the art without departing from the gist of the present invention, such as a case where the switching element may be a TFT.
  • the semiconductor device including the semiconductor element having the switching function according to the present invention at least one of the lower electrode and the upper electrode is formed of the transparent conductive layer, so that the interface between the semiconductor layer and the transparent conductive layer is formed. Therefore, the reverse current is rapidly converged by the barrier formed at this interface, and its peak value is also reduced. Therefore, the switching speed can be greatly improved. It is also considered that light leaked from the periphery penetrates through the lower electrode and the upper electrode and is incident on the semiconductor layer, whereby the reverse current is rapidly converged, and the peak value is also reduced.
  • At least one of the lower electrode and the upper electrode constituting the switching element is a photosensor element comprising the photoelectric conversion element and the semiconductor element having a switching function, which is the semiconductor device according to the present invention. Since the interface is formed of the transparent conductive layer, an interface between the semiconductor layer and the transparent conductive layer is formed, so that the reverse current is rapidly converged by the barrier formed at this interface, and However, its peak value also becomes smaller. Therefore, a more accurate signal output can be obtained, and the switching speed can be improved. It is considered that the light leaked from the periphery enters the semiconductor layer constituting the switching element, the reverse current is rapidly converged, and the peak value is also reduced.
  • the original reading apparatus which is a semiconductor device according to the present invention, has at least one of a lower electrode and an upper electrode constituting a switching element. Since one of the transparent conductive layers forms an interface between the semiconductor layer and the transparent conductive layer, the reverse current is rapidly converged by the barrier formed at this interface, and The peak value is also reduced, and the switching speed of the switching element is improved. For this reason, inversion inversion is reduced, and an accurate signal output can be obtained. This is particularly advantageous when reading a document under low illuminance, and can reduce power consumption. Further, the signal reading speed can be greatly increased. In addition, light leaked from the periphery enters the semiconductor layer constituting the switching element, and the reverse current is rapidly converged, and the peak value is also reduced. As a result, the switching speed of the switching element is improved. It is thought that it can be done. As described above, the present invention has various excellent effects.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

A semiconductor device for an original reader having a switching element such as a diode, an optical sensor element comprising a photoelectric conversion element and a switching element, and a switching element used in an image reader for inputting image information in a facsimile apparatus, an image scanner, and the like. In a semiconductor device (90) provided with a semiconductor element (blocking diode) (94) having a switching function and comprising a lower electrode (94a), a semiconductor layer (94b), an upper electrode (94c), all of which are formed vertically in this order; at least either one of the lower electrode (94a) and the upper electrode (94c) consists of one or more layers, and out of the conductive layers at least the one which is in contact with the semiconductor layer (94b) is transparent. An optical sensor element and an original document reader according to the present invention employ such semiconductor devices having switching function. In such a semiconductor device thus structured, the reverse direction current involved in switching elements such as blocking diodes and in optical sensor elements can be reduced, making it possible to enhance the switching speed, and to obtain exact signal output from the optical sensor element. Further, in an original document reader having these switching elements or optical sensor elements, inverted residual images can be reduced, and at the same time, the reading can be executed at a higher speed.

Description

明 細 書  Specification
半導体装置 技術分野 Semiconductor device technology
本発明は半導体装置に関し、 さらに詳しくは、 ガラスなどの基板上に 形成されるダイォードなどのスィツチング素子や、 光電変換素子とスィ ツチング素子とから構成される光センサ素子、 及びファクシミ リ、 ィメ 一ジスキャナなどにおいて、 画像情報を入力するための画像読み取り部 などに使用される原稿読み取り装置などの半導体装置に関する。  The present invention relates to a semiconductor device, and more particularly, to a switching element such as a diode formed on a substrate such as glass, an optical sensor element composed of a photoelectric conversion element and a switching element, and a facsimile and image sensor. The present invention relates to a semiconductor device such as a document reading device used in an image reading unit for inputting image information in a scanner or the like.
背景技術 - 近年、 ファクシミ リゃイメージスキャナなどの画像読み取り部には、 縮小光学系を必要とする C C D型の原稿読み取り装置に代わつて、 一般 に密着型ィメ一ジセンサと呼ばれる原稿読み取り装置が広く採用されて いる。 BACKGROUND ART-In recent years, image reading units, such as facsimile image scanners, have been widely replaced with document reading devices generally called contact image sensors, instead of CCD document reading devices requiring a reduction optical system. Has been adopted.
たとえば第 1 9図に示すように、 従来の原稿読み取り装置 1はガラス 基板 2上に、 光電変換素子であるフォ トダイォード 3と、 スィツチング 素子であるプロッキングダイオード 4 と、 フォ トダイオード 3からの電 気信号を読み出すためのチャンネル配線 C , . C 2. . . . C„ とが形成され て構成されている。 For example, as shown in FIG. 19, a conventional document reading apparatus 1 has a glass substrate 2 on which a photodiode 3 as a photoelectric conversion element, a blocking diode 4 as a switching element, and electricity from a photodiode 3 are arranged. channel interconnection C for reading an electrical signal,. C 2.... C "and is to be constituted by forming.
これらフォ トダイオード 3及びプロッキングダイォード 4は、 ともに 金属から成る不透明な下部電極 3 a , 4 aと、 アモルファスシリ コンか ら成る P i n構造の半導体層 3 b , 4 bと、 I T 0 ( Indi um Tin Oxi d e) から成る透明な上部電極 3 c , 4 cが、 順に堆積されて構成されて いる P また、 フォ トダイオード 3及びブロッキングダイオード 4は SiO から成る透明な層間絶縁膜 5により覆われていて、 この層間絶縁膜 5 に形成されたコンタク トホール 6を介して接続配線 7によって逆極性で 直列接続されている。 一方、 フォ トダイォード 3を構成する下部電極 3 aは、 層間絶縁膜 5に形成されたコンタク トホール 8を介してチャンネ ル配線 C L C S.... C„ に接続されている。 さらに、 これら全体は保護 膜 9により覆われている。 ここで、 ブロッキングダイオード 4の上部電 極 4 cが透明になっているのは、 フォ トダイォード 3の上部電極 3 c と 同時に堆積することによって製造工程を簡略化しているためである。 また、 これらフォ トダイオード 3及びブロッキングダイオード 4は、 第 2 0図に示すように一次元に mx n個配列され、 n個ごとに m個のブ ロック Β ,. Β2.... Βπ, に区分されていて、 プロッキングダイォード 4 のアノード電極はブロック Β B2.'... Bm 内で共通に接続され、 フォ トダイオード 3のアノード電極はチャンネル配線 C C 2.... C„ によ つてブロック Bし B2.... Βπ, 間で相対的に同一位置にあるもの同士で 共通に接続されている。 これらのブロッキングダイオード 4はフォ トダ ィォード 3をブロック Β ,. B2.... Bm 毎に順次選択するために必要な ものである。 The photodiode 3 and the blocking diode 4 are composed of opaque lower electrodes 3a and 4a, both made of metal, semiconductor layers 3b and 4b of amorphous silicon made of amorphous silicon, and IT0 ( Indi um Tin Oxi de) transparent upper electrode 3 c made of, 4 c is also P is configured by sequentially deposited, photodiode 3 and the blocking diode 4 is covered by a transparent interlayer insulating film 5 made of SiO This interlayer insulating film 5 Are connected in series by the connection wiring 7 via the contact hole 6 formed at the reverse polarity. On the other hand, the lower electrode 3a constituting the photodiode 3 is connected to the channel wirings CLC S .... C „through the contact holes 8 formed in the interlayer insulating film 5. The upper electrode 4c of the blocking diode 4 is transparent because it is deposited at the same time as the upper electrode 3c of the photodiode 3 to simplify the manufacturing process. there because it is. these photodiode 3 and the blocking diode 4, in a one-dimensional as shown in the second 0 Figure is mx n number sequence, m-number of blocks beta every n,. beta 2. ... Βπ, the anode electrode of the blocking diode 4 is connected in common within the block Β B 2 .'... B m , and the anode electrode of the photodiode 3 is connected to the channel wiring CC 2 .... by C „ Blocks B and B 2 .... Βπ, which are relatively connected at the same position. These blocking diode 4 follower Toda Iodo 3 blocks beta, which are necessary in order to sequentially select each. B 2 .... B m.
この原稿読み取り装置 1は電荷蓄積方式で動作するもので、 第 2 1図 のタイムチヤ一トに示すように、 駆動パルス Vp,. Vp2.... Vpra がプロッ ク 81. 82.... Bm ごとに順番に周期 Tで印加される。 この駆動パルス Vp,. Vp2.... Vpra が印加されているときは、 そのブロック Β ,. Β2.... Bm 内のブロッキングダイオード 4は順バイアスとなり、 フォ トダイォ ード 3は逆バイアスとなる。 このため、 フォ トダイオード 3の並列容量 は速やかに充電される。 この状態が読出状態である。 一方、 駆動パルス Vp,. Vp2.... Vpm が印加されていないときは、 そのブロック' Β ,. B2.... Bm 内のブロッキングダイオード 4は逆バイアスとなる。 したがって、 この間にフォ トダイォード 3に光が入射すると、 その光量に応じて生じ た光電流によってフォ トダイォ一ド 3の並列容量は放電される。.この状 態が蓄積状態である。 The document reading device 1 is intended to operate in a charge accumulation mode, as shown in Taimuchiya one bets second 1 view, the drive pulse Vp ,. Vp 2 .... Vp ra is plotted click 8 1. 8 2. ... applied in cycle T every B m . When these drive pulses Vp ,. Vp 2 .... Vpr are applied, the blocking diode 4 in the block Β,. Β 2 .... B m becomes forward-biased and the photodiode 3 Is reverse biased. Therefore, the parallel capacitance of the photodiode 3 is charged quickly. This state is a reading state. Meanwhile, when the drive pulse Vp ,. Vp 2 .... Vp m is not applied, the block 'Β,. B 2 .... blocking diode 4 in B m is reverse biased. Therefore, if light enters the photodiode 3 during this time, the parallel capacitance of the photodiode 3 is discharged by the photocurrent generated in accordance with the amount of light. This state The state is the accumulation state.
すなわち、 各プロック Β,. B2..., Bm は時間 tの読出状態と、 時間 T一 tの蓄積状態とを繰り返すことになる。 読出状態になったプロック Β,. B2.... Bm からは、 それまでの蓄積状態の間に入射した光量に相 当する出力電流 lout,. iout2.... Iout„ がチャンネル配線 Cし C 2. . . . Cn を経て流れ出し、 これら出力電流 lout,. Iout2.... Ioutn は外部の 信号処理回路によって増幅及び積分された後、 時系列的に出力されるこ とになる。 たとえば第 1ブロック B , が読出状態になると、 第 1プロッ ク B, から出力電流 loutし Iout2.... loutn が流れ出し、 次いで第 1ブ ロック B, が蓄積状態になって第 2ブロック B2 が読出状態になると、 第 2ブロック B2 から出力電流 lout,. Iout2.... Iout„ が流れ出すこと になる。 That is, each block Β, .B 2 ..., B m repeats the reading state at time t and the accumulation state at time T-t. From the block 読 出,. B 2 .... B m in the read state, the output current lout,. Iout 2 .... Iout „corresponding to the amount of light incident during the accumulation state up to that point is the channel. Wiring C then flows out through C 2 .... C n , and these output currents lout, Iout 2 .... Iout n are amplified and integrated by an external signal processing circuit, and then output in time series For example, when the first block B, is in the read state, the output current lout flows out of the first block B, Iout 2 .... lout n , and then the first block B, is in the accumulation state. is second block B 2 to the becomes a read state, the output current lout ,. Iout 2 .... Iout "flows out it from the second block B 2.
しかしながら実際は、 ブロック Β,. B2.... Bm が読出状態から蓄積 状態に切り換わった直後には、 出力電流 lout!. Iout2.... Iout„ と逆方 向に電流 (以下 「逆方向電流」 という。 なお、 「逆方向電流」 を 「逆方 向回復電流」 ともいう。 ) ΙΙ . ΙΓ2.... Irn が流れる。 この逆方向電流 Ir,. Ir2.... Irn の大きさは正常な出力電流 lout,. Iout2.... Ioutn の 1 0〜20%に達し、 その収束時間 Tr は 1 0 -3秒のオーダーにも達す る。 このため、 たとえば第 1ブロック Β, と第 2ブロック Β2 とで白が 読み取られ、 第 3ブロック Β3 で黒が読み取られた場合には、 第 2プロ ック Β2 が読出状態になったときに流れる出力電流 lout,. Iout2.... Io utn は通常よりも逆方向電流 Ir,. Ir2.... Ir„ の分だけ小さくなり、 さ らに第 3ブロック B3 が読出状態になったときには流れないはずの出力 電流 lout,. Iout2.... Ioutn が逆方向電流 ΙΙ . Ir2.... Irn の分だけ逆 方向に流れることになる。 However, in practice, immediately after the block Β ,. B 2 .... B m switches from the read state to the accumulation state, the output current lout !. Iout 2 .... Iout 電流referred to as a "reverse current". it should be noted, also referred to as a "reverse current""reverse direction recovery current".) ΙΙ. ΙΓ 2 .... Ir n flows. The magnitude of this reverse current Ir ,. Ir 2 .... Ir n reaches 10 to 20% of the normal output current lout ,. Iout 2 .... Iout n , and the convergence time Tr is 10 -In the order of 3 seconds. Thus, white is read, for example the first block beta, and the second block beta 2, if the black in the third block beta 3 has been read, the second pro click beta 2 becomes read state the output current lout ,. Iout 2 .... Io ut n reverse current than the normal Ir ,. Ir 2 .... Ir "minute only decreases, and et to the third block B 3 which flows when the output current lout ,. Iout 2 .... Iout n that should not flow flows to the amount corresponding reverse reverse current ΙΙ. Ir 2 .... Ir n when it is read state.
このような現象は再生画像において、 白を読み取った直後に読み取つ た黒は通常の黒よりも黒く、 黒を読み取った直後に読み取った白は通常 の白よりも白くなつて現れるため、 「反転残像」 と呼ばれている。 特に. 第 1ブロック B , で白が読み取られ、 第 2ブロック B 2 で灰 (白の 1 0 〜? 0 %の明るさ) が読み取られた場合には、 第 2ブロック B 2 からの 出力電流 l ou t , . I ou t 2. . . . I ou t„ は黒を示すことになるなど、 正確な信 号出力は得られなかった。 また、 消費電力の低減などを図るため低照度 下で原稿を読み取らせる傾向にあるが、 低照度下でも反転残像の大きさ は低下せず、 信号出力の大きさだけが低下するので、 反転残像の相対的 割合は増加するという問題があつた。 このような状態を可能な限り回避 するため、 駆動パルス VP L VP S. . . . Vpm の幅 tを長めに取る必要がある カ^ 信号読み出し速度が遅くなるという問題があった。 This phenomenon is caused by the fact that in a reproduced image, black read immediately after reading white is blacker than normal black, and white read immediately after reading black is It is called “reversed afterimage” because it appears whiter than white. In particular. The first block B, in white is read, if the ash (1 0 -? 0% brightness of white) is read in the second block B 2, the output current from the second block B 2 l ou t,. I ou t 2.... I ou t " etc. would indicate black, were not accurate signal output obtained. Further, under low illumination order to like reduction in power consumption However, there is a problem that the relative ratio of the reversal afterimage increases because the size of the reversal afterimage does not decrease even under the low illuminance, and only the signal output decreases. to avoid as much as possible this state, the driving pulse VP L VP S.... Vp Ca ^ signal reading speed that must take a longer width t of m is disadvantageously delayed.
この逆方向電流の原因は、 プロッキングダイォード 4にかかる電圧が 順バイアスから逆バイアスに変化させられても、 順バイアス時に注入さ れたキヤリアは瞬時には消失せず、 一定時間だけ逆方向に流れるためと 考えられる。 すなわち、 ブロッキングダイオード 4のスイッチング速度 はこの逆方向電流によって制限を受けていると考えられる。  The cause of this reverse current is that even if the voltage applied to the blocking diode 4 is changed from forward bias to reverse bias, the carrier injected during forward bias does not disappear instantaneously, It is thought that it flows to. That is, it is considered that the switching speed of the blocking diode 4 is limited by the reverse current.
そこで本発明者らは、 一般にプロッキングダイォードなどのスィツチ ング素子やそれを含む光センサ素子に伴う逆方向電流を低減することに より、 そのスイッチング速度を向上させるとともに、 光センサ素子から の正確な信号出力が得られるようにし、 さらに、 これらスイッチング素 子又は光センサ素子を有する原稿読み取り装置にあっては、 反転残像を 低減するとともに、 より高速読み出しを可能にするため、 鋭意研究を重 ねた結果、 本発明に至った。 発明の開示  Therefore, the present inventors generally improve the switching speed by reducing the reverse current associated with a switching element such as a blocking diode and an optical sensor element including the same, and improve the accuracy of the optical sensor element. In order to obtain a high signal output, and to provide a document reading device having these switching elements or optical sensor elements, intensive research has been conducted to reduce reversal afterimages and to enable higher-speed reading. As a result, the present invention has been achieved. Disclosure of the invention
本発明に係る半導体装置の要旨とするところは、 下部電極と、 半導体 層と、 上部 m極とが順に積層されて構成されるスィツチング機能を有す る半導体素子を 1又は複数備えた半導体装置において、 前記下部電極及 び上部電極のうち少なく ともいずれか一方が 1層又は 2層以上の導電層 から成り、 且つ少なく とも半導体層と接する導電層が透明導電層から成 ることにある。 The gist of the semiconductor device according to the present invention is to provide a semiconductor device including one or more semiconductor elements having a switching function and configured by sequentially stacking a lower electrode, a semiconductor layer, and an upper m-pole. The lower electrode and At least one of the upper electrode and the upper electrode may be formed of one or more conductive layers, and at least the conductive layer in contact with the semiconductor layer may be formed of a transparent conductive layer.
かかる半導体装置において、 前記スィツチング機能を有する半導体素 子と、 下部電極と半導体層と上部電極とが順に積層されて成る光電変換 素子とが直列接続されて構成される光センサ素子を 1又は複数備えたこ とにある。  In this semiconductor device, one or a plurality of optical sensor elements configured by serially connecting the semiconductor element having the switching function and a photoelectric conversion element in which a lower electrode, a semiconductor layer, and an upper electrode are sequentially stacked are provided. It is here.
また、 かかる半導体装置において、 前記スイッチング機能を有する半 導体素子と、 下部電極と半導体層と上部電極とが順に積層されて成る光 電変換素子とが直列接続されて構成される光センサ素子が一次元に複数 配列され、 一定個数ごとに複数のプロックに区分されているとともに、 これら光センサ素子のいずれか一方がプロック内で共通に接続され、 当 該他方がチャンネル配線によって該ブロック間で相対的に同一位置にあ るもの同士で共通に接続されていることにある。  Further, in this semiconductor device, a semiconductor element having the switching function and an optical sensor element configured by serially connecting a photoelectric conversion element in which a lower electrode, a semiconductor layer, and an upper electrode are sequentially stacked are connected to a primary element. A plurality of optical sensor elements are originally arranged and divided into a plurality of blocks by a certain number, and one of these optical sensor elements is commonly connected in the block, and the other is relatively connected between the blocks by channel wiring. That is, they are commonly connected to each other at the same position.
更に、 かかる半導体装置であって、 少なく とも前記スイッチング機能 を有する半導体素子を 1又は複数備えた半導体装置において、 該半導体 素子の下部電極及び上部電極のうち少なく ともいずれか一方が透明導電 層から成ることにある。  Further, in such a semiconductor device, at least one of a lower electrode and an upper electrode of the semiconductor device is provided with at least one semiconductor element having the switching function, and the semiconductor element includes a transparent conductive layer. It is in.
また、 かかる半導体装置であって、 少なく とも前記スイッチング機能 を有する半導体素子を 1又は複数備えた半導体装置において、 該半導体 素子の透明導電層が I T Oから成ることにある。  Further, in such a semiconductor device, in a semiconductor device provided with at least one or more semiconductor elements having the switching function, the transparent conductive layer of the semiconductor element is made of ITO.
更に、 かかる半導体装置であって、 少なく とも前記スイッチング機能 を有する半導体素子を 1又は複数備えた半導体装置において、 該半導体 素子の半導体層のうち、 少なく とも該透明導電層と接する半導体層が p 型半導体層であることにある。  Further, in such a semiconductor device, at least one or more semiconductor elements having the switching function, wherein at least a semiconductor layer in contact with the transparent conductive layer among semiconductor layers of the semiconductor element is a p-type. It is a semiconductor layer.
また、 かかる半導体装置であって、 少なく とも前記スイッチング機能 を有する半導体素子を 1又は複数備えた半導体装置において、 該半導体 素子の半導体層はプラズマ C V D法で連続的に堆積された水素化ァモル ファスシリコンから成り、 且つ p i n構造にされていることにある。 次に、 かかる半導体装置であって、 前記スイッチング機能を有する半 導体素子と前記光電変換素子とはそれぞれダイォード特性を備え、 互い の力ソード電極で直列接続されていることにある。 Further, in such a semiconductor device, at least one or more semiconductor elements having the switching function are provided. The semiconductor layer of the device consists of amorphous silicon hydride deposited continuously by plasma CVD and has a pin structure. Next, in such a semiconductor device, the semiconductor element having the switching function and the photoelectric conversion element each have a diode characteristic, and are connected in series with each other by force source electrodes.
また、 かかる半導体装置において、 前記スイッチング機能を有する半 導体素子及び前記光電変換素子を構成するそれぞれの下部電極、 半導体 層及び上部電極は、 それぞれ同時に堆積されたものであることにある。 更に、 かかる半導体装置において、 前記スイッチング機能を有する半 導体素子及び前記光電変換素子とが直列接続されて構成される光センサ 素子を 1又は複数備えた半導体装置において、 光入射側とは反対側に位 置する下部電極及び上部電極のいずれか一方が、 少なく とも半導体層と 接して透明導電層により構成されていることにある。 かかる半導体装置における作用は理論的に解明されていないが、 下部 電極若しくは上部電極又はこれらの双方が 1層又は 2層以上の導電層か ら成り、 且つ少なく とも半導体層と接する導電層が I T Oなどの透明導 電層から構成されていて、 半導体層と透明導電層との界面が形成されて いる。 この界面には、 電位障壁や、 透明導電層を構成する物質が半導体 層に拡散して生じたトラップ準位などのバリァが形成されていると考え られる。 したがって、 半導体装置にかかる電圧が順バイアスから逆バイ ァスに変化させられたときでも、 順バイアス時に注入されたキャリアの ほとんどはこのバリアによって阻止されると考えられる。 その結果、 逆 方向電流は急速に収束させられ、 かつ、 そのピーク値も小さくなり、 ス イッチング速度が向上させられるものと推定される。  Further, in such a semiconductor device, the semiconductor device having the switching function and the respective lower electrode, semiconductor layer, and upper electrode constituting the photoelectric conversion element are simultaneously deposited. Further, in such a semiconductor device, in a semiconductor device provided with one or a plurality of optical sensor elements configured by connecting the semiconductor element having the switching function and the photoelectric conversion element in series, At least one of the lower electrode and the upper electrode to be disposed is constituted by a transparent conductive layer at least in contact with the semiconductor layer. Although the operation of such a semiconductor device has not been theoretically elucidated, the lower electrode or the upper electrode or both of them consist of one or more conductive layers, and at least the conductive layer in contact with the semiconductor layer is made of ITO or the like. And an interface between the semiconductor layer and the transparent conductive layer is formed. It is considered that a barrier such as a potential level and a trap level generated by diffusing the material constituting the transparent conductive layer into the semiconductor layer are formed at this interface. Therefore, even when the voltage applied to the semiconductor device is changed from the forward bias to the reverse bias, most of the carriers injected during the forward bias are considered to be blocked by the barrier. As a result, it is presumed that the reverse current is rapidly converged, and its peak value is also reduced, thereby improving the switching speed.
なお.、 かかる半導体装置の作用の他の理論的推定によれば、 下部.電極 若しくは上部電極又はこれらの双方が 1層又ば.2層以上の導電層から成 り、 且つ少なく とも半導体層と接する導電層が I T Oなどの透明導電層 から構成されていて、 透明であるので、 周辺から漏れてきた光は下部電 極や上部電極を透過して半導体層に入射する。 これにより、 半導体層に おける再結合準位が増加し、 再結合速度が速くなる。 したがって、 半導 体装置にかかる電圧が順バイアスから逆バイアスに変化させられたとき でも、 順バイアス時に注入されたキャリアは再結合により速やかに消失 すると考えられる。 その結果、 逆方向電流は急速に収束させられ、 かつ、 そのピーク値も小さくなり、 スィツチング速度が向上させられることに なるものと推定される。 According to another theoretical estimation of the operation of such a semiconductor device, the lower electrode or the upper electrode or both of them are composed of one or more conductive layers. In addition, since at least the conductive layer in contact with the semiconductor layer is made of a transparent conductive layer such as ITO, and is transparent, light leaking from the periphery passes through the lower electrode and upper electrode and enters the semiconductor layer. I do. Thereby, the recombination level in the semiconductor layer is increased, and the recombination speed is increased. Therefore, even when the voltage applied to the semiconductor device is changed from the forward bias to the reverse bias, it is considered that the carriers injected at the time of the forward bias quickly disappear by recombination. As a result, it is presumed that the reverse current is rapidly converged, and the peak value is also reduced, so that the switching speed is improved.
次に、 かかるスィツチング機能を有する半導体素子と光電変換素子と から構成される光センサ素子などの半導体装置によれば、 スイッチング 機能を有する半導体素子を構成する下部電極若しくは上部電極又は.これ らの双方が 1層又は 2層以上の導電層から成り、 且つ少なく とも半導体 層と接する導電層が I T Oなどの透明導電層から構成されている。 した がって、 このスィツチング機能を有する半導体素子は上記推定される作 用を行なう。 この結果、 逆方向電流は急速に収束させられ、 かつ、 その ピーク値も小さくなる。 よって、 この光センサ素子からは正確な信号出 力が得られるとともに、 そのスィツチング速度も向上させられる。  Next, according to a semiconductor device such as an optical sensor element composed of a semiconductor element having such a switching function and a photoelectric conversion element, a lower electrode or an upper electrode or both of the semiconductor elements having a switching function are formed. Comprises one or more conductive layers, and at least the conductive layer in contact with the semiconductor layer comprises a transparent conductive layer such as ITO. Therefore, the semiconductor device having the switching function performs the above-described presumed operation. As a result, the reverse current is rapidly converged, and its peak value is also reduced. Therefore, an accurate signal output can be obtained from the optical sensor element, and the switching speed can be improved.
更に、 かかるスィツチング機能を有する半導体素子と光電変換素子を 備えた原稿読み取り装置などの半導体装置によれば、 スィツチング機能 を有する半導体素子を構成する下部電極若しくは上部電極又はこれらの 双方が 1層又は 2層以上の導電層から成り、 且つ少なく とも半導体層と 接する導電層が I T Oなどの透明導電層から構成されている。 したがつ て、 このスィツチング機能を有する半導体素子は上記推定さ る作用を 行なう。 これにより、 逆方向電流が急速に収束させられ、 かつ、 そのピ —ク値も小さくなり、 スィツチング素子のスイッチング速度が向上させ られる。 この結果、 原稿読み取り装置などの半導体装置は、 反転残像が 低減させられ、 信号読み出し速度は大幅に速められる。 図面の簡単な説明 Further, according to a semiconductor device such as a document reading device provided with a semiconductor element having the switching function and a photoelectric conversion element, the lower electrode or the upper electrode, or both of them, which constitute the semiconductor element having the switching function, is formed of one layer or two layers. At least the conductive layer in contact with the semiconductor layer is composed of a transparent conductive layer such as ITO. Therefore, the semiconductor element having the switching function performs the above-described estimated operation. As a result, the reverse current is rapidly converged, and the peak value is reduced, so that the switching speed of the switching element is improved. As a result, a semiconductor device such as a document reading device has a reverse image lag. The signal readout speed is greatly increased. BRIEF DESCRIPTION OF THE FIGURES
第 1図は本発明に係る半導体装置であるスィツチング素子の一実施例 を示す断面模式図であり、 第 2図、 第 3図、 第 4図、 第 5図、 第 6図及 び第 7図はいずれも本発明に係る半導体装置であるスィツチング素子の 他の実施例を示す断面模式図である。  FIG. 1 is a schematic cross-sectional view showing one embodiment of a switching element which is a semiconductor device according to the present invention. FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, and FIG. 7 is a schematic cross-sectional view showing another embodiment of a switching element which is a semiconductor device according to the present invention.
第 8図は本発明に係る半導体装置である光センサ素子の一実施例を示 す断面模式図であり、 第 9図(a) (b)は第 8図に示した光センサ素子の動 作を説明するための回路図である。 第 1 0図、 第 1 1図及び第 1 2図は いずれも本発明に係る半導体装置である光センサ素子の他の実施例を示 す断面模式図である。  FIG. 8 is a schematic cross-sectional view showing one embodiment of an optical sensor element which is a semiconductor device according to the present invention. FIGS. 9 (a) and 9 (b) show the operation of the optical sensor element shown in FIG. FIG. 6 is a circuit diagram for explaining the operation of the embodiment. FIGS. 10, 11, and 12 are schematic cross-sectional views showing other embodiments of the optical sensor element which is the semiconductor device according to the present invention.
第 1 3図は本発明に係る半導体装置である原稿読み取り装置の一実施 例を示す断面模式図であり、 第 1 4図は第 1 3図に示した原稿読み取り 装置の一部平面図である。 第 1 5図は本発明の効果を確認するために行 なつた比較実験の結果を示すもので、 実際に作製した原稿読み取り装置 の出力電圧を示すグラフである。 第 1 6図、 第 1 7図及び第 1 8図はい ずれも本発明に係る半導体装置である原稿読み取り装置の他の実施例を 示す断面模式図である。  FIG. 13 is a schematic cross-sectional view showing one embodiment of a document reading apparatus which is a semiconductor device according to the present invention, and FIG. 14 is a partial plan view of the document reading apparatus shown in FIG. . FIG. 15 shows the results of a comparative experiment conducted to confirm the effect of the present invention, and is a graph showing the output voltage of an original manuscript reading apparatus actually manufactured. FIG. 16, FIG. 17, and FIG. 18 are all schematic cross-sectional views showing another embodiment of the document reading apparatus which is a semiconductor device according to the present invention.
第 1 9図は従来の半導体装置である原稿読み取り装置の一例を示す断 面模式図であり、 第 2 0図は第 1 9図に示した原稿読み取り装置の回路 図である。 また、 第 2 1図は第 1 9図及び第 2 0図に示した原稿読み取 り装置の動作を説明するためのタイムチヤ一トである。 発明を実施するための最良の形態  FIG. 19 is a schematic sectional view showing an example of a document reading apparatus which is a conventional semiconductor device. FIG. 20 is a circuit diagram of the document reading apparatus shown in FIG. FIG. 21 is a time chart for explaining the operation of the original reading apparatus shown in FIGS. 19 and 20. BEST MODE FOR CARRYING OUT THE INVENTION
次に、 本発明に係る半導体装置の実施例について図面に基づき詳しく 説明する。 まず、 本発明に係る半導体装置をスイッチング機能を有する 半導体素子であるスイッチング素子を例にして説明する。 Next, embodiments of the semiconductor device according to the present invention will be described in detail with reference to the drawings. First, the semiconductor device according to the present invention has a switching function. A description will be given using a switching element as a semiconductor element as an example.
第 1図に示すように、 本発明に係るスイッチング素子 1 0はガラスな どから成る基板 1 2上に、 I TO (Indium Tin Oxide) などから成る透 明な下部電極 1 4と、 アモルファスシリ コンなどから成る半導体層 1 6 と、 上部電極 1 8とが形成されて構成されている。 ここで半導体層 1 6 は、 基板 1 2側から順に、 正孔が多数キャリアとなる p型アモルファス シリコン層 1 6 aと、 真性半導体となる i型アモルファスシリコン層 1 6 bと、 電子が多数キヤリアとなる n型アモルファスシリコン層 1 6 c とが積層され、 p i n構造にされている。  As shown in FIG. 1, a switching element 10 according to the present invention includes a transparent lower electrode 14 made of ITO (Indium Tin Oxide) and an amorphous silicon on a substrate 12 made of glass or the like. A semiconductor layer 16 made of such as above and an upper electrode 18 are formed. Here, the semiconductor layer 16 includes, in order from the substrate 12 side, a p-type amorphous silicon layer 16 a in which holes serve as majority carriers, an i-type amorphous silicon layer 16 b in which an intrinsic semiconductor is provided, and a large number of carriers. An n-type amorphous silicon layer 16 c is laminated to form a pin structure.
このスイッチング素子 1 0を製造するには、 まず基板 1 2上に電子ビ —ムゃ抵抗加熱による真空蒸着法、 あるいは DCや R Fによるスパッ夕 リング法などによって I TOなどの透明導電膜 ( 1 4) を堆積する。 さ らにこの上に、 プラズマ CVD法などによって、 p型アモルファスシリ コン膜 ( 1 6 a) と、 i型アモルファスシリコン膜 ( 1 6 b) と、 n型 アモルファスシリコン膜 ( 1 6 c) とを連続的に堆積する。 そして再度 この上に、 真空蒸着法やスパッ夕リング法などによって I TOなどの透 明導電膜 ( 1 8) を堆積する。 なお、 これら透明導電膜 ( 1 4, 1 8) の膜厚はそれぞれ数百〜数千 A程度が好ましいが、 堆積するァモルファ スシリコン膜の性能や透明導電膜の特性などを考慮して適宜決定される ものである。  To manufacture the switching element 10, first, a transparent conductive film (14) such as ITO is formed on the substrate 12 by a vacuum evaporation method using electron beam resistance heating or a sputtering method using DC or RF. ) Is deposited. Further, a p-type amorphous silicon film (16a), an i-type amorphous silicon film (16b), and an n-type amorphous silicon film (16c) are formed thereon by a plasma CVD method or the like. Deposits continuously. Then, a transparent conductive film (18) such as ITO is deposited thereon again by a vacuum evaporation method or a sputtering method. The thickness of each of these transparent conductive films (14, 18) is preferably about several hundreds to several thousand A, but is appropriately determined in consideration of the performance of the deposited amorphous silicon film and the characteristics of the transparent conductive films. It is what is done.
次いで、 これらの膜を順にパターン化することによって、 下部電極 1 4と半導体層 1 6と上部電極 1 8とを形成する。 たとえばフォ トリソグ ラフィ法によってパターン化する場合は、 まず最上層の透明導電膜 ( 1 8)上にレジスト液を塗布し、 プリべークをした後、 所定のパターンが 刻まれたマスクを用いて露光を行ない、 さらに現像及びポストべークを 行なう。 そして、 透明導電膜として I TOを用いた場合であれば塩 と 硝酸の混合液によってその透明導電膜をエッチングし、 上部電極 1 8を 形成する。 次に、 平行平板型のエッチング装置を用いてアモルファスシ リコン膜 ( 1 6 a , 1 6 b, 1 6 c ) をエッチングする。 すなわち、 チ ヤンバー内を 1 0 -3Torr以下まで排気した後、 CF4 ガスと 02 ガスとを 導入し、 さらに圧力を 5. 0 P aに保持しながら 1 3. 5 6 MH zの高 周波電源を用いて電極に 0. 1〜0. 7W/cm2 の電力を供給する。 このようにしてアモルファスシリコン膜をエッチングし、 半導体層 1 6 を形成するのである。 そして、 パターニングに用いたレジストを一旦除 去した後、 前述した最上層の透明導電膜 ( 1 8 ) と同様に、 最下層の透 明導電膜 ( 1 4 ) もフォ トリソグラフィ法などによってパターン化し、 下部電極 1 4を形成すれば、 下部電極 1 4 と半導体層 1 6 と上部電極 1 8とから構成されるスイッチング素子 1 0が製造されることになる。 ここでは、 フォ ト リ ソグラフィ法によって下部電極 1 4 と半導体層 1 6と上部電極 1 8とを形成する方法を例示したが、 マスク法などによつ て最初から不必要な部分には膜が堆積されないようにして形成してもよ いなど、 その製造方法は何ら限定されるものではない。 Next, the lower electrode 14, the semiconductor layer 16, and the upper electrode 18 are formed by sequentially patterning these films. For example, in the case of patterning by photolithography, a resist solution is first applied on the uppermost transparent conductive film (18), pre-baked, and then a mask with a predetermined pattern is used. Exposure is performed, followed by development and post baking. If ITO is used as the transparent conductive film, the transparent conductive film is etched with a mixed solution of salt and nitric acid to form the upper electrode 18. Form. Next, the amorphous silicon films (16a, 16b, 16c) are etched using a parallel plate type etching apparatus. That is, the switch Yanba 1 0 - was evacuated to 3 Torr or less, introducing a CF 4 gas and 0 2 gas, 1 3. 5 6 MH z height while maintaining further pressure 5. 0 P a A power of 0.1 to 0.7 W / cm 2 is supplied to the electrodes using a frequency power supply. Thus, the amorphous silicon film is etched to form the semiconductor layer 16. After the resist used for patterning is once removed, the lowermost transparent conductive film (14) is patterned by photolithography or the like in the same manner as the above-mentioned uppermost transparent conductive film (18). When the lower electrode 14 is formed, the switching element 10 including the lower electrode 14, the semiconductor layer 16 and the upper electrode 18 is manufactured. Here, the method of forming the lower electrode 14, the semiconductor layer 16, and the upper electrode 18 by photolithography has been exemplified. However, a film is formed in an unnecessary portion from the beginning by a mask method or the like. The manufacturing method is not limited at all, for example, it may be formed so as not to be deposited.
このスイッチング素子 1 0は下部電極 1 4及び上部電極 1 8が透明導 電層から構成され、 半導体層 1 6と透明導電層である下部電極 1 4及び 上部電極 1 8、 特に下部電極 1 4 との接合部に界面が形成されている。 この界面には電位障壁や、 透明導電層を構成する物質が半導体層 1 6に 拡散して生じたトラップ準位などのバリアが形成されていると考えられ る。 したがって、 スイッチング素子にかかる電圧が順パ'ィァスから逆バ ィァスに変化させられたときでも、 順バイアス時に注入されたキヤリァ のほとんどはこのバリアによって阻止されると考えられる。 これにより、 逆方向電流は 1 0 -5〜 1 0 _6秒のオーダーで収束させられ、 かつ、 その ピーク値も小さくなり、 スイッチング速度が向上させられるものと推定 される。 そこで、 このスイッチング素子 1 0を原稿^み取り装置に使用 すれば、 より正確な信号出力を得ることができ、 さらに信号読み出し速 度を速めることも可能である。 In the switching element 10, the lower electrode 14 and the upper electrode 18 are formed of a transparent conductive layer, and the semiconductor layer 16 and the lower electrode 14 and the upper electrode 18 which are transparent conductive layers, particularly the lower electrode 14 are formed. An interface is formed at the junction. It is considered that a potential barrier and a barrier such as a trap level formed by diffusing the material constituting the transparent conductive layer into the semiconductor layer 16 are formed at this interface. Therefore, even when the voltage applied to the switching element is changed from a forward bias to a reverse bias, most of the carriers injected during the forward bias are considered to be blocked by this barrier. Thus, reverse current 1 0 - 5 to be made to converge on the order of 1 0 _ 6 seconds, and the peak value becomes small, it is estimated that the switching speed is improved. Therefore, if this switching element 10 is used in a document reading device, a more accurate signal output can be obtained, and the signal reading speed can be further improved. It is also possible to increase the speed.
なお、 このスイッチング素子 1 0の作動を他の推定的理論により説明 すれば、 下部電極 1 4及び上部電極 1 8が透明で、 周辺からの漏光がこ れらを透過して半導体層 1 6に入射する。 これにより、 アモルファスシ リコンから成る半導体層 1 6には多数のトラップ準位が存在していて、 この半導体層 1 6に光が入射すると、 これらのトラップ準位が変化して 再結合準位が増加すると考えられる。 このため、 再結合速度が速くなり、 スィツチング素子 1 0にかかる電圧が順バイアスから逆バイアスに変化 させられたときでも、 順バイアス時に注入されたキャリアは再結合によ つて速やかに消失すると考えられる。 このため、 逆方向電流は 1 0 〜 1 0 - 6秒のオーダーで収束させられ、 かつ、 そのピーク値も小さくなり、 スィツチング速度が向上させられるものと推定される。 If the operation of the switching element 10 is explained by another presumed theory, the lower electrode 14 and the upper electrode 18 are transparent, and light leakage from the surroundings penetrates these to the semiconductor layer 16. Incident. As a result, a large number of trap levels exist in the semiconductor layer 16 made of amorphous silicon, and when light enters the semiconductor layer 16, these trap levels change and the recombination level changes. It is expected to increase. Therefore, the recombination speed is increased, and even when the voltage applied to the switching element 10 is changed from the forward bias to the reverse bias, the carriers injected at the time of the forward bias are considered to be quickly lost by the recombination. . Thus, reverse current 1 0-1 0 - allowed to converge on the order of 6 seconds, and the peak value becomes small, it is estimated that Suitsuchingu speed is improved.
以上、 本発明に係るスイッチング素子の一実施例を詳述したが、 本発 明は上述した実施例に限定されることなく、 その他の態様でも実施し得 るものである。  As described above, one embodiment of the switching element according to the present invention has been described in detail. However, the present invention is not limited to the above-described embodiment, and can be implemented in other aspects.
たとえば第 2図に示すように、 ガラスなどの基板 1 2上に、 I T Oな どから成る透明な下部電極 1 4 と、 i型アモルファスシリコン層だけか ら成る半導体層 2 0と、 金属などから成る不透明な上部電極 2 2とが形 成されて構成されたスィツチング素子 2 4でもよい。 このスイッチング 素子 2 4では、 i型アモルファスシリコン層 ( 2 0 ) と下部電極 1 4と の界面でショッ トキ一バリア一が形成されていて、 上述と同様に作動さ せられることになる。  For example, as shown in FIG. 2, a transparent lower electrode 14 made of ITO or the like, a semiconductor layer 20 made only of an i-type amorphous silicon layer, and a metal A switching element 24 formed by forming an opaque upper electrode 22 may be used. In this switching element 24, a short-circuit barrier is formed at the interface between the i-type amorphous silicon layer (20) and the lower electrode 14, and the switching element 24 is operated in the same manner as described above.
また第 3図に示すように、 ガラスなどの基板 1 2上に、 I T Oなどか ら成る透明な下部電極 1 4 と、 型アモルファスシリコン層 2 6 aと i 型アモルファスシリ コン層 2 6 bとが積層されて成る半導体層 2 6 と、 金属な.どから成る不透明な上部電極 2 2とが形成されて構成されたスィ ツチング素子 2 8でもよい。 本例から明らかなように、 半導体層は p i 構造にされていてもよい。 As shown in FIG. 3, a transparent lower electrode 14 made of ITO or the like, a type amorphous silicon layer 26a and an i-type amorphous silicon layer 26b are formed on a substrate 12 made of glass or the like. The switching element 28 may be configured by forming a stacked semiconductor layer 26 and an opaque upper electrode 22 made of metal or the like. As is clear from this example, the semiconductor layer is pi It may be structured.
さらに第 4図に示すように、 ガラスなどの基板 1 2上に、 I T Oなど から成る透明な下部電極 1 4 と、 絶縁層 3 0 と、 i型アモルファスシリ コン層 3 2 aと p型アモルファスシリコン層 3 2 bとが積層されて成る 半導体層 3 2と、 金属などから成る不透明な上部電極 2 2とが形成され て構成されたスィツチング素子 3 4でもよい。 このスィツチング素子 3 4は M I S (Metal-Insulator- Semiconductor) 型になっていて、 半導体 層 3 2は下部電極 1 4上に薄い絶縁層 3 0を介して堆積されている。 本 例から明らかなように、 半導体層は下部電極上に直接でなく間接に堆積 されていてもよく、 その他の各層についても同様である。  Further, as shown in FIG. 4, a transparent lower electrode 14 made of ITO or the like, an insulating layer 30, an i-type amorphous silicon layer 32 a and a p-type amorphous silicon A switching element 34 formed by forming a semiconductor layer 32 formed by laminating the layers 32b and an opaque upper electrode 22 made of metal or the like may be used. The switching element 34 is of a metal-insulator-semiconductor (MIS) type, and the semiconductor layer 32 is deposited on the lower electrode 14 via a thin insulating layer 30. As is clear from this example, the semiconductor layer may be deposited indirectly instead of directly on the lower electrode, and the same applies to other layers.
以上、 下部電極 1 4を透明にする実施例を説明したが、 本発明におい ては、 透明にする電極は下部電極でも上部電極でもよく、 さらに双方と も透明にしてもよい。 すなわち、 下部電極及び上部電極のうち少なく と もいずれか一方が透明であればよいのである。  Although the embodiment in which the lower electrode 14 is made transparent has been described above, in the present invention, the electrode to be made transparent may be the lower electrode or the upper electrode, or both may be made transparent. That is, it is only necessary that at least one of the lower electrode and the upper electrode is transparent.
次に、 本発明に係る半導体装置であるスィツチング素子の下部電極若 しくは上部電極又は双方の電極が 1層以上の金属層と、 その金属層の上 に堆積される透明導電層とから構成されるものであってもよい。  Next, the lower electrode or the upper electrode or both electrodes of the switching element, which is the semiconductor device according to the present invention, comprises one or more metal layers and a transparent conductive layer deposited on the metal layers. May be used.
たとえば第 5図に示すように、 スイッチング素子 3 6は基板 1 2上に、 二層構造の下部電極 3 8と、 アモルファスシリコンなどから成る半導体 層 1 6と、 上部電極 1 8とが形成されて構成されている。 この二層構造 の下部電極 3 8は、 クロム Crなどから成る金属層 3 8 aと、 この金属層 3 8 a上に堆積される I T Oなどから成る透明導電層 3 8 bとから構成 されている。 また、 この半導体層 1 6は p i n構造あるいは n i p構造 のいずれでもよいが、 基板 1 2側から順に、 正孔が多数キャリアとなる p型アモルファスシリコン層 1 6 aと、 真性半導体となる i型ァモルフ ァスシリコン層 1 6 bと、 電子が多数キヤリアとなる n型アモルファス シリコン層 1 6 cとが積層された、 p i n構造が好ましい。 このスイッチング素子 1 0を製造するには、 まず基板 1 2上に、 電子 ビームや抵抗加熱による真空蒸着法、 あるいは D Cや R Fによるスパッ 夕リング法などによってクロム Crなどの金属膜 ( 3 8 a ) を堆積する。 次いでこの上に、 真空蒸着法やスパッ夕リング法などによって I T Oな どの透明導電膜 ( 3 8 b ) を堆積する。 その後は、 前述の実施例と同様 にして、 p型アモルファスシリコン膜、 i型アモルファスシリコン膜、 n型アモルファスシリコン膜を連続的に堆積した後、 この上に導電膜を 堆積する。 次いで、 上層の導電膜と、 3層から成るアモルファスシリコ ン膜と、 下層の透明導電膜とを順に所定形状にパターン化し、 上部電極 1 8と、 半導体層 1 6と、 下部電極 3 8の一部である透明導電層 3 8 b とを形成する。 次に、 パターニングに用いたレジストを一旦除去した後、 再びフォ トリソグラフィ法などによって金属膜を別の所定形状にパター ン化し、 下部電極 3 8の一部である金属層 3 8 aを形成することにより、 下部電極 3 8 と半導体層 1 6と上部電極 1 8とから構成されるスィツチ ング素子 3 6が製造されることになる。 For example, as shown in FIG. 5, the switching element 36 has a lower electrode 38 having a two-layer structure, a semiconductor layer 16 made of amorphous silicon or the like, and an upper electrode 18 formed on a substrate 12. It is configured. The lower electrode 38 of this two-layer structure is composed of a metal layer 38a made of chromium Cr or the like and a transparent conductive layer 38b made of ITO or the like deposited on the metal layer 38a. . The semiconductor layer 16 may have either a pin structure or a nip structure. From the substrate 12 side, a p-type amorphous silicon layer 16a in which holes serve as majority carriers and an i-type amorphous layer serving as an intrinsic semiconductor are provided. A pin structure in which a base silicon layer 16b and an n-type amorphous silicon layer 16c in which a large number of electrons are carried is preferably stacked. In order to manufacture the switching element 10, first, a metal film such as chromium Cr (38 a) is formed on the substrate 12 by a vacuum evaporation method using an electron beam or resistance heating, or a sputtering method using DC or RF. Is deposited. Next, a transparent conductive film (38b) such as ITO is deposited thereon by a vacuum evaporation method or a sputtering method. Thereafter, in the same manner as in the above-described embodiment, a p-type amorphous silicon film, an i-type amorphous silicon film, and an n-type amorphous silicon film are successively deposited, and a conductive film is deposited thereon. Next, the upper conductive film, the amorphous silicon film composed of three layers, and the lower transparent conductive film are patterned into a predetermined shape in order, and the upper electrode 18, the semiconductor layer 16, and the lower electrode 38 are patterned. And a transparent conductive layer 38b as a part. Next, after once removing the resist used for patterning, the metal film is again patterned into another predetermined shape by photolithography or the like, thereby forming a metal layer 38a that is a part of the lower electrode 38. As a result, a switching element 36 composed of the lower electrode 38, the semiconductor layer 16 and the upper electrode 18 is manufactured.
ここでは、 金属膜 ( 3 8 a ) と透明導電膜 ( 3 8 b ) をブランケッ ト 状態で堆積した後、 アモルファスシリコン膜を堆積しているが、 この了 モルファスシリコン膜を堆積する前に、 透明導電膜だけを先にパターン 化して透明導電層 3 8 bを形成しておいてもよい。 この場合は、 上部電 極 1 8 と半導体層 1 6 とを形成した後、 ブランケッ ト状態の金属膜をパ ターン化して金属層 3 8 aを形成すれば、 前述したスィツチング素子 3 6と同じ構成となる。 また、 金属層と透明導電層との堆積は真空を破ら ずに連続的に行なってもよいし、 一度、 真空を破って不連続的に行なつ てもよい。 さらにここでは、 主としてフォ トリツグラフィ法によってパ ターン化する方法を例示したが、 マスク法などによって最初から不必要 な部分には膜が堆積ざれないようにして形成してもよく、 その製造方法 は何ら限定されるものではない。 このスィッチング素子 3 6では、 下部電極 3 8が金属層 3 8 aと透明 導電層 3 8 bとから構成され、 半導体層 1 6と透明導電層 3 8 bとの接 合部に界面が形成されている。 したがって、 このスイッチング素子 3 6 は前述のスィツチング素子と同様に作動させられることになる。 その結 果、 逆方向電流は 1 0 〜 1 0— 6秒のオーダーで収束させられ、 かつ、 そのピーク値も小さくなり、 スイッチング速度が向上させられる。 よつ て、 このスィツチング素子 3 6を原稿読み取り装置に使用すれば、 より 正確な信号出力を得ることができ、 さらに信号読み出し速度を速めるこ とも可能である。 Here, the amorphous silicon film is deposited after the metal film (38a) and the transparent conductive film (38b) are deposited in a blanket state, but before the amorphous silicon film is deposited, the transparent silicon film is deposited. The transparent conductive layer 38b may be formed by patterning only the conductive film first. In this case, after forming the upper electrode 18 and the semiconductor layer 16 and then patterning the metal film in a blanket state to form the metal layer 38a, the same configuration as the switching element 36 described above can be obtained. Becomes Further, the deposition of the metal layer and the transparent conductive layer may be performed continuously without breaking the vacuum, or may be performed once by breaking the vacuum. Furthermore, here, the method of patterning mainly by photolithography has been exemplified, but a film may be formed by using a mask method or the like so that a film is not deposited on unnecessary portions from the beginning. It is not limited at all. In this switching element 36, the lower electrode 38 is composed of a metal layer 38a and a transparent conductive layer 38b, and an interface is formed at the junction between the semiconductor layer 16 and the transparent conductive layer 38b. ing. Therefore, this switching element 36 is operated in the same manner as the above-mentioned switching element. As a result, the reverse current is caused to converge on the order of 1 0-1 0 6 seconds, and the peak value becomes small, the switching speed is improved. Therefore, if this switching element 36 is used in a document reading device, a more accurate signal output can be obtained, and the signal reading speed can be further increased.
次に、 第 6図に示すように、 本発明に係るスイッチング素子 4 0はガ ラスなどの基板 1 2上に、 金属層 3 8 aと透明導電層 3 8 bとから構成 される下部電極 3 8と、 p型アモルファスシリコン層 2 6 aと i型ァモ ルファスシリコン層 2 6 bとが積層されて成る半導体層 2 6 と、 金属な どから成る不透明な上部電極 2 2とが形成されて構成されていてもよい c すなわち本例から明らかなように、 半導体層は p i構造にされていても よい。 要するに本発明は、 スイッチング素子を構成する半導体層に透明 導電層との界面を形成することによって、 スィツチング素子に生じる逆 方向電流を阻止するようにすればよいのである。  Next, as shown in FIG. 6, a switching element 40 according to the present invention comprises a lower electrode 3 composed of a metal layer 38 a and a transparent conductive layer 38 b on a substrate 12 such as a glass. 8, a semiconductor layer 26 formed by laminating a p-type amorphous silicon layer 26a and an i-type amorphous silicon layer 26b, and an opaque upper electrode 22 formed of metal or the like. The semiconductor layer may have a pi structure, that is, as is clear from this example. In short, according to the present invention, a reverse current generated in the switching element may be prevented by forming an interface with the transparent conductive layer in the semiconductor layer constituting the switching element.
また第 7図に示すように、 ガラスなどの基板 1 2上に、 金属層 3 8 a と透明導電層 3 8 bとから構成される下部電極 3. 8と、 p型ァモルファ スシリコン層 4 2 aと i型アモルファスシリコン層 4 2 bとが積層され て成る半導体層 4 2と、 絶縁層 4 4 と、 金属などから成る不透明な上部 電極 2 2とが形成されて構成されたスィツチング素子 4 6でもよい。 こ のスィツチング素子 4 6は M I S型になっていて、 金属から成る上部電 極 2 2は半導体層 4 2上に絶縁層 4 4を介して堆積されている。 本例か ら明らかなように、 上部電極は半導体層上に直接でなく間接に堆積され ていてもよい。 更に、 上述の実施例では、 下部電極 3 8を構成する金属層 3 8 aと透 明導電層 3 8 bとを異なる形状にしているが、 同一形状にしてもよい。 その他、 本発明をスイッチング素子に適用するにあたり、 一々説明する までもなく、 適宜種々の構成を採用することができるのは言うまでもな い。 As shown in FIG. 7, a lower electrode 3.8 composed of a metal layer 38a and a transparent conductive layer 38b and a p-type amorphous silicon layer 42 are formed on a substrate 12 made of glass or the like. a switching element 46 composed of a semiconductor layer 42 formed by laminating a and an i-type amorphous silicon layer 42 b, an insulating layer 44, and an opaque upper electrode 22 made of metal or the like. May be. The switching element 46 is of the MIS type, and the upper electrode 22 made of metal is deposited on the semiconductor layer 42 via the insulating layer 44. As is clear from this example, the upper electrode may be deposited on the semiconductor layer indirectly instead of directly. Further, in the above embodiment, the metal layer 38a and the transparent conductive layer 38b constituting the lower electrode 38 have different shapes, but may have the same shape. In addition, when applying the present invention to a switching element, it goes without saying that various configurations can be appropriately adopted without any explanation.
以上、 本発明に係る半導体装置をスィツチング素子に適用した実施例 を詳述したが、 次に、 本発明に係る半導体装置を光センサ素子に適用し た実施例を図面に基づき詳しく説明する。  The embodiment in which the semiconductor device according to the present invention is applied to a switching element has been described in detail above. Next, an embodiment in which the semiconductor device according to the present invention is applied to an optical sensor element will be described in detail with reference to the drawings.
第 8図に示すように、 本発明に係る光センサ素子 4 8は、 ガラスなど から成る基板 1 2上に、 光電変換素子であるフォ トダイォード 5 0 と、 スィツチング素子であるプロッキングダイォード 5 2とが形成されて構 成されている。 これらフォ トダイオード 5 0及びプロッキングダイォ一 ド 5 2は、 ともに I T O ( Indi um Tin Oxi de) などから成る透明な下部 電極 5 0 a , 5 2 aと、 アモルファスシリコンなどから成る p i n構造 の半導体層 5 O b , 5 2 bと、 I T Oなどから成る透明な上部電極 5 0 c, 5 2 cとが順に堆積されて構成されている。 ここで、 ブロッキング ダイォ一ド 5 2を構成する下部電極 5 2 aが透明であることが本実施例 の最大の特徴である。  As shown in FIG. 8, an optical sensor element 48 according to the present invention comprises a substrate 12 made of glass or the like, a photo diode 50 as a photoelectric conversion element, and a blocking diode 52 as a switching element. Are formed. Both the photodiode 50 and the blocking diode 52 have a transparent lower electrode 50a, 52a made of ITO (Indium Tin Oxide) or the like and a pin structure made of amorphous silicon or the like. Semiconductor layers 5Ob and 52b and transparent upper electrodes 50c and 52c made of ITO or the like are sequentially deposited. Here, the greatest feature of the present embodiment is that the lower electrode 52a constituting the blocking diode 52 is transparent.
これらフォ トダイオード 5 0及びブロッキングダイォード 5 2は Si O x や SiNx などから成る透明な層間絶縁膜 5 4により覆われていて、 こ の層間絶縁膜 5 4に形成されたコンタク トホール 5 6を介して接続配線 5 8によって互いに逆極性で直列接続されている。 すなわち、 フォ トダ ィォ一ド 5 0とブロッキングダイォード 5 とはカフ一ド電極同士で接 続されているのである。 These photodiodes 5 0 and blocking die O over de 5 2 is covered with Si O x or SiN transparent interlayer insulating film made of such x 5 4, contactor formed in the interlayer insulating film 4 of this Tohoru 5 6 Are connected in series by the connection wiring 58 with opposite polarities. That is, the photodiode 50 and the blocking diode 5 are connected by the cuff electrodes.
この光センサ素子 4 8を製造するには、 まず基板 1 2上に、 電子ビー ムゃ抵抗加熱による真空蒸着法、 あるいは D Cや R Fによるスパッタリ ング法などによって I T Oなどの透明導電膜 ( 5 0 a, 5 2 a ) を堆積 する。 たとえば DCスパッタリング法によって I TO膜を堆積する場合 は、 まず基板 1 2をチヤンバ一内にセッ トし、 そのチャンバ一内を 1 0 一5 Torr以下まで排気する。 その後、 基板 1 2を 1 0 0〜25 0 °Cに保持 しながら、 圧力 0. 1〜1. 0 P a、 DC電力 0. 1〜 1. 0 c m 2 の下でアルゴンガスと酸素ガスとを一定の割合で導入する。 これによ り、 基板 1 2上に I TO膜を堆積することができる。 なお、 この透明導 電膜の膜厚は、 この上に堆積されるアモルファスシリコン膜の性能やこ の透明導電膜の特性など考慮して適宜決定されるが、 I TO膜であれば 1 20 0 A程度が好ましい。 In order to manufacture the optical sensor element 48, first, a transparent conductive film (50a) such as ITO is formed on the substrate 12 by an electron beam, a vacuum deposition method using resistance heating, or a sputtering method using DC or RF. , 52 a) I do. For example when depositing I TO film by DC sputtering method, first set the substrate 1 2 Chiyanba in one, evacuating the chamber in one to 1 0 one 5 Torr or less. Then, while holding the substrate 1 2 1 0 0 to 25 0 ° C, and pressure 0. 1~1. 0 P a, argon gas and oxygen gas under DC power 0.. 1 to 1. 0 cm 2 Is introduced at a fixed rate. Thereby, an ITO film can be deposited on the substrate 12. The thickness of the transparent conductive film is appropriately determined in consideration of the performance of the amorphous silicon film deposited thereon and the characteristics of the transparent conductive film. The degree is preferred.
さらにこの上に、 プラズマ CVD法などによって、 正孔が多数キヤリ ァとなる p型アモルファスシリコン膜と、 真性半導体となる i型ァモル ファスシリコン膜と、 電子が多数キヤリアとなる n型アモルファスシリ コン膜とを連続的に堆積する。  On top of this, a p-type amorphous silicon film with many holes as carriers, an i-type amorphous silicon film as an intrinsic semiconductor, and an n-type amorphous silicon film with many electrons as carriers by plasma CVD. Are continuously deposited.
そして再度この上に、 前述した最下層の透明導電膜と同様に、 真空蒸 着法やスパッタリング法などによって I TOなどの透明導電膜を堆積す る。 なお、 この透明導電膜の膜厚は、 アモルファスシリコン膜の性能や この透明導電膜の特性などを考慮して適宜決定されるもので、 数百〜数 千 A程度が好ましいが、 I TO膜であれば 6 0 0 A程度が好ましい。 次いで、 これらの膜を順にパターン化することによって、 下部電極 5 0 a, 5 2 aと半導体層 5 0 b, 5 2 bと上部電極 5 0 c, 5 2 cとを 形成する。 たとえばフォ トリソグラフィ法によってパターン化する場合 は、 まず最上層の透明導電 膜上にレジスト液を塗布し、 プリべークを した後、 所定のパターンが刻まれたマスクを用いて露光を行ない、 さら に現像及びポストべ一クを行なう。 そして、 透明導電膜に I TOを用い た場合であれば、 塩酸と硝酸の混合液によってその透明導電膜をエッチ ングし、 上部電極 5 0 c, 5.2 cを形成する。 次に、 平行平板型のエツ チング装置を用いてアモルファスシリコン膜をエッチングする。 すなわ ち、 チャンバ一内を 1 0— 3Torr以下まで排気した後、 CF4 ガスと 02 ガ スとを導入し、 さらに圧力を 5. 0 P aに保持しながら 1 3. 5 6 MH zの高周波電源を用いて電極に 0. 1〜0. 7W./cm2 の電力を供給 する。 これにより、 アモルファスシリコン膜をエッチングし、 半導体層 5 0 b, 5 2 bを形成することができる。 さらに、 パターニングに用い たレジストを一旦除去した後、 前述した最上層の透明導電膜と同様に、 最下層の透明導電膜もフォ トリソグラフィ法などによってパターン化し、 下部電極 5 0 a, 5 2 aを形成すれば、 フォ トダイオード 5 0 とブロッ キングダイォード 5 2とを形成することができる。 Then, a transparent conductive film such as ITO is deposited thereon again by a vacuum deposition method or a sputtering method in the same manner as the lowermost transparent conductive film described above. The thickness of the transparent conductive film is appropriately determined in consideration of the performance of the amorphous silicon film, the characteristics of the transparent conductive film, and the like, and is preferably about several hundred to several thousand A. If so, about 600 A is preferable. Next, these films are sequentially patterned to form lower electrodes 50a and 52a, semiconductor layers 50b and 52b, and upper electrodes 50c and 52c. For example, when patterning is performed by photolithography, a resist solution is first applied to the uppermost transparent conductive film, prebaked, and then exposed using a mask engraved with a predetermined pattern. Further, development and postbaking are performed. If ITO is used for the transparent conductive film, the transparent conductive film is etched with a mixed solution of hydrochloric acid and nitric acid to form upper electrodes 50c and 5.2c. Next, the amorphous silicon film is etched using a parallel plate type etching apparatus. Sand Chi, after evacuating the chamber one to 1 0- 3 Torr or less, introducing a CF 4 gas and 0 2 gas, 1 3. 5 6 MH z while maintaining further pressure to 5. 0 P a An electric power of 0.1 to 0.7 W./cm 2 is supplied to the electrodes using a high frequency power supply. This allows the amorphous silicon film to be etched to form the semiconductor layers 50b and 52b. Further, after the resist used for patterning is once removed, the lowermost transparent conductive film is patterned by photolithography or the like in the same manner as the uppermost transparent conductive film described above, and the lower electrodes 50a and 52a are formed. , A photodiode 50 and a blocking diode 52 can be formed.
次いで、 これらフォ トダイォード 5 0 とプロッキングダイォード 5 2 の上に、 熱 CVD法, 常圧 CVD法, プラズマ CVD法, スパッタリ ン グ法などによって SiOx や SiNx などを堆積した後、 これをフオ トリソ グラフィ法などによって所定形状にパターン化し、 層間絶縁膜 5 4を形 成する。 たとえばプラズマ CVD法でシリコン酸化膜を堆積する場合は、 チャンバ一内を 1 0 _2Torr以下まで排気し、 基板 1 2を所定温度に加熱 保持した後、 シランガス 2 0〜 6 0 sccmと、 亜酸化窒素ガス 1 5 0〜 3 O Osccmを導入し、 0. 3〜1. 2 Torrの圧力に保持する。 ここで、 必 要に応じて水素ガスや窒素ガスを導入してもよい。 その後、 圧力が安定 するのを待って、 1 3. 5 6MH zの高周波電源を用いて基板 1 2と対 面する電極に 0. 0 1〜0. 5 W/cm2 の電力を供給する。 ここで、 供給する電力は装置の構造や堆積する膜質に依存し、 また、 シリコン酸 化膜の場合には平行平板型のエッチング装置を用いることができる。 こ れによりシリコン酸化膜をパターン化し、 層間絶縁膜 5 4を形成するこ とができる。 なお、 フォ トダイオード 5 0とブロッキングダイォード 5 2上のコンタク トホール 5 6はこのときに形成すればよい。 Next, SiO x and SiN x are deposited on the photo diode 50 and the blocking diode 52 by a thermal CVD method, a normal pressure CVD method, a plasma CVD method, a sputtering method, or the like. An interlayer insulating film 54 is formed by patterning into a predetermined shape by photolithography or the like. For example, when depositing a silicon oxide film by a plasma CVD method, the inside of the chamber is evacuated to 10 to 2 Torr or less, the substrate 12 is heated and maintained at a predetermined temperature, and then silane gas of 20 to 60 sccm is added. Nitrogen oxide gas is introduced at 150 to 3 Osccm and maintained at a pressure of 0.3 to 1.2 Torr. Here, hydrogen gas or nitrogen gas may be introduced as needed. Then, after the pressure is stabilized, a power of 0.01 to 0.5 W / cm 2 is supplied to the electrode facing the substrate 12 using a high-frequency power supply of 13.6 MHz. Here, the power to be supplied depends on the structure of the device and the quality of the film to be deposited. In the case of a silicon oxide film, a parallel plate type etching device can be used. As a result, the silicon oxide film can be patterned, and the interlayer insulating film 54 can be formed. The contact hole 56 on the photodiode 50 and the blocking diode 52 may be formed at this time.
さらにこれらの上に、 真空蒸着法やスパッタリング法などによって Cr, Ni, Pd, Ti, Mo, Ta, Alなどの金属を単層又は多層に、 さらに好ましく は 5 0 0 A厚の Crと 1 . 5 a m厚の Alとを 2層に堆積する。 次いでこれ をフォ トリソグラフィ法などによって所定形状にパターン化し、 接続配 線 5 8を形成する。 これにより、 上部電極 5 0 c 5 2 c同士が接続配 線 5 8により電気的に接続され、 フォ トダイォード 5 0 とブロッキング ダイオード 5 2とから構成される光センサ素子 4 8が製造されることに なる。 ここで、 接続配線 5 8が A1と Crとの 2層膜の場合、 A1のエツチン グは燐酸、 硝酸及び酢酸の混合液で行なえばよく、 一方 Crのエッチング は硝酸第 2セリウムアンモニゥムで行なえばよい。 また、 これらの材料 は電気的接続が可能であれば金厲でなくてもよく、 特に限定されるもの ではない。 Further, a metal such as Cr, Ni, Pd, Ti, Mo, Ta, Al or the like is formed on these in a single layer or a multilayer by a vacuum deposition method or a sputtering method. Deposits 500 A thick Cr and 1.5 am Al in two layers. Next, this is patterned into a predetermined shape by a photolithography method or the like, and a connection wiring 58 is formed. As a result, the upper electrodes 50 c 52 c are electrically connected to each other through the connection wiring 58, and the optical sensor element 48 composed of the photodiode 50 and the blocking diode 52 is manufactured. Become. Here, when the connection wiring 58 is a two-layer film of A1 and Cr, the etching of A1 may be performed with a mixed solution of phosphoric acid, nitric acid, and acetic acid, while the etching of Cr is performed using ceric ammonium nitrate. Just do it. These materials are not limited to metal as long as they can be electrically connected, and are not particularly limited.
なおここでは、 主としてフォ トリソグラフィ法によってパターン化す る方法を例示したが、 マスク法などによつて最初から不必要な部分には 膜が堆積されないようにして形成してもよいなど、 その製造方法は何ら 限定されるものではない。  Here, a method of patterning mainly by photolithography has been described as an example, but a manufacturing method such as forming a film such that a film is not deposited on unnecessary portions from the beginning by a mask method or the like may be used. Is not limited at all.
次に、 この光センサ素子 4 8の動作について説明する。  Next, the operation of the optical sensor element 48 will be described.
第 9図(a) に示すように、 ブロッキングダイォード 5 2のァノード電 極 (下部電極 5 2 a ) がフォ トダイオード 5 0のァノード電極 (下部電 極 5 0 a ) に対して正電位 Vpにされると、 ブロッキングダイォ一ド 5 2 は順バイアスとなり、 フォ トダイオード 5 0は逆バイアスとなる。 これ により、 フォ トダイオード 5 0の並列容量 6 0は充電され、 フォ トダイ オード 5 0とプロッキングダイォード 5 2との接続部の電位が高くなる c 次いで第 9図(b) に示すように、 ブロッキングダイォード 5 2のァノー ド電極が接地されると、 ブロッキングダイォ一ド 5 2は逆バイアスにな る。 この状態でフォ トダイオード 5 0に光が入射すると、 フォ トダイォ 一ド 5 0の並列容量 6 0はそこに生じた光電流 I pによって放電される。 その後、 再びブロッキングダイォ一ド 5 2のァノ一ド電極が正電位 Vpに されると、 ブロッキングダイオード 5 2は順バイアスとなり、 フォ トダ ィオード 5 0の並列容量 6 0は再び充電される。 このとき流れる充電電 流が光電流 I Pに相当し、 出力電流として流れる。 したがって、 この出力 電流を検出すればフォ トダイオード 5 0に入射した光量を検出すること になる。 As shown in FIG. 9 (a), the anode electrode (lower electrode 52a) of the blocking diode 52 has a positive potential Vp with respect to the anode electrode (lower electrode 50a) of the photodiode 50. In this case, the blocking diode 52 becomes forward-biased, and the photodiode 50 becomes reverse-biased. As a result, the parallel capacitance 60 of the photodiode 50 is charged, and the potential at the connection between the photodiode 50 and the blocking diode 52 increases. Then, as shown in FIG. When the anode electrode of the blocking diode 52 is grounded, the blocking diode 52 becomes reverse-biased. When light enters the photodiode 50 in this state, the parallel capacitance 60 of the photodiode 50 is discharged by the photocurrent Ip generated there. Thereafter, when the anode electrode of the blocking diode 52 is again set to the positive potential Vp, the blocking diode 52 becomes forward-biased and The parallel capacitance 60 of the diode 50 is charged again. The charging current flowing at this time corresponds to the photocurrent IP and flows as an output current. Therefore, if this output current is detected, the amount of light incident on the photodiode 50 will be detected.
本例では、 ブロッキングダイォード 5 2の下部電極 5 2 a及び上部電 極 5 2 cが透明導電層から構成されているため、 半導体層 5 2 bと透明 導電層である下部電極 5 2 a及び上部電極 5 2 cとの接合部に界面が形 成されている。 したがって、 スイッチング素子であるブロッキングダイ オード 5 2は前述と同様に作動させられると考えられる。 これにより、 逆方向電流は 1 0 - 5〜1 0 秒のオーダ一で収束させられ、 かつ、 その ピーク値も小さくなる。 よって、 この光センサ素子 4 8からは正確な信 号出力が得られるとともに、 そのスィツチング速度も向上させられる。 さらに、 この光センサ素子 4 8を原稿読み取り装置に使用すれば、 より 正確な信号出力を得ることができ、 さらに信号読み出し速度を速めるこ とも可能である。 In this example, since the lower electrode 52 a and the upper electrode 52 c of the blocking diode 52 are formed of a transparent conductive layer, the semiconductor layer 52 b and the lower electrode 52 a that is a transparent conductive layer are formed. An interface is formed at the junction with the upper electrode 52c. Therefore, it is considered that the blocking diode 52 as a switching element is operated in the same manner as described above. Thus, reverse current 1 0 - 5 are made to converge at ~ 1 0 seconds order one, and also decreases the peak value. Therefore, an accurate signal output can be obtained from the optical sensor element 48, and the switching speed can be improved. Furthermore, if this optical sensor element 48 is used in a document reading device, a more accurate signal output can be obtained, and the signal reading speed can be further increased.
以上、 本発明に係る光センサ素子の一実施例を詳述したが、 本発明が 適用される光センサ素子は上述した実施例に限定されることなく、 その 他の態様でも実施し得るものである。  As described above, one embodiment of the optical sensor element according to the present invention has been described in detail. However, the optical sensor element to which the present invention is applied is not limited to the above-described embodiment, but may be implemented in other aspects. is there.
たとえば上述した実施例では、 フォ トダイオード 5 0を構成する上部 電極 5 0 cと、 ブロッキングダイォ一ド 5 2を構成する上部電極 5 2 c とが接続配線 5 8によって接続されているが、 第 1 0図に示すように、 フォ トダイオード 5 0を構成する下部電極 6 2と、 プロッキングダイォ ―ド 5 2を構成する下部電極 6 2とが共通になっていて、 この下部電極 6 2によってフォ トダイオード 5 0とブロッキングダイオード 5 2とが 直列接続されて構成された光センサ素子 6 4でもよい。 この場合は、 下 部電極 6 2を I T Oなどの透明導電層で形成しておけばよい。 また、 フ ォ トダイオード 5 0の上部電極 5 0 c及びブロッキングダィォード 5 2 の上部電極 5 2 cは、 それぞれ引出配線 6 6 , 6 8によって外部に取り 出しておけばよい。 なお本例では、 フォ トダイオー ド 5 0 とプロッキン グダィォ一ド 5 2とはァノード電極同士で接続され、 互いに逆極性で直 列接続されている。 For example, in the above-described embodiment, the upper electrode 50 c constituting the photodiode 50 and the upper electrode 52 c constituting the blocking diode 52 are connected by the connection wiring 58. As shown in FIG. 10, the lower electrode 62 constituting the photodiode 50 and the lower electrode 62 constituting the blocking diode 52 are common. The optical sensor element 64 may be configured such that the photodiode 50 and the blocking diode 52 are connected in series by 2. In this case, the lower electrode 62 may be formed of a transparent conductive layer such as ITO. The upper electrode 50 c of the photodiode 50 and the blocking diode 52 The upper electrode 52 c may be extracted to the outside by the lead wirings 66 and 68, respectively. In this example, the photodiode 50 and the blocking diode 52 are connected by anode electrodes and are connected in series with opposite polarities.
ここで、 上述した実施例では、 製造工程の簡素化などの理由から、 フ ォ トダイォード 5 0及びブロッキングダイオード 5 2を構成する下部電 極 5 0 a , 5 2 a、 半導体層 5 O b , 5 2 b及び上部電極 5 0 c , 5 2 cは、 それぞれ同時に堆積されたもので、 それぞれ同じ材料から構成さ れているが、 フォ トダイォード 5 0 'を構成する上部電極 5 0 Cは透明で なければならないが、 ブロッキングダイォード 5 2を構成する上部電極 5 2 cは透明でなくてもよい。 また、 フォ トダイォード 5 0を構成する 下部電極 5 0 aは透明でなくてもよく、 少なく ともブロッキングダイォ 一ド (スィツチング素子) 5 2を構成する下部電極 5 2 aが透明であれ ばよい。 、  Here, in the above-described embodiment, the lower electrodes 50a and 52a and the semiconductor layers 5Ob and 5b constituting the photodiode 50 and the blocking diode 52 are formed for reasons such as simplification of the manufacturing process. 2b and the upper electrodes 50c and 52c are deposited simultaneously and are made of the same material, respectively, but the upper electrode 50C constituting the photodiode 50 'must be transparent. However, the upper electrode 52 c constituting the blocking diode 52 need not be transparent. In addition, the lower electrode 50a constituting the photodiode 50 may not be transparent, and at least the lower electrode 52a constituting the blocking diode (switching element) 52 may be transparent. ,
以上、 本発明に係る半導体装置である光センサ素子において、 少なく ともスィツチング素子の下部電極を透明に構成した実施例を説明したが、 光センサ素子における少なく ともスィツチング素子の下部電極若しくは 上部電極又は双方の電極を 1層以上の金属層と、 その金属層の上に堆積 される透明導電層とから構成してもよい。 次に、 この実施例を図面に基 づき詳しく説明する。  As described above, the embodiment in which at least the lower electrode of the switching element is configured to be transparent in the optical sensor element as the semiconductor device according to the present invention has been described. The electrode may be composed of one or more metal layers and a transparent conductive layer deposited on the metal layer. Next, this embodiment will be described in detail with reference to the drawings.
第 1 1図に示すように、 本実施例に係る光センサ素子 7 0は概略前述 の実施例と同様に、 ガラスなどから成る基板 1 2上に、 光電変換素子で あるフォ トダイオー ド 7 2と、 スィッチング素子であるブロッキングダ ィオード 7 4 とが形成されて構成されている。  As shown in FIG. 11, an optical sensor element 70 according to the present embodiment has a photo diode 72 as a photoelectric conversion element on a substrate 12 made of glass or the like, similarly to the above-described embodiment. And a blocking diode 74 serving as a switching element.
これらフォ トダイオード 7 2及びブロッキングダイオード 7 4は、 と もに二層構造の下部電極 7 2 a , . 7 4 aと、 アモルファスシリ コンなど から成る P i n構造の半導体層 7 2 b , 7 4 bと、 I T 0 ( I nd i um T i n Oxide) などから成る透明な上部電極 7 2. C , 74 cとが順に堆積され て構成されている。 ブロッキングダイォード 74の下部電極 74 aは、 クロム Crなどから成る金属層 74 a , と、 この金属層 74 a , 上に堆積 される I TOなどから成る透明導電層 74 a 2 とから構成されている。 この点が本実施例の最大の特徴であり、 その他は前述の実施例と同様、 フォ トダイオード 72及びプロッキングダイォード 74は SiOx や SiN X などから成る透明な層間絶縁膜 54により覆われていて、 この層間絶 縁膜 54に形成されたコンタク トホール 5 6を介して接続配線 5 8によ り互いに逆極性で直列接続されている。 Both the photodiode 72 and the blocking diode 74 are composed of a lower electrode 72 a, .74 a having a two-layer structure and a semiconductor layer 72 b, 74 having a Pin structure made of amorphous silicon or the like. b and IT 0 (Ind i um T in Oxide) and a transparent upper electrode 7 2. C, 74 c are sequentially deposited. Lower electrode 74 a blocking die O over de 74, the metal layer 74 a made of chrome Cr, and the metal layer 74 a, is composed of such a composed a transparent conductive layer 74 a 2 Metropolitan I TO deposited on I have. Is the largest feature of this point the present embodiment, and the other similar to the previous embodiments, is covered by the photodiode 72 and flop locking die O over de 74 SiO x or SiN X, such as a transparent interlayer insulating film 54 made of The connection is made in series by the connection wiring 58 through the contact hole 56 formed in the interlayer insulating film 54 with the opposite polarities.
この光センサ素子 70を製造するには、 まず基板 1 2上に、 電子ビー 厶ゃ抵抗加熱による真空蒸着法、 あるいは DCや RFによるスパッタリ ング法などによってクロム Crなどの金属膜を堆積する。 次いで、 この上 に、 真空蒸着法ゃスパッタリング法などによって I TOなどの透明導電 膜を堆積する。 たとえば DCスパッ夕リ ング法によって金属膜と透明導 電膜とを堆積する場合は、 まず基板 1 2をチャンバ一内にセッ トし、 そ のチャンバ一内を 1 0 _5Τοι 以下まで排気した後、 その基板 1 2を 1 0 0- 25 0 °Cに保持しながら、 圧力 0. 1〜1. 0 P a、 DC電力 0. 1〜 OWZcm2 の下で、 アルゴンガスと酸素ガスとを一定の割合 で導入し、 金属膜と透明導電膜とを順番に堆積することによって行われ る 0 In order to manufacture the optical sensor element 70, first, a metal film such as chromium Cr is deposited on the substrate 12 by a vacuum evaporation method using electron beam resistance heating or a sputtering method using DC or RF. Next, a transparent conductive film such as ITO is deposited thereon by a vacuum evaporation method or a sputtering method. For example, when depositing a metal film and a transparent conductive film by the DC sputtering method, first, the substrate 12 is set in the first chamber, and the inside of the first chamber is evacuated to less than 10 5 Τοι. after, while maintaining the substrate 1 2 1 0 0- 25 0 ° C, pressure 0. 1~1. 0 P a, under DC power 0. 1~ OWZcm 2, argon gas and oxygen gas It is performed by introducing at a fixed rate and sequentially depositing a metal film and a transparent conductive film.
その後は前述の実施例と同様にして、 アモルファスシリコン膜を P型、 i型、 n型の順に堆積した後、 I TOなどの透明導電膜を堆積する。 な お、 金属膜及び透明導電膜の膜厚はそれぞれ数百〜数千 A程度が好まし いが、 これらの膜の特性や、 アモルファスシリコン膜の性能などを考慮 して適宜決定されるものである。 たとえば金属膜としてクロム Crを用い、 透明導電膜として I TOを用いた場合であれば、 金属膜の膜厚は 1 5 0 0〜2 0 0 0 A程度が好ましく、 透明導電膜の膜厚は下層 ( 72 a 2 , 7 4 a 2 ) が 1 2 0 0 A程度、 上層 ( 7 2 c , 7 4 c ) が 6 0 0 A程度 が好ましい。 Thereafter, in the same manner as in the above-described embodiment, an amorphous silicon film is deposited in the order of P-type, i-type, and n-type, and then a transparent conductive film such as ITO is deposited. The thickness of each of the metal film and the transparent conductive film is preferably about several hundred to several thousand A, but is appropriately determined in consideration of the characteristics of these films and the performance of the amorphous silicon film. is there. For example, when chromium Cr is used as the metal film and ITO is used as the transparent conductive film, the thickness of the metal film is preferably about 150 to 200 A, and the thickness of the transparent conductive film is lower (72 a 2, It is preferable that 74 a 2 ) be about 1200 A and the upper layer (72 c, 74 c) be about 600 A.
次いで、 前述の実施例と同様に、 上層の透明導電膜と、 3層から成る アモルファスシリコン膜と、 下層の透明導電膜とを順に所定形状にパ夕 ーン化し、 上部電極 7 2 c , 7 4 cと、 半導体層 7 2 b , 7 4 bと、 下 部電極 7 2 a , 7 4 aの一部である透明導電層 7 2 a 2 , 7 4 a 2 とを 形成する。 次いで、 パターニングに用いたレジストを一旦除去した後、 再びフォ トリソグラフィ法などによって金属膜を別の所定形状にパ夕一 ン化し、 下部電極 7 2 a, 7 4 aの一部である金属層 7 2 a , , 7 4 a , を形成する。 これにより、 フォ トダイオード 7 2とブロッキングダイ オード 7 4 とが形成される。 ここで、 金厲膜としてクロム Crを用いた場 合であれば、 硝酸第 2セリゥ厶アンモニゥムなどによってエッチングを すればよい。 Next, similarly to the above-described embodiment, the upper transparent conductive film, the three-layer amorphous silicon film, and the lower transparent conductive film are patterned into a predetermined shape in order, and the upper electrodes 72 c and 7 are formed. 4 and c, to form the semiconductor layer 7 2 b, 7 4 b, and a lower portion electrode 7 2 a, 7 4 transparent conductive layer is part of a 7 2 a 2, 7 4 a 2. Next, after the resist used for patterning is once removed, the metal film is again patterned into another predetermined shape by photolithography or the like, and the metal layer which is a part of the lower electrodes 72 a and 74 a is formed. 7 2 a,, 7 4 a, are formed. As a result, a photodiode 72 and a blocking diode 74 are formed. Here, in the case where chromium Cr is used as the gold film, etching may be performed using, for example, a second cellium nitrate ammonium nitrate.
次に、 前述の実施例と同様に、 これらフォ トダイォード 7 2とブロッ キングダイォ一ド 7 4の上に、 層間絶縁膜 5 4 とコンタク トホール 5 6 を形成し、 さらにこれらの上に、 金属を単層又は多層に堆積した後、 パ ターン化し、 接続配線 5 8を形成する。 これにより、 上部電極 7 2 c , 7 4 c同士が接続配線 5 8により電気的に接続され、 フォ トダイォード 7 2とブロッキングダイオード 7 4とから構成される光センサ素子 7 0 が製造されることになる。  Next, an interlayer insulating film 54 and a contact hole 56 are formed on the photo diode 72 and the blocking diode 74 in the same manner as in the above-described embodiment, and a metal is simply formed thereon. After being deposited in layers or multilayers, it is patterned and the connection wiring 58 is formed. As a result, the upper electrodes 72 c and 74 c are electrically connected to each other by the connection wiring 58, and the optical sensor element 70 composed of the photodiode 72 and the blocking diode 74 is manufactured. Become.
ここでは、 金属膜と透明導電膜とをブランケッ ト状態で堆積した後、 アモルファスシリコン膜を堆積しているが、 このアモルファスシリコン 膜を堆積する前に、 透明導電膜だけを先にパターン化して透明導電層 7 2 a 2 , 7 4 a 2 を形成しておいてもよい。 この場合は、 上部電極 7 2 c , 7 4 cと半導体層 7 2 b , 7 4 bとを形成した後、 ブランケッ ト状 態の金属膜をパターン化して金属層 7 2 a , , 7 4 a , を形成すれば、 前述した光センサ素子 7 0と同じ構成となる。 また、 金属層と透明導電 層との堆積は真空を破らずに連続的に行なってもよいし、 一度、 真空を 破って不連続的に行なってもよい。 さらにここでは、 主としてフォ トリ ソグラフィ法によつてパターン化する方法を例示したが、 マスク法など によって最初から不必要な部分には膜が堆積されないようにして形成し てもよく、 その製造方法は何ら限定されるものではない。 Here, the amorphous silicon film is deposited after the metal film and the transparent conductive film are deposited in a blanket state, but before depositing the amorphous silicon film, only the transparent conductive film is first patterned to form a transparent film. conductive layer 7 2 a 2, 7 4 a 2 may be formed of. In this case, after forming the upper electrodes 72c, 74c and the semiconductor layers 72b, 74b, the blanket state metal film is patterned to form the metal layers 72a, 74a. , Are the same as those of the optical sensor element 70 described above. In addition, metal layer and transparent conductive The deposition with the layer may be performed continuously without breaking the vacuum or may be performed discontinuously once the vacuum is broken. Furthermore, here, the method of patterning mainly by photolithography has been exemplified, but a film may be formed by preventing the film from being deposited on unnecessary portions from the beginning by a mask method or the like. It is not limited at all.
なお、 この光センサ素子 7 0の動作は先に説明した光センサ素子 4 8 の動作と同様であるため、 説明を省略する。  The operation of the optical sensor element 70 is the same as the operation of the optical sensor element 48 described above, and a description thereof will be omitted.
次に、 たとえば上述した実施例では、 フォ トダイオード 7 2を構成す る上部電極 7 2 cと、 ブロッキングダイオード 7 4を構成する上部電極 Next, for example, in the above-described embodiment, the upper electrode 72 c constituting the photodiode 72 and the upper electrode constituting the blocking diode 74
7 4 cとが接続配線 5 8によって接続されているが、 第 1 2図に示すよ うに、 フォ トダイオード 7 2を構成する下部電極 7 6と、 ブロッキング ダイォード 7 4を構成する下部電極 7 6とが共通になっていて、 この下 部電極 7 6によってフォ トダイオード 7 2とプロッキングダイォ一ド 7 4とが接続されて成る光センサ素子 7 8でもよい。 この場合は、 金属層7 4 c are connected by connection wiring 58, as shown in FIG. 12, as shown in FIG. 12, a lower electrode 76 forming a photodiode 72 and a lower electrode 76 forming a blocking diode 74. The lower electrode 76 may be used as an optical sensor element 78 in which the photodiode 72 and the blocking diode 74 are connected. In this case, the metal layer
8 0と透明導電層 8 2 , 8 4 とを順に堆積して下部電極 7 6を構成し、 半導体層 7 4 bと透明導電層 8 4との接合部に界面が形成されるように すればよい。 また、 フォ トダイォード 7 2の上部電極 7 2 cと、 ブロッ キングダイォード 7 4の上部電極 7 4 cとは、 コンタク トホール 5 6を 介してそれぞれ引出配線 8 6 , 8 8によって外部に取り出しておけばよ い。 本例では、 フォ トダイォード 7 2とブロッキングダイォード 7 4と はァノード電極同士で接続され、 互いに逆極性で直列接続されているこ とになる。 80 and the transparent conductive layers 8 2 and 8 4 are sequentially deposited to form the lower electrode 76, so that an interface is formed at the junction between the semiconductor layer 74 b and the transparent conductive layer 84. Good. Also, the upper electrode 72 c of the photo diode 72 and the upper electrode 74 c of the blocking diode 74 can be taken out to the outside by the lead wirings 86, 88 via the contact holes 56, respectively. You should. In this example, the photo diode 72 and the blocking diode 74 are connected between the anode electrodes and are connected in series with opposite polarities.
なお上述した実施例では、 金属層 7 2 a , , 7 4 a , , 8 0 と透明導 電層 7 2 a 2 , 7 4 a 2 , 8 2 , 8 4 とを異なる形状にしているが、 同 —形状にしてもよい。 In yet mentioned above embodiments, the metal layer 7 2 a,, 7 4 a ,, 8 0 and the transparent conductive layer 7 2 a 2, 7 4 a 2, 8 2, but with a 8 4 different shapes, Same — may be shaped.
また、 上述した実施例では、 製造工程の簡素化などの理由から、 フォ トダイオード 7 2及びブロッキングダイオード 7 4を構成するそれぞれ の下部電極 7 2 a , 7 4 a、 半導体層 7 2 b , 7 4 b及び上部電極 7 2 c , 7 4 cは、 それぞれ同時に堆積されたもので、 それぞれ同じ材料か ら構成されている。 しかしながら、 このフォ トダイオード 7 2を構成す る上部電極 7 2 cは透明でなければならないが、 プロッキングダイォ一 ド 7 4を構成する上部電極 7 4 cは透明でなくてもよい。 また、 フォ ト ダイォード 7 2を構成する下部電極 7 2 aは、 金属層と透明導電層とか ら構成されていなくてもよく、 少なく ともブロッキングダイオード (ス ィツチング素子) 7 4を構成する下部電極 7 4 aが、 金属層 7 4 a , と 透明導電層 7 4 a 2 とから構成されていればよい。 要するに本発明は、 スィツチング素子を構成する半導体層に透明導電層との界面を形成する ことによって、 スィッチング素子に生じる逆方向電流を阻止するように すればよいのである。 Further, in the above-described embodiment, the photodiodes 72 and the blocking diodes 74 are formed for reasons such as simplification of the manufacturing process. The lower electrodes 72a and 74a, the semiconductor layers 72b and 74b, and the upper electrodes 72c and 74c are simultaneously deposited, and are made of the same material. However, the upper electrode 72c constituting the photodiode 72 must be transparent, but the upper electrode 74c constituting the blocking diode 74 need not be transparent. Further, the lower electrode 72 a constituting the photo diode 72 does not need to be composed of the metal layer and the transparent conductive layer, and at least the lower electrode 72 a constituting the blocking diode (switching element) 74. 4 a may be composed of a metal layer 7 4 a, the transparent conductive layer 7 4 a 2 Prefecture. In short, according to the present invention, the reverse current generated in the switching element may be prevented by forming an interface with the transparent conductive layer in the semiconductor layer constituting the switching element.
以上、 本発明に係る半導体装置をスィツチング素子及び光センサ素子 に適用した実施例を説明したが、 さらに本発明を原稿読み取り装置に適 用してもよい。 次に、 本発明を原稿読み取り装置に適用した実施例を、 図面に基づき詳しく説明する。  Although the embodiment in which the semiconductor device according to the present invention is applied to the switching element and the optical sensor element has been described above, the present invention may be further applied to a document reading apparatus. Next, an embodiment in which the present invention is applied to a document reading apparatus will be described in detail with reference to the drawings.
第 1 3図及び第 1 4図に示すように、 本発明に係る原稿読み取り装置 9 0は、 ガラスなどから成る基板 1 2上に、 光電変換素子であるフォ ト ダイオード 9 2と、 スィツチング素子であるプロッキングダイオード 9 4と、 フォ トダイオード 9 2からの電気信号を読み出すためのチヤンネ ル配線 C , . C 2. . . . C„ とが形成されて構成されている。 ここでば、 フ ォ トダイオード 9 2とブロッキングダイオード 9 4とにより光センサ素 子が構成されている。 As shown in FIGS. 13 and 14, an original reading device 90 according to the present invention includes a photodiode 92 as a photoelectric conversion element and a switching element on a substrate 12 made of glass or the like. there flops locking diode 9 4, photodiode 9 Chiyan'ne Le wiring C for reading an electrical signal from the 2,. C 2.... C "and is to be constituted by forming. in this case the, full The photodiode 92 and the blocking diode 94 constitute an optical sensor element.
これらフォ トダイオード 9 2及びプロッキングダイォ一ド 9 4は、 と もに I T O ( Indi um Tin Oxi de) や Sn02 などから成る透明な下部電極 9 2 a , 9 4 aと、 アモルファスシリコン a-Siなどから成る p i n構造 の半導体層 9 2 b , 9 4 bと、 I T Oや Sn02 などから成る透明な上部 電極 9 2 c, 9 4 cとが、 順に堆積されて構成されている。 These photodiodes 9 2 and flop locking die O one de 9 4, and the monitor ITO (Indi um Tin Oxi de) and Sn0 2 transparent lower electrode consisting of a 9 2 a, 9 4 a, amorphous silicon a the semiconductor layer 9 2 b of the pin structure consisting of a -Si, 9 4 b and, ITO or transparent upper made of a Sn0 2 Electrodes 92c and 94c are sequentially deposited.
これらフォ トダイオード 9 2及びプロッキングダィォード 9 4は SiO x や SiNx などから成る透明な層間絶縁膜 9 6により覆われていて、 こ の層間絶縁膜 9 6に形成されたコンタク トホール 9 8を介して接続配線 1 0 0により互いに逆極性で直列接続されている。 すなわち、 フォ トダ ィォード 9 2とブロッキングダイォード 9 4 とはカソード電極同士で接 続されている。 一方、 フォ トダイォード 9 2の下部電極 9 2 aは層間絶 縁膜 9 6に形成されたコンタク トホール 1 0 2を介してチヤンネル配線 C. C2.... C に接続されている。 さらに、 これら全体は保護膜 1 0 4により覆われている。 These photodiodes 9 2 and flop locking da I O over de 9 4 is covered with SiO x or transparent interlayer made of a SiN x insulating film 9 6, contactors Tohoru 9 formed in the interlayer insulating film 9 6 This They are connected in series with opposite polarities by a connection wiring 100 via 8. That is, the photodiode 92 and the blocking diode 94 are connected by the cathode electrodes. On the other hand, the lower electrode 92 a of the photodiode 92 is connected to the channel wirings C. C 2 ... C via contact holes 102 formed in the interlayer insulating film 96. Further, the entirety is covered with a protective film 104.
また従来と同様に、 これらフォ トダイォ一ド 9 2及びブロッキングダ ィオード 9 4は一次元に mx n個配列され、 n個ごとに m個のブロック Β,. B2.... Bm に区分されていて、 ブロッキングダイオード 9 4のァ ノ一ド電極はプロック B ,. B2.... Bm 内で共通に接続され、 フォ トダ ィオード 9 2のァノ一ド電極はチヤンネル配線 C,. C2.... Cn によつ てブロック B ,. B2.... Bm 間で相対的に同一位置にあるもの同士で共 通に接続されている。 As in the conventional case, these photodiodes 92 and blocking diodes 94 are arranged in mxn units in one dimension, and are divided into m blocks Β, .B 2 ... B m every n units. have been, § Roh one cathode electrode of blocking diode 9 4 proc B,. B 2 .... are connected in common in a B m, follower Toda Iodo 9 2 § Roh once electrode channel interconnection C, . C 2 .... C n Niyotsu Te block B,. B 2 .... are in between those in the same relative position between B m are connected to the Common.
ここで、 この原稿読み取り装置 9 0の製造方法は、 前述の光センサ素 子の製造方法と同様に、 まず基板 1 2上に I TOや Sn02 などの透明導 電膜を堆積した後、 この上に、 アモルファスシリコン膜を p型、 i型、 n型の順に連続的に堆積し、 更にこの上に、 I T0や Sn02 などの透明 導電膜を堆積する。 この最上層の透明導電膜の膜厚は数百〜数千 A程度 が好ましいが、 アモルファスシリコン膜の性能や透明導電膜の特性など を考慮して適宜決定されるものである。 Here, the method for manufacturing a document reading apparatus 9 0, like the production method of the aforementioned light sensor element, after first depositing a transparent conductive film such as I TO and Sn0 2 on the substrate 1 2, this above, the amorphous silicon film a p-type, i-type, continuously deposited in the order of n-type, further on this is deposited a transparent conductive film such as an I T0 and Sn0 2. The thickness of the uppermost transparent conductive film is preferably about several hundred to several thousand A, but is appropriately determined in consideration of the performance of the amorphous silicon film, the characteristics of the transparent conductive film, and the like.
次いで、 最上層の透明導電膜と 3層から成るアモルファスシリ コン膜 とをフォ トリソグラフィ法などによってパターン化した後、 さらに最下 層の透明導電膜もフォ トリソグラフィ法などによってパターン化するこ とによってフォ トダイォ一 ド 9 2 とプロッ.キングダイォード 9 4 とを形 成する。 Next, after patterning the uppermost transparent conductive film and the three-layer amorphous silicon film by photolithography or the like, the lowermost transparent conductive film is also patterned by photolithography or the like. Thus, a photodiode 92 and a blocking diode 94 are formed.
次に、 これらフォ トダイオー ド 9 2 とブロッキングダイオー ド 9 4の 上に、 SiOx や SiNx などを堆積し、 これをフォ トリ ソグラフィ法など によって所定形状にパターン化して層間絶縁膜 9 6を形成する。 すなわ ち、 フォ トダイォード 9 2 とプロッキングダイォー ド 9 4の上にはコン タク トホール 9 8を、 下部電極 9 2 aの上にはコン夕ク トホール 1 0 2 を形成するとともに、 下部電極 9 4 a上の取出電極 1 0 6を形成する領 域については層間絶縁膜 9 6を除去するのである。 Next, formed on these follower Todaio de 9 2 and the blocking diode 9 4, and the like is deposited SiO x or SiN x, an interlayer insulating film 9 6 is patterned into a predetermined shape, such as by which the follower tri lithography method I do. That is, a contact hole 98 is formed on the photo diode 92 and the blocking diode 94, and a contact hole 102 is formed on the lower electrode 92a. In the region where the extraction electrode 106 is formed on the electrode 94a, the interlayer insulating film 96 is removed.
さらにこれらの上に、 真空蒸着法やスパッ夕リ ング法などによって Cr, Ni, Pd, Ti, Mo, Ta, Alなどの金属を単層又は多層に堆積し、 これをフ ォ ト リ ソグラフィ法などによって所定形状にパターン化することによつ て、 接続配線 1 0 0 とチャンネル配線 Cし C2.... C„ と取出電極 1 0 6とを形成する。 これにより、 上部電極 9 2 c, 9 4 c と接続配線 1 0 0 とがコンタク トホール 9 8を介して電気的に接続されるとともに、 下 部電極 9 2 aとチャンネル配線 C C2.... C„ とがコンタク トホール 1 0 2を介して電気的に接続されることになる。 なお、 これらの材料は 電気的接続が可能であれば金属でなくてもよいなど、 特に限定されるも のではない。 Further, a single layer or multiple layers of metals such as Cr, Ni, Pd, Ti, Mo, Ta, and Al are deposited thereon by a vacuum evaporation method, a sputtering method, or the like. The connection wiring 100 and the channel wiring C and C 2 ... C „and the extraction electrode 106 are formed by patterning into a predetermined shape by, for example, the upper electrode 9 2 c, 9 4 with c and line 1 0 0 and are electrically connected via a contactor Tohoru 9 8, the lower portion electrode 9 2 a and the channel line CC 2 .... C "and are contactor Tohoru 1 0 2 electrically. Note that these materials are not particularly limited, for example, they may not be metals as long as they can be electrically connected.
最後にこれら全体に、 プラズマ CVD法, スパッタリ ング法などによ つて酸化シリコン, 窒化シリ コン, 酸化タンタルなどを堆積し、 これを フォ トリ ソグラフィ法によって所定形状にパターン化することによって、 取出電極 1 0 6 とチャンネル配線 C ,. C2.... C„ の取出電極 (図示し ない) 以外の全領域を覆うように保護膜 1 0 4を形成する。 この保護膜 1 0 4はフォ トダイオード 9 2, ブロッキングダイオー ド 9 4, チャン ネル配線 C】. C2.... C„ などを湿気ゃキズから保護するためのもので あ o この原稿読み取り装置 9 0によると、 スィッチング素子であるプロッ キングダイォ一ド 9 4の下部電極 9 4 aが透明導電層から構成されてい るため、 半導体層 9 4 bと下部電極 9 4 aとの接合部に界面が形成され ている。 この界面には、 電位障壁や、 透明導電層を構成する下部電極 9 4 aの物質が半導体層 9 4 bに拡散して生じたトラップ準位などのバリ ァが形成されていると考えられる。 したがって、 ブロック Β , . B 2. . . . B ra が読出状態から蓄積状態に切り換わった直後に流れる逆方向電流 IrFinally, silicon oxide, silicon nitride, tantalum oxide, etc. are deposited on the entire surface by plasma CVD, sputtering, or the like, and are patterned into a predetermined shape by photolithography to obtain the extraction electrode 1. A protective film 104 is formed so as to cover all regions except for the extraction electrodes (not shown) of the channel wirings C 6 and C 2 .. C 2 .. C „. diode 9 2, blocking diode 9 4, channel wiring C]. C 2 .... C "Oh intended to protect from moisture Ya scratches, etc. o According to this original reading device 90, since the lower electrode 94a of the blocking diode 94, which is a switching element, is made of a transparent conductive layer, the semiconductor layer 94b and the lower electrode 94a are joined. An interface is formed in the part. It is considered that a potential barrier and a barrier such as a trap level formed by the substance of the lower electrode 94a constituting the transparent conductive layer being diffused into the semiconductor layer 94b are formed at this interface. Therefore, the block Β,. B 2... . B ra is reverse current flows immediately after switched from the read state to the storage state Ir
Ir2. . . . Irn のほとんどは、 このバリアによって阻止されると考えら れ、 逆方向電流 I , lr2. . . . Ir„ は 1 (T5〜 l 0 秒のオーダ一で収束 させられ、 かつ、 そのピーク値も小さくなる。 これにより、 ブロッキン グダィォ一ド 1 2 0のスィツチング速度は向上させられ、 反転残像は大 幅に低減される。 よって、 正確な信号出力が得られることは勿論、 信号 読み出し速度をより速めることも可能である。 さらに、 反転残像は十分 に低減されているため、 低照度下で原稿を読み取らせた場合でも正確な 信号出力を確保することができ、 消費電力の低減などを図ることもでき る。 なお、 前述と同様に、 スイッチング素子であるブロッキングダイォ ―ド 9 4の下部電極 9 4 aが透明導電層から構成されているため、 周辺 からの漏光がプロッキングダイォード 9 4の半導体層 9 4 bに入射する ことにより再結合準位が増加して再結合速度が速くなることも原因と考 えられる。 Ir 2 ... Ir n is considered to be blocked by this barrier, and the reverse current I, lr 2 ... Ir „converges to 1 (on the order of T 5 to 10 seconds). As a result, the switching speed of the blocking diode 120 is improved, and the reversal afterimage is greatly reduced, so that an accurate signal output can be obtained. Of course, it is also possible to increase the signal reading speed, and since the reversal afterimage is sufficiently reduced, an accurate signal output can be secured even when the original is read under low illuminance. As described above, the lower electrode 94a of the blocking diode 94, which is a switching element, is made of a transparent conductive layer, so that it is possible to reduce power consumption. Light leakage Ngudaiodo 9 4 of the semiconductor layer 9 4 also causes the recombination rate recombination level is increased is increased by entering the b and considered Erareru.
次に、 このような効果を確認するため、 本発明に係る原稿読み取り装 置の実施例と、 従来の原稿読み取り装置の比較例とを作製して比較実験 を行なったので、 以下これについて説明する。  Next, in order to confirm such effects, an embodiment of the document reading apparatus according to the present invention and a comparative example of a conventional document reading apparatus were prepared and a comparative experiment was performed. .
実施例 1 Example 1
まず、 本発明に係る原稿読み取り装置は次に示す方法によって作製し た。  First, the original reading apparatus according to the present invention was manufactured by the following method.
基板 1 2にはコ一ニング社製の無アル力リガラス (# 7 0 5 9 ) を用 レ、、 まずこの基板 1 2上に D Cスパッ夕リ ング法によって 1 2 0 0 A厚 の I TO膜を堆積した。 すなわち、 基板 1 2をチヤンバ一内にセッ トし、 そのチャンバ一内を 1 0— 5Torr以下まで排気した後、 その基板 1 2を 1 0 0〜 2 5 0てに保持し、 圧力 0. 1〜 1. 0 P a、 D C電力 0. 1〜 1. 0 W/cm2 の下で、 アルゴンガスと酸素ガスとを一定の割合で導 入することによって、 基板 1 2上に I TO膜を堆積した。 さらにこの上 に、 プラズマ CVD法により、 5 0〜3 0 0 A厚の p型アモルファスシ リ コン膜と、 7 0 0 0〜 1 2 0 0 0 A厚の i型アモルファスシリコン膜 と、 5 0〜3 0 0 A厚の n型アモルファスシリ コン膜とを順番に堆積し た。 そして再度この上に、 前述した I TO膜と同じ方法で 6 0 0 A厚の .1 TO膜を堆積した。 Substrate 1 and 2 are made of Corning Co., Ltd. Al-free glass (# 7005) First, an ITO film having a thickness of 1200 A was deposited on the substrate 12 by a DC sputtering method. That is, set the substrate 1 2 Chiyanba in one, was evacuated and the chamber in one to 1 0- 5 Torr or less, and holds the substrate 1 2 1 0 0-2 5 0 hands, pressure 0. 1 to 1.0 Pa, DC power 0.1 to 1.0 W / cm 2 , by introducing argon gas and oxygen gas at a constant rate, the ITO film on the substrate 12 Was deposited. Furthermore, a p-type amorphous silicon film having a thickness of 500 to 300 A, an i-type amorphous silicon film having a thickness of 700 to 1200 A, and a An n-type amorphous silicon film having a thickness of about 300 A was sequentially deposited. Then, a .1TO film having a thickness of 600 A was deposited thereon again in the same manner as the ITO film.
次いで、 最上層の I TO膜と 3層から成るアモルファスシリ コン膜と をフォ トリソグラフィ法によってパターン化し、 上部電極 9 2 c, 9 4 · cと半導体層 9 2 b, 9 4 bとを形成した。 すなわち、 最上層の I TO 膜上にレジスト液を塗布し、 プリべ一クをした後、 所定のパターンが刻 まれたマスクを用いて露光を行ない、 さらに現像及びボス卜べ一クを行 なった。 そして、 塩酸と硝酸の混合液によって I TO膜をエッチングし た後、 平行平板型のエッチング装置を用いてアモルファスシリコン膜を エッチングした。 ここでは、 チャンバ一内を 1 0 -3Torr以下まで排気し た後、 CF4 ガスと 02 ガスを導入し、 圧力を 5. 0 P aに保持しながら 1 3. 5 6MHz の高周波電源を用いて電極に 0. 1〜0. 7 W/ c m 2 の電力を供給し、 アモルファスシリコン膜をエッチングした。 そしてパ ターニングに用いたレジストを除去した後、 前述した最上層の I TO膜 と同様に、 最下層の I TO膜もフォ トリソグラフィ法によってパターン 化し、 下部電極 9 2 a, 9 4 aを形成した。 Next, the uppermost ITO film and the three-layer amorphous silicon film are patterned by photolithography to form upper electrodes 92c, 94c and semiconductor layers 92b, 94b. did. In other words, a resist solution is applied on the uppermost ITO film, pre-baked, exposed using a mask engraved with a predetermined pattern, and further developed and boost-baked. Was. Then, after etching the ITO film with a mixed solution of hydrochloric acid and nitric acid, the amorphous silicon film was etched using a parallel plate type etching apparatus. Here, the chamber one 1 0 - was evacuated to 3 Torr or less, introducing a CF 4 gas and 0 2 gas, a high frequency power source 1 3. 5 6 MHz while maintaining the pressure to 5. 0 P a A power of 0.1 to 0.7 W / cm 2 was supplied to the electrodes to etch the amorphous silicon film. Then, after removing the resist used for patterning, the lowermost ITO film is patterned by photolithography in the same manner as the uppermost ITO film described above to form lower electrodes 92a and 94a. did.
なお、 フォ トダイオード 9 2及びブロッキングダイォード 9 4の数は それぞれ 1 7 2 8個とし、 これらを 3 2個ごとに 5 6個のブロックに区 分した。 また第 1 4図に示すように、 フォ トダイオード 9 2のサイズは 1 0 5 zm X 1 2 5〃mとし、 ブ□ッキングダイォード 9 4のサイズは 3 3 mx 3 3 zmとした。 The numbers of the photodiodes 92 and the blocking diodes 94 are assumed to be 1728, respectively, and these are divided into 56 blocks every 32. Minutes. Further, as shown in FIG. 14, the size of the photodiode 92 was set to 105 zm × 125 μm, and the size of the booking diode 94 was set to 33 mx 33 zm.
次に、 これらフォ トダイオード 9 2とブロッキングダイオード 9 4の 上に、 プラズマ C VD法によって 1. 5〃m厚のシリコン酸化膜を堆積 した。 すなわち、 チャンバ一内を 1 0— 2Torr以下まで排気した後、 基板 1 2を所定温度に加熱保持し、 シランガス 2 0〜6 0 seemと、 亜酸化窒 素ガス 1 5 0〜3 0 O sccmを導入し、 0. 3〜1. 2Torrの圧力に保持 した (ここで、 必要に応じて窒素ガスを導入することもある。 ) 。 その 後、 圧力が安定するのを待って、 1 3. 5 6 MH zの高周波電源を用い て基板 1 2と対面する電極に 0. 0 1〜0. 5W/cm2 の電力を供給 してシリコン酸化膜を堆積した。 次いで、 フォ トリソグラフィ法によつ て所定形状にパターン化して層間絶縁膜 9 6を形成した。 ここでのエツ チングには平行平板型のェッチング装置を用いた。 Next, a silicon oxide film having a thickness of 1.5 μm was deposited on the photodiode 92 and the blocking diode 94 by a plasma CVD method. That is, after evacuating the inside of the chamber one to 1 0- 2 Torr or less, and heating and holding the substrate 1 2 to a predetermined temperature, silane gas 2 Less than six 0 seem and, nitrous oxide gas 1 5 0 to 3 0 O sccm , And maintained at a pressure of 0.3 to 1.2 Torr (here, nitrogen gas may be introduced if necessary). After that, wait for the pressure to stabilize, and then supply electric power of 0.01 to 0.5 W / cm 2 to the electrode facing the substrate 12 using a high-frequency power supply of 13.56 MHz. A silicon oxide film was deposited. Next, the resultant was patterned into a predetermined shape by photolithography to form an interlayer insulating film 96. Here, a parallel plate type etching apparatus was used for the etching.
さらにこれらの上に、 スパッ夕リング法によって Crと A1の 2層を堆積 し、 フォ トリソグラフィ法によって所定形状にパターン化して、 接続配. 線 1 0 0とチャンネル配線 C ,. C2.... Cn と取出電極 1 0 6 とを形成 した。 ここで、 Crの膜厚は 5 0 0 A厚とし、 A1の膜厚は 1. 5 とし た。 また、 A1のエッチングは、 燐酸、 塩酸、 硝酸及び酢酸の混合液で行 ない、 Crのエッチングは硝酸第 2セリゥムアンモニゥムで行なった。 Furthermore, two layers of Cr and A1 are deposited on these by the sputtering method, patterned into a predetermined shape by the photolithography method, and the connection wiring 100 and the channel wirings C, C 2 .. .. to form a C n and the lead electrode 1 0 6. Here, the thickness of Cr was 500 A, and the thickness of A1 was 1.5. The etching of A1 was performed with a mixture of phosphoric acid, hydrochloric acid, nitric acid and acetic acid, and the etching of Cr was performed with a second cell ammonium nitrate.
最後にこれら全体に、 プラズマ CVD法によって 5 0 0 0 A厚のシリ コン窒化膜を堆積した。 すなわち、 チャンバ一内を 1 0 _2Torr以下まで 排気した後、 基板 1 2を所定温度に加熱保持し、 シランガス 2 0〜 6 0 sccmと、 アンモニアガス 1 5 0〜 3 0 0 sccmを導入し、 0. 3〜1. Finally, a 5,000 A thick silicon nitride film was deposited on all of them by plasma CVD. That is, after evacuating the inside of the chamber one to 1 0 _ 2 Torr or less, and heating and holding the substrate 1 2 to a predetermined temperature, introducing the silane gas 2 0 to 6 0 sccm, ammonia gas 1 5 0~ 3 0 0 sccm , 0.3-1.
Torrの圧力に保持した (ここで、 必要に応じて水素ガスや窒素ガスを導 入することもある。 ) 。 その後、 圧力が安定するのを待って、 1 3. 5 6 MH zの高周波電源を用いて基板 1 2と対向する電極に 0. 0 1〜 0. 5WZcm2 の電力を供給して、 シリコン窒化膜を堆積した。 次いで、 フォ トリソグラフィ法によって所定形状にパターン化して、 保護膜 1 0 4を形成した。 ここでのエッチングにも平行平板型のエッチング装置を 用いた。 The pressure was maintained at Torr (here, hydrogen gas or nitrogen gas may be introduced as necessary). After that, wait for the pressure to stabilize, and then use a high frequency power supply of 13.56 MHz to apply a voltage of 0.01 to 0 to the electrode facing the substrate 12. A power of 5 WZcm 2 was supplied to deposit a silicon nitride film. Next, the resultant was patterned into a predetermined shape by photolithography to form a protective film 104. A parallel plate type etching apparatus was used for the etching here.
比較例 1 Comparative Example 1
一方、 従来の原稿読み取り装置の比較例としては、 前述した実施例 1 と下部電極 9 2 a, 9 4 aの材料のみ異なるものを作製した。 すなわち、 前述した I TO膜に代えて、 1 5 0 0 ~ 2 0 0 0人厚のクロム膜をスパ ッ夕リ ング法によって堆積し、 これをフォ トリソグラフィ法によってパ ターン化することによって、 不透明な下部電極 9 2 a, 9 4 aを形成し た。  On the other hand, as a comparative example of the conventional manuscript reading apparatus, a manuscript reading apparatus different from the above-described embodiment 1 only in the material of the lower electrodes 92a and 94a was manufactured. That is, instead of the above-mentioned ITO film, a chromium film having a thickness of 1500 to 2000 persons is deposited by the sputtering method, and this is patterned by the photolithography method. Opaque lower electrodes 92a and 94a were formed.
次に、 これらの実施例 1 と比較例 1 とに駆動回路と信号処理回路とを 接続し、 クロックパルスの周波数を 5 0 0 KH z、 読み取り速度を 5 m sec Zlineとして、 白から黒に変化する原稿を 2 0ルクスの照度で照明 して読み取らせた。 この結果、 信号処理回路からは第 1 5図に示すよう な出力電圧 Vout が得られた。 なお本図において、 実線は実施例の出力 電圧 Vout を示し、 点線は比較例の出力電圧 Vout を示す。  Next, a driving circuit and a signal processing circuit were connected to the first embodiment and the first comparative example, and the frequency of the clock pulse was set to 500 kHz, the reading speed was set to 5 msec Zline, and the color was changed from white to black. The document to be read was illuminated with an illumination of 20 lux and read. As a result, an output voltage Vout as shown in FIG. 15 was obtained from the signal processing circuit. In this figure, the solid line indicates the output voltage Vout of the example, and the dotted line indicates the output voltage Vout of the comparative example.
このように、 白を読み取った直後の出力電圧 Vout には反転残像 Vr が現れ、 これが白を読み取った直後に読み取った黒は通常の黒よりも黒 くなる原因となっている。 しかし、 実施例 1の反転残像 Vr は比較例 1 の反転残像 Vr よりも小さくなり、 その収束時間も短くなつた。 その結 果をまとめたものを第 1表に示す。 ここでは、 白に相当する出力電圧 V out 〖ま 1 6 0〜 1 8 0 mVであった。 第 1 表 As described above, the inverted image Vr appears in the output voltage Vout immediately after reading white, which causes black read immediately after reading white to be blacker than normal black. However, the reversal afterimage Vr of Example 1 was smaller than the reversal afterimage Vr of Comparative Example 1, and the convergence time was shorter. Table 1 summarizes the results. Here, the output voltage V out corresponding to white was 160 to 180 mV. Table 1
Figure imgf000033_0001
Figure imgf000033_0001
以上、 本発明に係る原稿読み取り装置の一実施例を詳述したが、 本発 明は上述した実施例に限定されることなく、 その他の態様でも実施し得 るものである。 As described above, the embodiment of the document reading apparatus according to the present invention has been described in detail. However, the present invention is not limited to the above-described embodiment, and can be implemented in other aspects.
たとえば上述した実施例では、 フォ トダイォ一ド 9 2を構成する上部 電極 9 2 cと、 ブロッキングダイオード 9 4を構成する上部電極 9 4 c とが接続配線 1 0 0によって接続されているが、 第 1 6図に示すように、 フォ トダイオード 9 2を構成する下部電極 1 0 8と、 ブロッキングダイ オード 9 4を構成する下部電極 1 0 8とが共通になっていて、 この下部 電極 1 0 8によってフォ トダイオード 9 2とブロッキングダイオード 9 4とが接続されて成る原稿読み取り装置 1 1 0でもよい。 この場合、 下 部電極 1 0 8は I T Oなどから形成される。 また、 フォ トダイオード 9 2の上部電極 9 2 cは層間絶縁膜 9 6に形成されたコンタク トホール 9 8を介して引出配線 1 1 2によって取り出し、 且つコンタク トホール 1 0 2を介してチャンネル配線 C C 2. . . . C„ に接続し、 また、 ブロッ キングダイオード 9 4の上部電極 9 4 cはコンタク トホール 9 8を介し て引出配線 1 1 4によって外部に取り出して構成される。 本例では、 フ ォ トダイオード 9 2とブロッキングダイオード 9 4 とはァノ一ド電極同 士で接続され、 互いに逆極性で直列接続されていることになる。 For example, in the above-described embodiment, the upper electrode 92c constituting the photodiode 92 and the upper electrode 94c constituting the blocking diode 94 are connected by the connection wiring 100. As shown in FIG. 16, the lower electrode 108 forming the photodiode 92 and the lower electrode 108 forming the blocking diode 94 are common, and the lower electrode 108 The document reading device 110 may be a device in which the photodiode 92 and the blocking diode 94 are connected to each other. In this case, the lower electrode 108 is formed of ITO or the like. Further, the upper electrode 92 c of the photodiode 92 is taken out by a lead wire 112 through a contact hole 98 formed in the interlayer insulating film 96, and the channel wire CC is connected through a contact hole 102. 2 ... C „, and the upper electrode 94 c of the blocking diode 94 is drawn out to the outside by a lead wire 114 through a contact hole 98. In this example, The photodiode 92 and the blocking diode 94 are connected by the same anode electrode, and are connected in series with opposite polarities.
また上述した実施例では、 プロッキングダイォード 9 4のアノード電 極又は力ソ一ド電極がプロック B , . B 2. . . . B m 内で共通に接続され、 フォ トダイオー ド 9 2のァノ一ド電極又は力ソ一 ド電極がチャンネル配 線 d . C s . . . . C n によってブロック B B 2. . . . B m 間で相対的に同 一位置にあるもの同士で接続されているが、 フォ トダイォードとブ口ッ キングダイォードの配置を逆にして、 フォ トダイォードのァノード電極 又は力ソ一ド電極をプロック内で共通に接続し、 プロッキングダイォー ドのァノード電極又は力ソード電極をチヤンネル配線によってプロック 間で相対的に同一位置にあるもの同士で接続したものでもよい。 すなわ ち、 フォ トダイオード (光電変換素子) とプロッキングダイォード (ス ィツチング素子) とから構成される光センサ素子が一次元に複数配列さ れ、 一定個数ごとに複数のブロックに区分されていて、 これら光センサ 素子のいずれか一方がプロック内で共通に接続され、 当該他方がチャン ネル配線によってプロック間で相対的に同一位置にあるもの同士で共通 に接続されていればよいのである。 In the embodiment described above, the anode electrodes or Chikarasoichido electrode flop locking die O over de 9 4 proc B,. B 2... . Are connected in common in a B m, Follower Todaio de 9 2 § Roh once electrode or Chikarasoichi de electrode channel wiring d. C s.... Block BB 2 by C n.... Relatively same position between B m Although they are connected to each other, the arrangement of the photodiode and the blocking diode is reversed, and the anode electrode or force electrode of the photodiode is connected in common in the block, and the blocking diode is connected. Anode electrodes or force source electrodes may be connected to each other at a relatively same position between blocks by channel wiring. That is, a plurality of optical sensor elements, each composed of a photodiode (photoelectric conversion element) and a blocking diode (switching element), are arranged one-dimensionally, and are divided into a plurality of blocks every fixed number. It is only necessary that one of these optical sensor elements is commonly connected in the block, and that the other is commonly connected by the channel wiring to those at relatively the same position between the blocks.
また上述した実施例では、 製造工程の簡素化などの理由から、 フォ ト ダイオード 9 2及びブロッキングダイォ一ド 9 4を構成するそれぞれの 下部電極 9 2 a , 9 4 a、 半導体層 9 2 b , 9 4 b及び上部電極 9 2 c , 9 4 cはそれぞれ同時に堆積されたものであるため、 それぞれは同じ材 料から構成されているが、 フォ トダイオード 9 2を構成する上部電極 9 2 cは透明でなければならないが、 ブロッキングダイォ一ド 9 4を構成 する上部電極 9 4 cは透明でなくてもよい。 また、 フォ トダイオード 9 2を構成する下部電極 9 2 aも透明でなくてもよく、 少なく ともブロッ キングダイォード (スィツチング素子) 9 4を構成する下部電極 9 4 a が透明であればよい。  In the above-described embodiment, the lower electrodes 92 a and 94 a and the semiconductor layer 92 b constituting the photodiode 92 and the blocking diode 94 are formed for reasons such as simplification of the manufacturing process. , 94 b and the upper electrodes 92 c, 94 c are deposited simultaneously, so they are each composed of the same material, but the upper electrode 92 c constituting the photodiode 92 is formed. Must be transparent, but the upper electrode 94 c constituting the blocking diode 94 may not be transparent. Also, the lower electrode 92 a constituting the photodiode 92 may not be transparent, and at least the lower electrode 94 a constituting the blocking diode (switching element) 94 may be transparent.
以上、 本発明に係る半導体装置である原稿読み取り装置を、 それを構 成するスィツチング素子であるプロッキングダイォ一ド 9 4の下部電極 を少なく とも透明導電層により構成した実施例を説明したが、 本発明に 係る原稿読み取り装置においては、 少なく ともスィツチング素子を構成 する下部電極が、 1層以上の金属層とその金属層の上に堆積される透明 導電層とから構成されていてもよい。 次に、 かかる構成の原稿読み取り 装置の実施例を図面に基づき詳しく説明する。 As described above, the embodiment in which the original reading apparatus which is the semiconductor device according to the present invention has the lower electrode of the blocking diode 94 which is the switching element constituting the original reading apparatus constituted by at least the transparent conductive layer has been described. In the document reading apparatus according to the present invention, at least a switching element is configured. The lower electrode may be composed of at least one metal layer and a transparent conductive layer deposited on the metal layer. Next, an embodiment of the document reading apparatus having such a configuration will be described in detail with reference to the drawings.
第 1 7図及び前述の第 1 4図に示すように、 本発明に係る原稿読み取 り装置 1 1 6はガラスなどから成る基板 1 2上に、 光電変換素子である フォ トダイオード 1 1 8と、 スィツチング素子であるプロッキングダイ オード 1 2 0と、 フォ トダイオード 1 1 8からの電気信号を読み出すた めのチャンネル配線 C,. C2.... C とが形成されて構成されている。 ここでは、 フォ トダイオード 1 1 8とブロッキングダイオード 1 2 0と により光センサ素子が構成されている。 As shown in FIG. 17 and FIG. 14 described above, the original reading apparatus 1 16 according to the present invention includes a photodiode 1 18 as a photoelectric conversion element on a substrate 12 made of glass or the like. , a flop locking diode 1 2 0 is Suitsuchingu element, photodiode 1 1 8 and the channel line C ,. C 2 .... C of order to read out the electric signals from has to be constituted by forming . Here, an optical sensor element is constituted by the photodiode 118 and the blocking diode 120.
これらフォ トダイオード 1 1 8及びプロッキングダイオード 1 2 0は、 ともに二層構造の下部電極 1 1 8 a, 1 2 0 aと、 ァモルファスシリコ ンなどから成る p i n構造の半導体層 1 1 8 b, 1 2 0 bと、 I TO (Indium Tin Oxide) などから成る透明な上部電極 1 1 8 c, 1 2 0 c とが順に堆積されて構成されている。 これら下部電極 1 1 8 a, 1 2 0 aは、 Cr, Ni, Pd, Ti, Mo, Ta, Alなどから成る金属層 1 1 8 a , , 1 2 0 a , と、 I TO, Sn02 , Ti02 などから成る透明導電層 1 1 8 a 2 , 1 2 0 a 2 とから構成されている。 Each of the photodiode 118 and the blocking diode 120 has a lower electrode 118 a, 120 a having a two-layer structure, and a semiconductor layer 118 b having a pin structure made of amorphous silicon or the like. , 120b and transparent upper electrodes 118c, 120c made of ITO (Indium Tin Oxide) or the like are sequentially deposited. These lower electrode 1 1 8 a, 1 2 0 a is, Cr, Ni, Pd, Ti , Mo, Ta, and the like Al metal layer 1 1 8 a,, 1 2 0 a, a, I TO, Sn0 2 , and a Ti0 2 transparent conductive layer made of a 1 1 8 a 2, 1 2 0 a 2 Prefecture.
また、 フォ トダイオード 1 1 8及びブロッキングダイオード 1 2 0は 前述の実碓例と同様に、 透明な層間絶縁膜 9 6により覆われていて、 こ の層間絶縁膜 9 6に形成されたコンタク トホール 9 8を介して接続配線 1 0 0により互いに逆極性で直列接続されている。 一方、 フォ トダイォ ード 1 1 8の下部電極 1 1 8 aは層間絶縁膜 9 6に形成されたコンタク トホール 1 0 2を介してチャンネル配線 C C2.... C„ に接続され、 さらに、 これら全体は保護膜 1 0 4により覆われて構成されている。 ま た、 その他の構成も前述の実施例 同様に構成されている。 The photodiode 118 and the blocking diode 120 are covered with a transparent interlayer insulating film 96 as in the above-described embodiment, and the contact holes formed in the interlayer insulating film 96 are formed. They are connected in series with opposite polarities by connecting wires 100 through 98. On the other hand, the lower electrode 1 18 a of the photodiode 1 18 is connected to the channel wiring CC 2 ... C „via a contact hole 102 formed in the interlayer insulating film 96, These components are entirely covered with a protective film 104. Other configurations are the same as those of the above-described embodiment.
ここで、 この原稿読み取り装置 1 1 6の製造方法の一例を前述とは異 なる点を主として簡単に説明する。 Here, an example of a method of manufacturing the original reading device 116 is different from the above. The point will be mainly described briefly.
まず基板 1 2上に、 電子ビームや抵抗加熱による真空蒸着法、 あるい は D Cや R Fによるスパッタリング法などによって、 Cr, Ni, Pd, Ti, Mo, Ta, Alなどの金属膜を堆積する。 次いでこの上に、 真空蒸着法ゃス パッタリング法などによって I T Oや Sn02 などの透明導電膜を堆積す る。 さらにこの上に、 アモルファスシリコン膜を p型、 i型、 n型の順 に連続的に堆積し、 更にこの上に、 透明導電膜を堆積する。 なお、 金属 膜及び透明導電膜の膜厚は数百〜数千 A程度が好ましいが、 これらの膜 の特性や、 アモルファスシリコン膜の性能などを考慮して適宜決定され るものである。 次いで、 フォ トリソグラフィ法などによって、 上層の透 明導電膜と、 3層から成るアモルファスシリコン膜と、 下層の透明導電 膜とを所定形状にパターン化した後、 金属膜を別の所定形状にパターン 化することによって、 フォ トダイオード 1 1 8とブロッキングダイォ一 ド 1 2 0を形成する。 First, a metal film such as Cr, Ni, Pd, Ti, Mo, Ta, or Al is deposited on the substrate 12 by a vacuum deposition method using an electron beam or resistance heating, or a sputtering method using DC or RF. Then on this, it deposits a transparent conductive film such as ITO or Sn0 2 by vacuum deposition Yasu sputtering method. Further, an amorphous silicon film is successively deposited thereon in the order of p-type, i-type, and n-type, and a transparent conductive film is further deposited thereon. The thickness of the metal film and the transparent conductive film is preferably about several hundreds to several thousand A, but is appropriately determined in consideration of the characteristics of these films and the performance of the amorphous silicon film. Next, the upper transparent conductive film, the three-layer amorphous silicon film, and the lower transparent conductive film are patterned into a predetermined shape by photolithography or the like, and then the metal film is patterned into another predetermined shape. Thus, a photodiode 118 and a blocking diode 120 are formed.
次いで、 これらフォ トダイオード 1 1 8 とブロッキングダイオード 1 2 0の上に、 常法により Si Ox や SiNx などを堆積した後、 これを所定 形状にパターン化することによって層間絶縁膜 9 6を形成する。 このと き、 フォ トダイオード 1 1 8、 ブロッキングダイオード 1 2 0及び金属 層 1 1 8 a , 上の所定位置にはコンタク トホール 9 8, 1 0 2を形成す るとともに、 金属層 1 2 0 a , 上の取出電極 1 0 6を形成する領域につ いては層間絶縁膜 9 6を除去する。 Then, on these photodiodes 1 1 8 and the blocking diode 1 2 0, after depositing and Si O x and SiN x by a conventional method, an interlayer insulating film 9 6 by patterning into a predetermined shape Form. At this time, contact holes 98 and 102 are formed at predetermined positions on the photodiode 118, the blocking diode 120 and the metal layer 118a, and the metal layer 120a is formed. On the other hand, in the region where the upper extraction electrode 106 is to be formed, the interlayer insulating film 96 is removed.
さらにこれらの上に、 常法によって金属を単層又は多層に堆積した後、 これを所定形状にパターン化することによって、 接続配線 1 0 0 とチヤ ンネル配線 C , . C 2. . . . C„ と取出電極 1 0 6とを形成する。 これによ り、 上部電極 1 1 8 c, 1 2 0 c同士が接続配線 1 0 0により電気的に 接続され、 金属層 1 1 .8 a , とチヤンネル配線 C C 2. . . . C„ と 電 気的に接続されることになる。 なお、 これらの 料は電気的接続が可能 であれば金属でなくてもよく、 特に限定されるものではない。 最後にこ れら全体に、 酸化シリコン, 窒化シリコン, 酸化タンタルなどを堆積し た後、 これを所定形状にパターン化することによって、 取出電極 1 0 0 とチヤンネル配線 C】. C2.... c „ の取出電極 (図示しない) 以外の全 領域を覆うように保護膜 1 0 4を形成する。 Further, on these, after depositing a metal single layer or multilayer by a conventional method by patterning into a predetermined shape, line 1 0 0 and Chiya tunnel line C,. C 2... . C „And the extraction electrode 106 are formed, whereby the upper electrodes 118c and 120c are electrically connected to each other by the connection wiring 100, and the metal layers 11.8a, And the channel wiring CC 2 ... C „. These charges can be connected electrically. If it is, it does not need to be a metal and is not particularly limited. Throughout these last, silicon oxide, silicon nitride, after depositing and tantalum oxide, by patterning into a predetermined shape, the extraction electrodes 1 0 0 and channel line C]. C 2 ... A protective film 104 is formed so as to cover the entire region except for the c 電極 extraction electrode (not shown).
ここでは、 金属膜と透明導電膜とをブランケッ ト状態で堆積した後、 アモルファスシリコン膜を堆積している力、 このアモルファスシリ コン 膜を堆積する前に、 透明導電膜だけを先にパターン化して透明導電層 1 1 8 a 2 , 1 2 0 a 2 を形成しておいてもよい。 この場合は、 上部電極 1 1 8 c, 1 2 0 cと半導体層 1 1 8 b, 1 2 0 bとを形成した後、 ブ ランケッ ト状態の金属膜をパターン化して金属層 1 1 8 a , , 1 2 0 a . を形成すれば、 前述した原稿読み取り装置 1 1 6と同じ構成となる。 また、 金属層と透明導電層との堆積は真空を破らずに連続的に行なって もよいし、 一度、 真空を破って不連続的に行なってもよい。 さらにここ では、 主としてフォ トリソグラフィ法によってパターン化する方法を例 示したが、 マスク法などによって最初から不必要な部分には膜が堆積さ れないようにして形成してもよく、 その製造方法は何ら限定されるもの ではない。  Here, after depositing the metal film and the transparent conductive film in a blanket state, the force for depositing the amorphous silicon film, and before depositing the amorphous silicon film, the transparent conductive film alone is first patterned. The transparent conductive layers 1 18 a 2 and 120 a 2 may be formed in advance. In this case, after the upper electrodes 118c, 120c and the semiconductor layers 118b, 120b are formed, the metal film in the blanket state is patterned to form the metal layer 118a. ,, 120 a., The configuration is the same as that of the original reading device 1 16 described above. Further, the deposition of the metal layer and the transparent conductive layer may be performed continuously without breaking the vacuum, or may be performed discontinuously once the vacuum is broken. Furthermore, here, a method of patterning mainly by photolithography has been described as an example, but a film may be formed by using a mask method or the like so that a film is not deposited on unnecessary portions from the beginning. Is not limited at all.
この原稿読み取り装置 1 1 6では、 下部電極 1 2 0 aが金属層 1 2 0 a, と透明導電層 1 2 0 a2 とから構成されているため、 半導体層 1 2 0 bと透明導電層 1 2 0 a 2 の接合部に界面が形成されている。 この界 面には、 電位障壁や、 透明導電層 1 2 0 a 2 を構成する物質が半導体層 1 2 0 bに拡散して生じたトラップ準位などのバリァが形成されている と考えられる。 したがって、 前述の原稿読み取り装置 9 0と同様に作動 させられるものと考えられ、 その結果、 同様の効果が得られる。 In this original reading device 1 16, since the lower electrode 120 a is composed of the metal layer 120 a and the transparent conductive layer 120 a 2 , the semiconductor layer 120 b and the transparent conductive layer interface is formed at the junction of the 1 2 0 a 2. This is interfacial potential barrier and is considered to Baria such as a transparent conductive layer 1 2 0 a 2 trap level substance constituting occurs diffused into the semiconductor layer 1 2 0 b a is formed. Therefore, it is considered that the same operation as that of the above-described original reading apparatus 90 is performed, and as a result, the same effect is obtained.
このような効果を確認するため、 本実施例に係る原稿読み取り装置を 作製して前述の比較例 1 と比較実験を行なった。 実施例 2 In order to confirm such effects, a document reading apparatus according to the present example was manufactured, and a comparative experiment was performed with Comparative Example 1 described above. Example 2
まず、 本実施例に係る原稿読み取り装置は次に示す方法によって作製 した。  First, the document reading apparatus according to the present example was manufactured by the following method.
基板 1 2にはコ一二ング社製の無アル力リガラス (# 7 0 5 9 ) を用 レ、、 まずこの基板 1 2上に DCスパッ夕リング法によって 1 5 0 0〜2 0 0 0 A厚のクロム膜を堆積し、 さらに 6 0 0 A厚の I TO膜を堆積し た。 具体的には、 基板 1 2をチヤンバ一内にセッ トし、 そのチヤンバー 内を 1 0 _5Torr以下まで排気した後、 その基板 1 2を 1 0 0〜 2 5 0 °C に保持し、 圧力 0. 1〜し 0 P a、 D C電力 0. 1〜 1. OW/c m 2 の下で、 アルゴンガスと酸素ガスとを一定の割合で導入することによ つて、 クロム膜と I TO膜とを順番に堆積した。 さらにこの上に、 実施 例 1 と同様に、 アモルファスシリコン膜を p型、 i型、 n型の順番に堆 積し、 更にこの上に、 I TO膜を堆積した。 The substrate 12 is made of Al-free glass (# 7509) manufactured by Koingen Co., Ltd. First, the substrate 12 is placed on the substrate 12 by the DC sputtering method. An A thick chromium film was deposited, followed by a 600 A thick ITO film. Specifically, it sets the substrate 1 2 Chiyanba in one, after evacuating the inside of the Chiyanba until 1 0 _ 5 Torr or less, and holds the substrate 1 2 1 0 0~ 2 5 0 ° C , Chromium film and ITO film by introducing argon gas and oxygen gas at a constant rate under pressure 0.1 to 0 Pa, DC power 0.1 to 1. OW / cm 2 And were sequentially deposited. Further, as in Example 1, an amorphous silicon film was deposited thereon in the order of p-type, i-type, and n-type, and an ITO film was further deposited thereon.
次いで実施例 1 と同様に、 上層の I TO膜と、 3層から成るァモルフ ァスシリコン膜と、 下層の I TO膜とを所定形状にパターン化し、 上部 電極 1 1 8 c, 1 2 0 cと、 半導体層 1 1 8 b, 1 2 0 bと、 下部電極 1 1 8 a, 1 2 0 aの一部である透明導電層 1 1 8 a 2 , 1 2 0 a 2 と を形成した。 なお、 下部電極 1 1 8 a, 1 2 0 aの一部である透明導電 層 1 1 8 a 2 , 1 2 0 a 2 は、 上部電極 1 1 8 c, 1 2 0 c及び半導体 層 1 1 8 b, 1 2 0 bのパターニングに用いたレジストにより、 塩酸と 硝酸の混合液によって下層の I TO膜をエッチングして形成した。 次い で、 パターニングに用いたレジストを除去した後、 フォ トリソグラフィ 法によってクロム膜を所定形状にパターン化し、 下部電極 1 1 8 a, 1 2 0 aの一部である金属層 1 1 8 a , , 1 2 0 a , を形成した。 なお、 クロム膜のエッチングには硝酸第 2セリゥムアンモニゥムを用いた。 このようにしてフォ トダイオード 1 1 8とブロッキングダイオード 1 2 0とを実施例 1 と同じ個数、 構成で、 且つ同じ大きさで形成した。 そ の後、 実施例 1 と同様にして、 層間絶縁膜 9 6、 接続配線 1 0 0、 保護 膜 1 0 4を形成し、 原稿読み取り装置を作製した。 Next, in the same manner as in Example 1, the upper ITO film, the three-layer amorphous silicon film, and the lower ITO film were patterned into a predetermined shape, and the upper electrodes 118 c and 120 c were formed. and the semiconductor layer 1 1 8 b, 1 2 0 b, to form the lower electrode 1 1 8 a, 1 2 0 a is part transparent conductive layer 1 1 8 a 2 of, 1 2 0 a 2. The lower electrode 1 1 8 a, 1 2 0 a is part transparent conductive layer 1 1 8 a 2 of, 1 2 0 a 2, the upper electrode 1 1 8 c, 1 2 0 c and the semiconductor layer 1 1 Using the resist used for patterning 8b and 120b, the underlying ITO film was etched using a mixture of hydrochloric acid and nitric acid. Then, after removing the resist used for patterning, the chromium film is patterned into a predetermined shape by photolithography, and the metal layer 118 a, which is a part of the lower electrodes 118 a and 120 a, is formed. ,, 120 a, are formed. The second chromium ammonium nitrate was used for etching the chromium film. In this way, the photodiodes 118 and the blocking diodes 120 were formed in the same number, configuration, and size as in Example 1. So Thereafter, in the same manner as in Example 1, the interlayer insulating film 96, the connection wiring 100, and the protective film 104 were formed, and a document reading apparatus was manufactured.
次に、 この実施例 2で得られた原稿読み取り装置と、 前述の比較例 1 で得られた原稿読み取り装置に駆動回路と信号処理回路とを接続し、 ク 口ックパルスの周波数を 5 0 0 KH z、 読み取り速度を 5 msec /line として、 白から黒に変化する原稿を 2 0ルクスの照度で照明して読み取 らせた。 この結果、 信号処理回路からは前述の第 1 5図に示すような出 力電圧 Vout が得られた。 このように、 白を読み取った直後の出力電圧 Vout には反転残像 Vr が現れ、 これが白を読み取った直後に読み取つ た黒は通常の黒よりも黒くなる原因となっている。 しかし、 実施例の反 転残像 Vr は比較例の反転残像 Vr よりも小さくなり、 その収束時間も 短くなつた。 その結果をまとめたものを第 1表に示す。 ここでは、 白に 相当する出力電圧 Vout は 1 6 0〜 1 8 O mVであった。 次に、 本発明に係る原稿読み取り装置は、 たとえば上述した実施例で は、 フォ トダイオード 1 1 8を構成する上部電極 1 1 8 cと、 ブロッキ ングダィォ一ド 1 2 0を構成する上部電極 1 2 0 cとが接続配線 1 0 0 によって接続されているが、 第 1 8図に示すように、 フォ トダイオード 1 1 8を構成する下部電極 1 2 2と、 プロッキングダイォード 1 2 0を 構成する下部電極 1 2 2とが共通になっていて、 この下部電極 1 2 2に よってフォ トダイオード 1 1 8とプロッキングダイォ一ド 1 2 0どが接 続されて成る原稿読み取り装置 1 2 4でもよい。 この場合は、 金属層 1 2 6と透明導電層 1 2 8とを順に堆積して下部電極 1 2 2を構成し、 半 導体層 1 1 8 b, 1 2 0 bと透明導電層 1 2 8との界面が形成されるよ うに構成される。 また、 フォ トダイオード 1 1 8の上部電極 1 1 8 cは コンタク トホール 9 8を介して引出配線 1 3 0によって取り出してコン タク トホール 1 0 2を介してチャンネル配線 C ,. C2.... C„ に接続し、 一方、 ブロッキングダイオード 1 2 0の上部電極 1 2 0 cはコンタク ト ホール 9 8を介して引出配線 1 3 2によって外部に取り出すように構成 される。 本例では、 フォ トダイオード 1 1 8とプロッキングダイォード 1 2 0とはアノード電極同士で接続され、 互いに逆極性で直列接続され ていることになる。 Next, a drive circuit and a signal processing circuit were connected to the original reading apparatus obtained in Example 2 and the original reading apparatus obtained in Comparative Example 1 described above, and the frequency of the quick pulse was set to 500 KH. At a scanning speed of 5 msec / line, the original that changed from white to black was illuminated at 20 lux and read. As a result, an output voltage Vout as shown in FIG. 15 was obtained from the signal processing circuit. As described above, the inverted image Vr appears in the output voltage Vout immediately after reading white, and this causes black read immediately after reading white to be blacker than normal black. However, the inversion image Vr of the example was smaller than the inversion image Vr of the comparative example, and the convergence time was shorter. Table 1 summarizes the results. Here, the output voltage Vout corresponding to white was 160 to 18 OmV. Next, for example, in the above-described embodiment, the original reading device according to the present invention includes an upper electrode 118 c constituting the photodiode 118 and an upper electrode 1 constituting the blocking diode 120. 20 c is connected by connection wiring 100, and as shown in FIG. 18, the lower electrode 122 constituting the photodiode 118 and the blocking diode 120 are connected to each other. The lower electrode 1 2 2 is common, and the lower electrode 1 2 2 connects the photodiode 118 and the blocking diode 120 to the original reading device 1. 2 4 is acceptable. In this case, the metal layer 1 26 and the transparent conductive layer 1 28 are sequentially deposited to form the lower electrode 122, and the semiconductor layers 1 18 b and 120 b and the transparent conductive layer 1 2 8 It is configured so that an interface with is formed. In addition, the upper electrode 1 18 c of the photodiode 1 18 is taken out by the lead-out wiring 130 via the contact hole 98 and the channel wiring C,. C 2 ... via the contact hole 102. Connect to C „ On the other hand, the upper electrode 120c of the blocking diode 120 is configured to be taken out to the outside through the contact hole 98 by the lead wiring 132. In this example, the photodiode 118 and the blocking diode 120 are connected by the anode electrodes, and are connected in series with opposite polarities.
なお上述の第 1 7図又は第 1 8図に示す実施例では、 金属層 1 1 8 a 1 , 1 2 0 a , と透明導電層 1 1 8 a 2 , 1 2 0 a 2 とを、 あるいは金 属層 1 2 6と透明導電層 1 2 8とを異なる形状にしているが、 同一形状 にしてもよい。 In the embodiment shown in FIG. 17 or FIG. 18 described above, the metal layer 1 18 a 1, 120 a, and the transparent conductive layer 1 18 a 2 , 120 a 2 , or Although the metal layer 126 and the transparent conductive layer 128 have different shapes, they may have the same shape.
また上述した実施例では、 プロッキングダイォード 1 2 0のアノード 電極又は力ソ一ド電極がプロック Bし B2.... Bm 内で共通に接続され、 フォ トダイオード 1 1 8のァノード電極又は力ソード電極がチヤンネル 配線 d. Cs.... Cn によってブロック Β,. B2.... Bm 間で相対的に 同一位置にあるもの同士で接続されているが、 フォ トダイオードとプロ ッキングダイォードの配置を逆にして、 フォ トダイォ一ドのァノード電 極又は力ソード電極をプロック内で共通に接続し、 プロッキングダイォ —ドのァノ一ド電極又は力ソード電極をチヤンネル配線によってプロッ ク間で相対的に同一位置にあるもの同士で接続したものでもよい。 すな わち、 フォ トダイオード (光電変換素子) とプロッキングダイォード (スィツチング素子) とから構成される光センサ素子が一次元に複数配 列され、 一定個数ごとに複数のブロックに区分されていて、 これら光セ ンサ素子のいずれか一方がプロック内で共通に接続され、 当該他方がチ ャンネル配線によってブロック間で相対的に同一位置にあるもの同士で 共通に接続されていればよいのである。 In the embodiment described above, the anode electrode or Chikarasoichido electrode flop locking die O over de 1 2 0 are connected to a common within to proc B B 2 .... B m, Anodo the photodiode 1 1 8 Although the electrode or force cathode electrode are connected with each other being in the same relative position between the blocks Β ,. B 2 .... B m by channel wiring d. Cs .... C n, the Photo Invert the arrangement of the diode and the blocking diode, connect the anode electrode or the force electrode of the photodiode in the block, and connect the anode electrode or the force electrode of the blocking diode. The electrodes may be connected to each other at relatively the same position between blocks by channel wiring. That is, a plurality of photosensor elements, each composed of a photodiode (photoelectric conversion element) and a blocking diode (switching element), are arranged one-dimensionally, and are divided into a plurality of blocks every fixed number. Therefore, it is only necessary that one of these optical sensor elements is commonly connected in the block and that the other is commonly connected by the channel wiring at the relatively same position between the blocks. .
さらに上述した実施例では、 製造工程の簡素化などの理由から、 フォ トダイオード 1 1 8及びプロッキングダイォード 1 2 0を構成するそれ ぞれの下部 ¾極 1 1 8 a, 1 2 0 a、 半導体層 1 1 8 b, 1 2 O b及び 上部電極 1 1 8 c , 1 2 0 cは、 それぞれ同時に堆積ざれたもので、 そ れぞれ同じ材料から構成されているが、 フォ トダイォ一ド 1 1 8を構成 する上部電極 1 1 8 cは透明でなければならないが、 ブロッキングダイ オード 1 2 0を構成する上部電極 1 2 0 cは透明でなくてもよい。 また、 フォ トダイオード 1 1 8を構成する下部電極 1 1 8 aは、 金属層と透明 導電層とから構成されていなくてもよく、 少なく ともブロッキングダイ ォ一ド (スィツチング素子) 1 2 0を構成する下部電極 1 2 0 a力、 金 属層 1 2 0 a , と透明導電層 1 2 0 a 2 とから構成されていればよい。 すなわち、 本発明は、 スイッチング素子を構成する半導体層に透明導電 層との界面を形成することによってスィッチング素子に生じる逆方向電 流を阻止するようにすればよいのである。 なお、 金属層は 1層でもよい が、 2層以上でもよい。 ― Further, in the above-described embodiment, the lower electrodes 1 18a and 120 a of the photodiodes 118 and the blocking diodes 120 are formed for reasons such as simplification of the manufacturing process. , The semiconductor layers 1 18 b, 12 O b and The upper electrodes 1 18 c and 120 c are respectively deposited simultaneously and are made of the same material, respectively, but the upper electrodes 1 18 c constituting the photodiode 118 are formed. Must be transparent, but the upper electrode 120c constituting the blocking diode 120 may not be transparent. Further, the lower electrode 118a constituting the photodiode 118 does not need to be composed of a metal layer and a transparent conductive layer, and at least a blocking diode (switching element) 120 is required. lower electrode 1 2 0 a power constituting, metallic layer 1 2 0 a, and may be composed of a transparent conductive layer 1 2 0 a 2 Prefecture. That is, in the present invention, a reverse current generated in the switching element may be prevented by forming an interface between the semiconductor layer constituting the switching element and the transparent conductive layer. The number of metal layers may be one, but may be two or more. ―
以上、 本発明に係る半導体装置はいずれも基板 1 2側から主として p i nの順に積層されているが、 これとは逆に n i pの順に積層され、 n i P構造にされていてもよい。 なお、 透明導電層により構成された下部 電極又は上部電極と半導体層の P層とが接して構成されているのが好ま . しい。 また、 上述した p i n型以外に、 n i型、 p i型、 p n型、 M I S型、 ヘテロ接合型、 ホモ接合型、 ショ ッ トキーバリア一型あるいはこ れらを組み合わせた型などに単層又は多層に堆積したものでもよい。 さ らに、 半導体層を構成するアモルファスシリコンとしては、 水素化ァモ ルファスシリコン a-Si :H、 水素化ァモルファスシリコンカ一バイ ド a-Si C :H 、 アモルファスシリコンナイ トライ ドなどの他、 単なるァモルファ スシリコン a-Siなどが好ましいが、 シリコンと炭素、 ゲルマニウム、 ス ズなどの他の元素との合金から成るアモルファスシリコン系半導体の非 晶質あるいは微結晶を堆積したものでもよいなど、 これらの構造は何ら 限定されるものではない。 さらに、 本発明が適用される半導体層は非晶 質又は微結晶に限定されるものではなく、 単結晶であってもよい。 その他、 光電変換素子をフォ トダイォードのような光起電力型の素子 でなく、 たとえば光導電型の素子にしてもよい。 また、 スイッチング素 子を T F Tなどにしてもよいなど、 本発明はその主旨を逸脱しない範囲 内で当業者の知識に基づき種々なる改良、 修正、 変形を加えた態様で実 施し得るものである。 産業上の利用可能性 As described above, all of the semiconductor devices according to the present invention are stacked mainly in the order of pins from the substrate 12 side. On the contrary, the semiconductor devices may be stacked in the order of nip and have a niP structure. It is preferable that the lower electrode or the upper electrode formed of the transparent conductive layer and the P layer of the semiconductor layer are in contact with each other. In addition to the pin type described above, ni-type, pi-type, pn-type, MIS-type, hetero-junction-type, homo-junction-type, Schottky barrier-type, or a combination of these are deposited in a single layer or multilayer. May be done. In addition, amorphous silicon constituting the semiconductor layer includes other materials such as amorphous silicon hydride a-Si: H, amorphous silicon carbide a-SiC: H, and amorphous silicon nitride. However, simple amorphous silicon a-Si is preferred, but amorphous silicon-based semiconductors composed of alloys of silicon and other elements such as carbon, germanium, and tin, or amorphous or microcrystals may be deposited. These structures are not limited at all. Further, the semiconductor layer to which the present invention is applied is not limited to amorphous or microcrystal, but may be a single crystal. In addition, the photoelectric conversion element is not limited to a photovoltaic element such as a photodiode, but may be, for example, a photoconductive element. In addition, the present invention can be implemented in various modified, modified, and modified embodiments based on the knowledge of those skilled in the art without departing from the gist of the present invention, such as a case where the switching element may be a TFT. Industrial applicability
本発明に係るスィツチング機能を有する半導体素子から成る半導体装 置は下部電極及び上部電極のうち少なく ともいずれか一方が透明導電層 で構成されることにより、 半導体層と透明導電層との界面が形成される ため、 逆方向電流はこの界面に形成きれたバリアによって急速に収束さ せられ、 かつ、 そのピーク値も小さくなる。 このため、 スイッチング速 度が大幅に向上させられることになる。 なお、 周辺から漏れてきた光が 下部電極や上部電極を透過して半導体層に入射し、 逆方向電流が急速に 収束させられ、 かつ、 そのピーク値も小さくなるとも考えられる。 次に、 本発明に係る半導体装置である光電変換素子とスィツチング機 能を有する半導体素子とから成る光センサ素子は、 少なく ともスィッチ ング素子を構成する下部電極及び上部電極のうち少なく ともいずれか一 方が透明導電層で構成されることにより、 半導体層と透明導電層との界 面が形成されるため、 逆方向電流はこの界面に形成されたバリアによつ て急速に収束させられ、 かつ、 そのピーク値も小さくなる。 このため、 より正確な信号出力が得られるとともに、 スィツチング速度も向上させ られる。 なお、 周辺から漏れてきた光がスイッチング素子を構成する半 導体層に入射し、 逆方向電流が急速に収束させられ、 かつ、 そのピーク 値も小さくなるとも考えられる。  In the semiconductor device including the semiconductor element having the switching function according to the present invention, at least one of the lower electrode and the upper electrode is formed of the transparent conductive layer, so that the interface between the semiconductor layer and the transparent conductive layer is formed. Therefore, the reverse current is rapidly converged by the barrier formed at this interface, and its peak value is also reduced. Therefore, the switching speed can be greatly improved. It is also considered that light leaked from the periphery penetrates through the lower electrode and the upper electrode and is incident on the semiconductor layer, whereby the reverse current is rapidly converged, and the peak value is also reduced. Next, at least one of the lower electrode and the upper electrode constituting the switching element is a photosensor element comprising the photoelectric conversion element and the semiconductor element having a switching function, which is the semiconductor device according to the present invention. Since the interface is formed of the transparent conductive layer, an interface between the semiconductor layer and the transparent conductive layer is formed, so that the reverse current is rapidly converged by the barrier formed at this interface, and However, its peak value also becomes smaller. Therefore, a more accurate signal output can be obtained, and the switching speed can be improved. It is considered that the light leaked from the periphery enters the semiconductor layer constituting the switching element, the reverse current is rapidly converged, and the peak value is also reduced.
更に、 本発明に係る半導体装置である原稿読み取り装置は、 少なく と もスィツチング素子を構成する下部電極及び上部電極のうち少なく とも いずれか一方が透明導電層で構成されることにより、 半導体層と透明導 電層との界面が形成されるため、 逆方向電流はこの界面に形成されたバ リアによって急速に収束させられ、 かつ、 そのピーク値も小さくなり、 スイッチング素子のスイッチング速度が向上させられる。 このため、 反 転残像は低減させられ、 正確な信号出力を得ることができる。 特に、 低 照度下で原稿を読み取らせる場合に有利で、 消費電力の低減などを図る こともできる。 さらに信号読み出し速度を大幅に速めることも可能であ る。 なお、 周辺から漏れてきた光がスイッチング素子を構成する半導体 層に入射し、 逆方向電流が急速に収束させられ、 かつ、 そのピーク値も 小さくなり、 その結果、 スイッチング素子のスイッチング速度が向上さ せられるとも考えられる。 このように、 本発明は種々の優れた効果を奏 するものである。 Further, the original reading apparatus, which is a semiconductor device according to the present invention, has at least one of a lower electrode and an upper electrode constituting a switching element. Since one of the transparent conductive layers forms an interface between the semiconductor layer and the transparent conductive layer, the reverse current is rapidly converged by the barrier formed at this interface, and The peak value is also reduced, and the switching speed of the switching element is improved. For this reason, inversion inversion is reduced, and an accurate signal output can be obtained. This is particularly advantageous when reading a document under low illuminance, and can reduce power consumption. Further, the signal reading speed can be greatly increased. In addition, light leaked from the periphery enters the semiconductor layer constituting the switching element, and the reverse current is rapidly converged, and the peak value is also reduced. As a result, the switching speed of the switching element is improved. It is thought that it can be done. As described above, the present invention has various excellent effects.

Claims

請 求 の 範 囲 The scope of the claims
1 . 下部電極と、 半導体層と、 上部電極とが順に積層されて構成される スィツチング機能を有する半導体素子を 1又は複数備えた半導体装置に おいて、 1. In a semiconductor device having one or more semiconductor elements having a switching function and configured by sequentially stacking a lower electrode, a semiconductor layer, and an upper electrode,
前記下部電極及び上部電極のうち少なく ともいずれか一方が 1層又は 2層以上の導電層から成り、 且つ少なく とも半導体層と接する導電層が 透明導電層から成ることを特徴とする半導体装置。  A semiconductor device, wherein at least one of the lower electrode and the upper electrode comprises one or more conductive layers, and at least the conductive layer in contact with the semiconductor layer comprises a transparent conductive layer.
2 . 前記請求項 1 に記載のスイッチング機能を有する半導体素子と、 下 部電極と半導体層と上部電極とが順に積層されて成る光電変換素子とが 直列接続されて構成される光センサ素子を 1又は複数備えたことを特徴 とする半導体装置。  2. An optical sensor element configured by serially connecting a semiconductor element having a switching function according to claim 1 and a photoelectric conversion element formed by sequentially stacking a lower electrode, a semiconductor layer, and an upper electrode is referred to as an optical sensor element. Or a semiconductor device including a plurality of the semiconductor devices.
3 . 前記請求項 1に記載のスイッチング機能を有する半導体素子と、 下 部電極と半導体層と上部電極とが順に積層されて成る光電変換素子とが 直列接続されて構成される光センサ素子が一次元に複数配列され、 一定 個数ごとに複数のプロックに区分されているとともに、  3. An optical sensor element configured by serially connecting a semiconductor element having a switching function according to claim 1 and a photoelectric conversion element formed by sequentially stacking a lower electrode, a semiconductor layer, and an upper electrode is a primary element. Originally, it is arranged in plurals, divided into multiple blocks by a certain number,
これら光センサ素子のいずれか一方がプロック内で共通に接続され、 当該他方がチャンネル配線によって該ブロック間で相対的に同一位置に あるもの同士で共通に接続されていることを特徴とする半導体装置。  A semiconductor device, wherein one of these optical sensor elements is commonly connected in a block, and the other is commonly connected by the channel wiring to those at relatively the same position between the blocks. .
4 . 少なく とも前記スイッチング機能を有する半導体素子を 1又は複数 備えた半導体装置において、 該半導体素子の下部電極及び上部電極 う ち少なく ともいずれか一方が透明導電層から成ることを特徴とする請求 項 1乃至請求項 3のいずれかに記載する半導体装置。  4. A semiconductor device provided with at least one or more semiconductor elements having the switching function, wherein at least one of the lower electrode and the upper electrode of the semiconductor element is made of a transparent conductive layer. The semiconductor device according to claim 1.
5 . 少なく とも前記スイッチング機能を有する半導体素子を 1又は複数 備えた半導体装置において、 該半導体素子の透明導電層が I T Oから成 ることを特徴とする請求項 1乃至請求項 4のいずれかに記載の半導体装 5. A semiconductor device comprising at least one semiconductor element having the switching function, wherein the transparent conductive layer of the semiconductor element is made of ITO. Semiconductor equipment
6 . 少なく とも前記スイッチング機能を有する半導体素子を 1又は複数 備えた半導体装置において、 該半導体素子の半導体層のうち、 少なく と も該透明導電層と接する半導体層が P型半導体層であることを特徴とす る請求項 1乃至請求項 5のいずれかに記載の半導体装置。 6. In a semiconductor device provided with at least one or more semiconductor elements having the switching function, it is preferable that at least a semiconductor layer in contact with the transparent conductive layer among the semiconductor layers of the semiconductor element is a P-type semiconductor layer. 6. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
7 . 少なく とも前記スイッチング機能を有する半導体素子を 1又は複数 備えた半導体装置において、 該半導体素子の半導体層はプラズマ C V D 法で連続的に堆積された水素化アモルファスシリコンから成り、 且つ p i n構造にされていることを特徴とする請求項 1乃至請求項 6のいずれ かに記載の半導体装置。  7. In a semiconductor device provided with at least one or more semiconductor elements having the switching function, a semiconductor layer of the semiconductor element is made of hydrogenated amorphous silicon continuously deposited by a plasma CVD method, and has a pin structure. 7. The semiconductor device according to claim 1, wherein:
8 . 前記スィツチング機能を有する半導体素子と前記光電変換素子とは それぞれダイォード特性を備え、 互いのカソード電極で直列接続されて いることを特徴とする請求項 2乃至請求項 7のいずれかに記載の半導体  8. The semiconductor device according to any one of claims 2 to 7, wherein the semiconductor element having the switching function and the photoelectric conversion element each have a diode characteristic and are connected in series by their respective cathode electrodes. Semiconductor
9 . 前記スィツチング機能を有する半導体素子及び前記光電変換素子を 構成するそれぞれの下部電極、 半導体層及び上部電極は、 それぞれ同時 に堆積されたものであることを特徴とする請求項 2乃至請求項 8のいず れかに記載の半導体装置。 9. The semiconductor device having the switching function and the lower electrode, the semiconductor layer, and the upper electrode constituting the photoelectric conversion device are respectively deposited simultaneously. The semiconductor device according to any one of the above.
1 0 . 前記スイッチング機能を有する半導体素子及び前記光電変換素子 とが直列接続されて構成される光センサ素子を 1又は複数備えた半導体 装置において、 光入射側とは反対側に位置する下部電極及び上部電極の いずれか一方が、 少なく とも半導体層と接して透明導電層により構成さ れていることを特徴とする請求項 2乃至請求項 9のいずれかに記載の半 導体装置。  10. In a semiconductor device provided with one or a plurality of optical sensor elements configured by serially connecting the semiconductor element having the switching function and the photoelectric conversion element, a lower electrode positioned on the side opposite to the light incident side; 10. The semiconductor device according to claim 2, wherein one of the upper electrodes is formed of a transparent conductive layer at least in contact with the semiconductor layer.
PCT/JP1993/000794 1992-06-15 1993-06-14 Semiconductor device WO1993026046A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP19930913518 EP0601200A4 (en) 1992-06-15 1993-06-14 Semiconductor device.

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
JP4181852A JPH05347398A (en) 1992-06-15 1992-06-15 Original reader
JP4/181852 1992-06-15
JP4188718A JPH066514A (en) 1992-06-22 1992-06-22 Switching element
JP4/188718 1992-06-22
JP4/197623 1992-06-30
JP4197622A JPH0621425A (en) 1992-06-30 1992-06-30 Manuscript reader
JP4197624A JPH0621484A (en) 1992-06-30 1992-06-30 Switching device
JP4/197622 1992-06-30
JP4197621A JPH0621424A (en) 1992-06-30 1992-06-30 Photosensor element
JP4197623A JPH0621426A (en) 1992-06-30 1992-06-30 Photosensor element
JP4/197624 1992-06-30
JP4/197621 1992-06-30

Publications (1)

Publication Number Publication Date
WO1993026046A1 true WO1993026046A1 (en) 1993-12-23

Family

ID=27553525

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1993/000794 WO1993026046A1 (en) 1992-06-15 1993-06-14 Semiconductor device

Country Status (1)

Country Link
WO (1) WO1993026046A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61203668A (en) * 1985-03-06 1986-09-09 Fujitsu Ltd Image sensor
JPS6260275A (en) * 1985-09-10 1987-03-16 Matsushita Electric Ind Co Ltd Manufacture of element for photoelectric conversion
JPS6259469B2 (en) * 1979-09-26 1987-12-11 Ricoh Kk
JPS6386973A (en) * 1986-09-16 1988-04-18 オボニツク・イメージング・システムズ・インコーポレイテツド Light sensitive pickcell with exposure blocking device
JPH03265171A (en) * 1990-03-14 1991-11-26 Nippon Steel Corp Image sensor and photoelectric conversion device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6259469B2 (en) * 1979-09-26 1987-12-11 Ricoh Kk
JPS61203668A (en) * 1985-03-06 1986-09-09 Fujitsu Ltd Image sensor
JPS6260275A (en) * 1985-09-10 1987-03-16 Matsushita Electric Ind Co Ltd Manufacture of element for photoelectric conversion
JPS6386973A (en) * 1986-09-16 1988-04-18 オボニツク・イメージング・システムズ・インコーポレイテツド Light sensitive pickcell with exposure blocking device
JPH03265171A (en) * 1990-03-14 1991-11-26 Nippon Steel Corp Image sensor and photoelectric conversion device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0601200A4 *

Similar Documents

Publication Publication Date Title
JPH0481353B2 (en)
US20080128697A1 (en) Tfa image sensor with stability-optimized photodiode
US20060223214A1 (en) Optoelectronic component for converting electromagnetic radiation into a intensity-dependent photocurrent
US5130259A (en) Infrared staring imaging array and method of manufacture
JPH04154165A (en) Semiconductor device
JPH023552B2 (en)
JPH0217992B2 (en)
JPH07192663A (en) Image pickup device
WO1993026046A1 (en) Semiconductor device
JPH04154168A (en) Manufacture of image sensor
EP0601200A1 (en) Semiconductor device
JPH04153623A (en) Wiring structure
JPH07335935A (en) Manufacture of optoelectric transducer
JPH0621425A (en) Manuscript reader
JPS6213066A (en) Photoelectric converter
JPH05347398A (en) Original reader
JPH06283699A (en) Original reader
JPH06260678A (en) Reader and manufacture thereof
JPH06283698A (en) Original reader
JP3398161B2 (en) Photoelectric conversion device
JPH0214790B2 (en)
JPH02166769A (en) Laminated solid state image sensor and manufacture thereof
JPH0621426A (en) Photosensor element
JPH0621484A (en) Switching device
JPH0621424A (en) Photosensor element

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): DE FR GB IT NL

ENP Entry into the national phase

Ref country code: US

Ref document number: 1994 193003

Date of ref document: 19940215

Kind code of ref document: A

Format of ref document f/p: F

WWE Wipo information: entry into national phase

Ref document number: 1993913518

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWP Wipo information: published in national office

Ref document number: 1993913518

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1993913518

Country of ref document: EP