WO1993020587A1 - Mos structure for reducing snapback - Google Patents

Mos structure for reducing snapback Download PDF

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Publication number
WO1993020587A1
WO1993020587A1 PCT/US1993/003129 US9303129W WO9320587A1 WO 1993020587 A1 WO1993020587 A1 WO 1993020587A1 US 9303129 W US9303129 W US 9303129W WO 9320587 A1 WO9320587 A1 WO 9320587A1
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WO
WIPO (PCT)
Prior art keywords
substrate
channel
conductivity type
layer
dielectric material
Prior art date
Application number
PCT/US1993/003129
Other languages
French (fr)
Inventor
Michael S. Liu
Original Assignee
Honeywell Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc. filed Critical Honeywell Inc.
Publication of WO1993020587A1 publication Critical patent/WO1993020587A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect

Definitions

  • the invention relates generally to semiconductor devices and more particularly to a structure for reducing, snapback in n-channel metal oxide semiconductor (MOS) devices.
  • MOS metal oxide semiconductor
  • N-channel MOSFETS that are fabricated in silicon-on- insulator (SOI) substrates exhibit a characteristic called kink effect that can be explained as follows.
  • SOI NMOS usually has no substrate contact.
  • the holes will be driven by the resultant electric field of the drain and gate toward the bottom Si0 2 /Si interface near the source region to form stationary charge cloud to raise the potential of the floating SOI body leading to the kink current.
  • SOI devices become thinner and gate lengths become shorter an effect called snapback can occur in N-channel MOS devices.
  • FIGS. 1 and 2 show an NMOS transistor 12 formed in silicon layer 1 . Buried oxide layer 16 isolates the transistor 12 from substrate 18. Transistor 12 includes source 20, gate 22 and drain 24. In this approach the holes created by impact ionization in channel 25 near drain 24 travel for example along paths 26 to reach P+ region 28.
  • the snapback phenomenon is related to the resistance of paths 26 with the likelihood of snapback increasing with increased resistance. The resistance of the paths 26 is dependent on the length of paths 26. In practice, the most resistive path is the width of the device since the outer region is doped move heavily than the channel region.
  • a scaled down NMOS transistor may have a gate length of 1 micron and the width of the NMOS could easily be 10 to over 100 microns, the longer, the worse.
  • Figs. 1 and 2 also show gate oxide 32, field oxide 34 and trenches 30.
  • the snapback problem could be reduced by reducing the power supply voltages to the transistors. However in many applications it is not feasible to reduce power supply • voltages.
  • the present invention solves these and other needs by providing an effective SOI NMOS semiconductor structure which has a substrate with a lower portion of p+ conductivity and a buried oxide layer having an opening with lower p conductivity below the channel region.
  • holes resulting from impact ionization in the channel near the drain edge are removed by way of a low resistance path from the channel through the opening to the p+ portion.
  • Fig. 1 is a plan view of a prior art device.
  • Fig. 2 is a sectional view of the device of Fig. 1 along section line 22.
  • Figs. 3.4 and 5 are enlarged cross-section drawings in accordance with the present invention.
  • the starting material may be a p/p+ (p on p+) wafer shown as substrate 42.
  • the first step is to grow a thick oxide (approximately 6000A) on substrate 42 to serve as a mask oxide for the oxygen implantation process.
  • the masking oxide 44 will appear as shown in Fig. 3 with masking oxide 44 covering what will be channel region 46 of the NMOS device.
  • the next step is the oxygen implantation 45 of substrate 42 as illustrated in Fig. 3.
  • Oxygen implantation can be done with a dose level preferably in the range of 1.5 x 10 18 ions/ cm-2 to 2.0 x 10 18 ions/cm-2.
  • the implantation energy is preferably in the range of 150 KeV to 200 KeV.
  • the oxygen implant process can be planned to result in a silicon layer of the desired thickness for construction of the NMOS device. In practice, expitaxial layer is added to the desired thickness or the silicon layer is reduced by oxidation to the desired thickness.
  • a buried oxide layer 48 having an upper surface 49 as illustrated in Fig. 4 has been formed.
  • the thickness of silicon layer 14 may be in the range of 2300 to 3300 angstroms and the thickness of buried oxide layer 49 may be approximately 4000 angstroms after a high temperature annealing process.
  • the annealing process is to form the buried oxide layer and to eliminate many of the defects created during the oxygen implantation.
  • the normal NMOS processes associated with forming gate oxide 50, forming polysilicon gate 52, and implanting source 54 and drain 56 may be performed according to well known methods.
  • NMOS device 40 having a structure for reducing snapback according to the present invention
  • impact ionization may occur in channel region 46 near drain 56 and electron-hole pairs will be produced. When this occurs the electrons will be accelerated toward the drain, but the unwanted holes need to be removed from the channel region.
  • Applicant's invention makes a tie with the p+ substrate from the bottom of channel 46 through opening 58 where hole current may be drained to ground at electrode or terminal 60. This greatly reduces the path length 47 to the short length from the bottom of channel 46 into the lower p+ portion of substrate 42.
  • the oxygen implantation process for SOI creates many defects in the implanted silicon.
  • the oxygen implanted regions will later be doped to provide source 54 and drain 56 regions.
  • the defects will not be a problem in the heavily doped source 54 and drain 56.
  • channel region 46 will have been protected from the oxygen implanting by masking oxide 44. Therefore, channel region 46 will be relatively defect free which will result in improved performance.

Abstract

A structure for reducing the snapback effect in a n-channel MOS transistor. An SOI structure is produced by ion implantation of a p on p+ substrate. An oxyde mask prevents ion implantation in a channel region and results in an opening in the buried oxide directly below the channel region. In operation holes produced by impact ionization in the channel are drained away from the channel through the opening in the buried oxide.

Description

MOS STRUCTURE FOR REDUCING SNAPBACK
BACKGROUND OF THE INVENTION The invention relates generally to semiconductor devices and more particularly to a structure for reducing, snapback in n-channel metal oxide semiconductor (MOS) devices.
N-channel MOSFETS that are fabricated in silicon-on- insulator (SOI) substrates exhibit a characteristic called kink effect that can be explained as follows. The SOI NMOS usually has no substrate contact. At high drain bias in NMOS operation, as the electrons accelerate from source to drain the electron-hole pairs will be generated near the drain region due to impact ionization. The electrons will be collected by the drain, but the holes will be driven by the resultant electric field of the drain and gate toward the bottom Si02/Si interface near the source region to form stationary charge cloud to raise the potential of the floating SOI body leading to the kink current. As SOI devices become thinner and gate lengths become shorter an effect called snapback can occur in N-channel MOS devices. Assume for illustration purposes a drain to source voltage of approximately 6 volts or higher. In normal operation the drain current increases with increasing gate voltage and decreases with decreasing gate voltage. When snapback occurs, the drain current does not decrease when the gate voltage is decreased, but rather stays at the value it was with a higher gate voltage. Snapback represents a more serious problem than kink effect.
When snapback occurs it is apparently as a result of holes produced from impact ionization in the vicinity of the drain edge. The accumulating holes can have the effect of positively charging the bottom insulating layer. As more holes accumulate to cause the source barrier lowering so that electrons begin to inject into the active body region, the source-body junction becomes forward biased. This in turn turns on the parasitic bipolar transfer and leads to snapback-
In the past the solution to reducing snapback has been to use a designated portion of the SOI to collect the hole current. This approach is illustrated in FIGS. 1 and 2 . which show an NMOS transistor 12 formed in silicon layer 1 . Buried oxide layer 16 isolates the transistor 12 from substrate 18. Transistor 12 includes source 20, gate 22 and drain 24. In this approach the holes created by impact ionization in channel 25 near drain 24 travel for example along paths 26 to reach P+ region 28. The snapback phenomenon is related to the resistance of paths 26 with the likelihood of snapback increasing with increased resistance. The resistance of the paths 26 is dependent on the length of paths 26. In practice, the most resistive path is the width of the device since the outer region is doped move heavily than the channel region. For example a scaled down NMOS transistor may have a gate length of 1 micron and the width of the NMOS could easily be 10 to over 100 microns, the longer, the worse. Figs. 1 and 2 also show gate oxide 32, field oxide 34 and trenches 30.
The snapback problem could be reduced by reducing the power supply voltages to the transistors. However in many applications it is not feasible to reduce power supply • voltages.
In applications directed toward reducing single event upset (SEU) it is necessary to use a small volume of silicon which favors using a thin layer of SOI. The thin SOI layer reduces the effectiveness of the approach of Figs. 1 and 2 in reducing snapback. Thus a need exists for effectively reducing snapback in n-channel MOS transistors.
SUMMARY OF THE INVENTION The present invention solves these and other needs by providing an effective SOI NMOS semiconductor structure which has a substrate with a lower portion of p+ conductivity and a buried oxide layer having an opening with lower p conductivity below the channel region. In operation, holes resulting from impact ionization in the channel near the drain edge are removed by way of a low resistance path from the channel through the opening to the p+ portion.
BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view of a prior art device. Fig. 2 is a sectional view of the device of Fig. 1 along section line 22. Figs. 3.4 and 5 are enlarged cross-section drawings in accordance with the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT The starting material may be a p/p+ (p on p+) wafer shown as substrate 42. In accordance with the present invention , the first step is to grow a thick oxide (approximately 6000A) on substrate 42 to serve as a mask oxide for the oxygen implantation process. After the mask oxide has been grown and masked and the unmasked portions etched and removed, all according to known processes, the masking oxide 44 will appear as shown in Fig. 3 with masking oxide 44 covering what will be channel region 46 of the NMOS device.
The next step is the oxygen implantation 45 of substrate 42 as illustrated in Fig. 3. Oxygen implantation can be done with a dose level preferably in the range of 1.5 x 1018 ions/ cm-2 to 2.0 x 1018 ions/cm-2. The implantation energy is preferably in the range of 150 KeV to 200 KeV. The oxygen implant process can be planned to result in a silicon layer of the desired thickness for construction of the NMOS device. In practice, expitaxial layer is added to the desired thickness or the silicon layer is reduced by oxidation to the desired thickness.
Following the oxygen implantation a buried oxide layer 48 having an upper surface 49 as illustrated in Fig. 4 has been formed. By way of example, but not by way of limitation, the thickness of silicon layer 14 may be in the range of 2300 to 3300 angstroms and the thickness of buried oxide layer 49 may be approximately 4000 angstroms after a high temperature annealing process. The annealing process is to form the buried oxide layer and to eliminate many of the defects created during the oxygen implantation. Following the annealing the normal NMOS processes associated with forming gate oxide 50, forming polysilicon gate 52, and implanting source 54 and drain 56 may be performed according to well known methods.
Now that the construction of NMOS device 40 having a structure for reducing snapback according to the present invention has been disclosed, the operation and advantages can be set forth and appreciated. In operation, impact ionization may occur in channel region 46 near drain 56 and electron-hole pairs will be produced. When this occurs the electrons will be accelerated toward the drain, but the unwanted holes need to be removed from the channel region. Unlike the past solution of causing the holes to follow a winding and high electrical resistance path 26 through the side of the gate field structure as shown in Figs. 1 and 2, Applicant's invention makes a tie with the p+ substrate from the bottom of channel 46 through opening 58 where hole current may be drained to ground at electrode or terminal 60. This greatly reduces the path length 47 to the short length from the bottom of channel 46 into the lower p+ portion of substrate 42.
The oxygen implantation process for SOI creates many defects in the implanted silicon. In Applicant's invention the oxygen implanted regions will later be doped to provide source 54 and drain 56 regions. The defects will not be a problem in the heavily doped source 54 and drain 56.
Furthermore, channel region 46 will have been protected from the oxygen implanting by masking oxide 44. Therefore, channel region 46 will be relatively defect free which will result in improved performance. In accordance with the foregoing description,
Applicants have developed a structure for reducing snapback that may be incorporated into the design of n-channel NMOS transistors. Although a specific embodiment of Applicant' s invention is shown and described for illustrative purposes, a number of variations and modifications will be apparent to those skilled in the art. It is not intended that coverage be limited to the disclosed embodiment, but only by the terms of the following claims.

Claims

CLAIMS The embodiments of an invention in which an exclusive property or right is claimed are defined as follows: 1. An n-channel MOS device comprising: a substrate of a semiconductor material having .a lower portion of a first conductivity type; a layer of a dielectric material over the lower, portion of said substrate, said dielectric material having an upper surface; an island of a semiconductor material of a first conductivity type over a portion of said dielectric layer with a channel region in said island and with spaced first and second regions of a second conductivity type in said island forming the source and drain regions respectively of said device; and means for preventing a positive charge buildup at said upper surface of said layer of dielectric material.
2. The device of claim 1 wherein said means for preventing a positive charge buildup comprises; means for providing a low resistance path from said channel to said lower portion of said semiconductor substrate of a first conductivity type; and an electrode of a conducting material electrically connected to said lower portion of said lower substrate.
3. The device of claim 2 wherein said means for providing a low resistance path from said channel to said lower portion of said semiconductor substrate comprises: an opening extending through said layer of dielectric material to provide a direct path to said lower portion of said substrate for holes generated by impact ionization near said drain end of said channel, said opening substantially defined by vertical projection of said channel region.
4. The device of claim 3 wherein said dielectric material -is silicon dioxide.
5. An n-channel MOS device comprising: a substrate of a semiconductor material having a lower portion of a first conductivity type; a layer of a dielectric material over the lower, portion of said substrate, said dielectric material having an upper surface and having an opening there - through; an- island nf a semiconductor material of a first conductivity type over a portion of said dielectric layer with a channel region in said island substantially defined by a vertical projection of said opening in said dielectric material and with spaced regions of a second conductivity type in said island forming the source and drain regions of said device; an electrode of a conducting material electrically connected to said substrate and providing a direct path for draining any positive charge generated by impact ionization.
6. A method for fabricating an n-channel MOS device comprising the following steps; providing a semiconductor substrate of a first conductivity type; growing an oxide mask on said semiconductor substrate to substantially define a channel region in said semiconductor substrate; implanting oxygen ions into said semiconductor substrate to form a buried oxide layer, except in said channel region, said buried oxide layer having a second semiconductor substrate thereon; annealing said device; and forming source and drain regions in said second semiconductor substrate using normal n-channel MOS processes.
7. The method of claim 5 wherein said step of implanting oxygen ions is performed at a dose level of 1.5 x 1018 to 2.0 x 1018 cm-2 and an energy level of 150 Kev to 200 KeV.
PCT/US1993/003129 1992-03-30 1993-03-30 Mos structure for reducing snapback WO1993020587A1 (en)

Applications Claiming Priority (2)

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US86039992A 1992-03-30 1992-03-30
US07/860,399 1992-03-30

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6461902B1 (en) * 2000-07-18 2002-10-08 Institute Of Microelectronics RF LDMOS on partial SOI substrate
US6528853B2 (en) * 2000-01-05 2003-03-04 International Business Machines Corporation Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors
CN107634101A (en) * 2017-09-21 2018-01-26 中国工程物理研究院电子工程研究所 Semiconductor field effect transistor and its manufacture method with three-stage oxygen buried layer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0042552A2 (en) * 1980-06-16 1981-12-30 Kabushiki Kaisha Toshiba MOS type semiconductor device
US4523213A (en) * 1979-05-08 1985-06-11 Vlsi Technology Research Association MOS Semiconductor device and method of manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4523213A (en) * 1979-05-08 1985-06-11 Vlsi Technology Research Association MOS Semiconductor device and method of manufacturing the same
EP0042552A2 (en) * 1980-06-16 1981-12-30 Kabushiki Kaisha Toshiba MOS type semiconductor device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 013, no. 483 (E-839)2 November 1989 *
PATENT ABSTRACTS OF JAPAN vol. 015, no. 200 (E-1070)22 May 1991 *
PATENT ABSTRACTS OF JAPAN vol. 12, no. 423 (E-680)(3270) 9 November 1988 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6528853B2 (en) * 2000-01-05 2003-03-04 International Business Machines Corporation Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors
US6461902B1 (en) * 2000-07-18 2002-10-08 Institute Of Microelectronics RF LDMOS on partial SOI substrate
CN107634101A (en) * 2017-09-21 2018-01-26 中国工程物理研究院电子工程研究所 Semiconductor field effect transistor and its manufacture method with three-stage oxygen buried layer

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