WO1993011563A1 - Dispositif semi-conducteur avec un systeme de couches metalliques et procede pour sa fabrication - Google Patents

Dispositif semi-conducteur avec un systeme de couches metalliques et procede pour sa fabrication Download PDF

Info

Publication number
WO1993011563A1
WO1993011563A1 PCT/DE1992/000995 DE9200995W WO9311563A1 WO 1993011563 A1 WO1993011563 A1 WO 1993011563A1 DE 9200995 W DE9200995 W DE 9200995W WO 9311563 A1 WO9311563 A1 WO 9311563A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor arrangement
nickel
substrate
thickness
Prior art date
Application number
PCT/DE1992/000995
Other languages
German (de)
English (en)
Inventor
Ernst Scherrer
Helmut Skapa
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO1993011563A1 publication Critical patent/WO1993011563A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors

Definitions

  • the invention relates to a semiconductor arrangement with a substrate, on the surface of which a solderable metal layer system is arranged, which has nickel.
  • the power density is increasing more and more due to progressive integration technology. This increases the requirements for good heat dissipation.
  • One way of effectively dissipating the heat generated during the operation of these components is to apply a coating to the substrate which consists of a good heat conductor, preferably made of metal. It is known to design this coating as a metal layer system, which means that there are several layers made of different metals intended.
  • the outer layer is designed as a solderable layer. It is suitable for electrical solder contacting.
  • power semiconductors for example, in addition to the function of heat dissipation, it also takes over the function for electrical contacting.
  • solderable metal layer system it is known to apply a solderable metal layer system to silicon substrates which has two nickel layers and a gold layer as the outer layer. It is applied using electroless plating.
  • US Pat. No. 3,922,385 discloses a semiconductor arrangement with a metal layer system applied by the sputtering process, which has an inner layer made of nickel / magnesium and an outer layer made of a solderable metal, for example nickel, silver or gold, having.
  • a metal layer system applied by the sputtering process, which has an inner layer made of nickel / magnesium and an outer layer made of a solderable metal, for example nickel, silver or gold, having.
  • Various methods, including the sputter method are known for applying the metal layer system.
  • Electroless plating and vapor deposition technology have the disadvantage that, at least after the first nickel layer has been applied, a tempering process is required to produce a mechanically stable and electrically perfect contact. In addition, there is a risk of nickel splashes in the evaporation process, which leads to a loss in yield.
  • the temperature change resistance of the solder layer and the void density can also be improved in the known metal layer systems.
  • the semiconductor arrangement according to the invention with the features mentioned in the main claim has the advantage over the fact that no tempering process is required, so that the production is simplified.
  • the chrome layer acts as a good adhesion promoter, so that the subsequent nickel layer is mechanically strong and electrically optimally connected to the substrate.
  • the outer layer of precious metal seals the nickel layer, which is applied oxide-free due to the sputtering process, which creates the best conditions for solderability. This is due, among other things, to the very low void density and also to the high temperature fatigue strength of the solder layer.
  • the inventive selection of the materials of the individual layers of the metal layer system and their respective application by means of the sputtering process result in optimal layer adhesion and lead to a negligible incorporation of residual gas, which leads to particularly low contact and layer resistances. This is particularly noticeable, for example, in the case of power diodes due to low forward voltages. With the sputtering process, there is no risk of nickel splashes, as is the case with the known application processes. The choice of the materials mentioned gives a cost-effective coating.
  • the metal layer system according to the invention consists of a first layer which has chromium (this Formulation means that besides chromium there may also be other material / materials) or consists of chromium.
  • This first layer is. applied to the surface of the substrate by sputtering.
  • a second layer, applied to the first layer by sputtering, has nickel or consists of nickel.
  • a third layer is arranged on it, which is also produced in the sputtering process. It consists of precious metal, particularly preferably of silver, or has silver.
  • the second layer also contains vanadium in addition to nickel.
  • the second layer is preferably 7% by weight vanadium.
  • the first layer preferably has a minimum thickness of 70 nm. A thickness of at least 250 nm is preferred for the second layer.
  • the third layer has in particular a thickness of at least 100 nm.
  • the invention further relates to a method for applying a solderable.
  • Metal layer system on the surface of a substrate of a semiconductor arrangement by sputtering the individual layers, a first layer consisting of chromium or having chromium being applied to the substrate first, then a second layer is applied to the first layer, which consists of Nickel consists or has nickel and then a third layer is applied to the second layer, which consists of noble metal or has noble metal, preferably consists of silver or has silver.
  • the sputter coating is preferably carried out with Ar ⁇ gon-ions, in particular at a pressure of approximately 5 '10 "2 mbar.
  • the sputtering process can be carried out at a sputtering rate of approximately 500 nm / min.
  • FIG. 1 shows a cross section through a section of a substrate of a semiconductor arrangement with a first applied layer of a metal layer system.
  • FIG. 2 shows the representation according to FIG. 1 after carrying out a further process step by which a second layer was applied
  • FIG. 3 shows the arrangement according to FIG. 2 after application of a third layer
  • FIG. 4 shows a cross section through a semiconductor arrangement which has the metal layer system on both sides. Description of an embodiment
  • FIG. 1 shows a semiconductor arrangement 1 which has a substrate 2. Only a section of the substrate 2 is shown in FIG. 1.
  • This substrate 2 can be, for example, a silicon substrate. This can be provided with p-doping or else with n-doping.
  • the semiconductor arrangement 1 can be part of an integrated circuit or a power semiconductor or another electronic component.
  • a second layer 5 is applied to this first layer 4 (FIG. 2), which essentially consists of nickel (Ni), preferably additionally a certain proportion of vanadium (V), in particular at least 7% by weight of vanadium ( V).
  • the three layers 4, 5 and 6 form a solderable metal layer system 7, which on the one hand serves to dissipate heat during operation of the semiconductor arrangement and represents an electrical contact to the substrate (Si) and on the other hand also provides a solder contact.
  • the individual layers 4, 5, 6 are applied sequentially by sputtering. The individual manufacturing steps are shown in Figures 1 to 3. It is clearly evident that the first layer 4 is first applied to the substrate 2 by means of sputtering and that the second layer 5 is then applied thereon — also by means of the sputtering method. Finally, the third layer 6 is then applied to the second layer 5, also by sputtering.
  • the coating of the substrate with the metal layer system 7 takes place only on one side, one speaks of a so-called backside coating of the semiconductor arrangement.
  • both the top and the bottom or all sides of a semiconductor arrangement it is of course also possible for both the top and the bottom or all sides of a semiconductor arrangement to be provided with the metal layer system.
  • the interrupted substrate 2 has the metal layer system 7 described above on both the top side -8 and the bottom side 9.
  • the second layer 5 preferably consists not only of nickel (Ni) but also has vanadium (V) in addition to the nickel (Ni).
  • the vanadium content is preferably at least 7 percent by weight.
  • the sputtering process preferably takes place by means of argon ions (Ar ions) at approximately 5 10 -2 mbar and at a residual gas partial pressure of 1 * 10 -7 mbar (0 2 , H2 ⁇ ).
  • the good layer homogeneity that can be achieved according to the invention (+ 3% over the diameter of a 4-inch wafer) allows the production of very thin layers. It is preferably provided that the first layer has a thickness of at least 70 nm and the second layer 5 has at least a thickness of 250 nm and the third layer 6 has at least a thickness of 100 nm.
  • the nickel target loses its magnetic properties.
  • the material utilization of the nickel target increases from approx. 12 percent by weight to approx. 40 percent by weight.
  • sputtering rates comparable to those of chrome or silver of approximately 600 nm / min are achieved with the nickel source in magnetron sputtering.
  • Commercial sputtering systems with loading lock can be used to carry out the coating process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physical Vapour Deposition (AREA)
  • Die Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un dispositif semi-conducteur avec un substrat sur la surface duquel est disposé un système de couches métalliques soudable comportant du nickel. Il est prévu qu'une première couche (4) du système de couches métalliques (7) comporte du chrome (Cr), qu'une deuxième couche (5) comporte du nickel (Ni) et qu'une troisième couche (6) comporte un métal noble, en particulier l'argent (Ag).
PCT/DE1992/000995 1991-12-04 1992-11-28 Dispositif semi-conducteur avec un systeme de couches metalliques et procede pour sa fabrication WO1993011563A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19914139908 DE4139908A1 (de) 1991-12-04 1991-12-04 Halbleiteranordnung mit metallschichtsystem sowie verfahren zur herstellung
DEP4139908.0 1991-12-04

Publications (1)

Publication Number Publication Date
WO1993011563A1 true WO1993011563A1 (fr) 1993-06-10

Family

ID=6446209

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1992/000995 WO1993011563A1 (fr) 1991-12-04 1992-11-28 Dispositif semi-conducteur avec un systeme de couches metalliques et procede pour sa fabrication

Country Status (2)

Country Link
DE (1) DE4139908A1 (fr)
WO (1) WO1993011563A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0823731A2 (fr) * 1996-08-05 1998-02-11 Motorola, Inc. Méthode de fabrication d'un système de métallisation pour semi-conducteur et sa structure
EP2287899B1 (fr) * 2009-08-18 2014-05-07 SEMIKRON Elektronik GmbH & Co. KG Connexion par soudage avec une couche soudable à plusieurs couches et procédé de fabrication correspondant

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007048299A1 (de) * 2007-10-08 2009-04-09 Behr Gmbh & Co. Kg Mehrschichtlot

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2081661A1 (fr) * 1970-03-03 1971-12-10 Licentia Gmbh
EP0463362A2 (fr) * 1990-06-28 1992-01-02 Nippondenso Co., Ltd. Dispositif comprenant des couches métalliques

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2081661A1 (fr) * 1970-03-03 1971-12-10 Licentia Gmbh
EP0463362A2 (fr) * 1990-06-28 1992-01-02 Nippondenso Co., Ltd. Dispositif comprenant des couches métalliques

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 4, no. 152 (E-31)24. Oktober 1980 *
PATENT ABSTRACTS OF JAPAN vol. 5, no. 113 (E-66)22. Juli 1981 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0823731A2 (fr) * 1996-08-05 1998-02-11 Motorola, Inc. Méthode de fabrication d'un système de métallisation pour semi-conducteur et sa structure
EP0823731A3 (fr) * 1996-08-05 1999-11-03 Motorola, Inc. Méthode de fabrication d'un système de métallisation pour semi-conducteur et sa structure
US6140703A (en) * 1996-08-05 2000-10-31 Motorola, Inc. Semiconductor metallization structure
EP2287899B1 (fr) * 2009-08-18 2014-05-07 SEMIKRON Elektronik GmbH & Co. KG Connexion par soudage avec une couche soudable à plusieurs couches et procédé de fabrication correspondant

Also Published As

Publication number Publication date
DE4139908A1 (de) 1993-06-09

Similar Documents

Publication Publication Date Title
DE2440481C3 (de) Verfahren zum Herstellen von Dünnschicht-Leiterzügen auf einem elektrisch isolierenden Träger
DE3632209C2 (fr)
DE68918773T2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung mit mindestens einer kleine Kontaktlöcher enthaltenden Leiterbahn.
DE2729030C2 (de) Verfahren zum Herstellen eines mehrschichtigen Leiterzugsmusters für monolithisch integrierte Halbleiterschaltungen
DE4292563C1 (de) Verfahren zur Metallisierung von Substraten unter Verwendung einer Verarmungsreaktions-Metalloxid-Reduzierung
DE3340563C2 (de) Schichtkondensator und Verfahren zur Herstellung desselben
DE69531980T2 (de) Metallisierung von keramischen Materialien durch Auftrag einer haftenden reduzierbaren Schicht
DE2810054A1 (de) Elektronische schaltungsvorrichtung und verfahren zu deren herstellung
DE19626977A1 (de) Dünnfilmvielschichtverdrahtungsplatte und deren Herstellung
DE3347489C2 (fr)
EP0002703B1 (fr) Méthode de production de conducteurs à bande mince sur substrats semi-conducteurs et conducteurs produits par cette méthode
DE102008051921A1 (de) Mehrschichtsystem mit Kontaktelementen und Verfahren zum Erstellen eines Kontaktelements für ein Mehrschichtsystem
DE3033513C2 (de) Verfahren zur Herstellung einer aluminiumhaltigen Leiterschicht
DE2719988C2 (de) Amorphe, Tantal enthaltende mindestens bis 300 Grad C temperaturstabile Metallschicht und Verfahren zu ihrer Herstellung
DE2509912B2 (de) Elektronische Dünnfilmschaltung
DE3638799C2 (fr)
DD201627A5 (de) Verfahren zum bilden elektrisch leitender durchdringungen in duennfilmen
WO1993011563A1 (fr) Dispositif semi-conducteur avec un systeme de couches metalliques et procede pour sa fabrication
DE3636366C2 (fr)
DE2134291A1 (de) Halbleitervorrichtung
DE3018510C2 (de) Josephson-Übergangselement
DE2534414A1 (de) Magneto-widerstand und verfahren zu dessen herstellung
EP1111694A2 (fr) Dispositif à couche mince avec un condensateur ajustable
DE1764937C3 (de) Verfahren zur Herstellung von Isolationsschichten zwischen mehrschichtig übereinander angeordneten metallischen Leitungsverbindungen für eine Halbleiteranordnung
DE3818509A1 (de) Verfahren und einrichtung zum herstellen eines niederohmigen kontaktes mit aluminium und dessen legierungen durch selektives niederschlagen von wolfram

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase