WO1992021154A1 - Antifusibles au silicium amorphe et leurs procedes de fabrication - Google Patents

Antifusibles au silicium amorphe et leurs procedes de fabrication Download PDF

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Publication number
WO1992021154A1
WO1992021154A1 PCT/US1992/003919 US9203919W WO9221154A1 WO 1992021154 A1 WO1992021154 A1 WO 1992021154A1 US 9203919 W US9203919 W US 9203919W WO 9221154 A1 WO9221154 A1 WO 9221154A1
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WO
WIPO (PCT)
Prior art keywords
layer
plug
conductive
amorphous silicon
level
Prior art date
Application number
PCT/US1992/003919
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English (en)
Inventor
Kathryn E. Gordon
Richard J. Wong
Original Assignee
Quicklogic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quicklogic Corporation filed Critical Quicklogic Corporation
Priority to JP51099492A priority Critical patent/JP3209745B2/ja
Publication of WO1992021154A1 publication Critical patent/WO1992021154A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to programmable integrated circuit structures and methods for fabrication thereof, and more particularly to amorphous silicon antifuses and circuits and routing structures incorporating antifuses, and methods for fabrication thereof.
  • Programmable semiconductor devices include programmable read only memories (“PROMs”), programmable logic devices (“PLDs”) , and programmable gate arrays. Programmable elements suitable for one or more of these device types include fuses and antifuses.
  • a fuse is a structure which electrically couples a first terminal to a second terminal, but which, when programmed by passage of sufficient current between its terminals, electronically decouples the first terminal from the second terminal.
  • a fuse typically is of a conductive material which has a geometry that causes portions of the conductive fuse material to physically separate from each other when heated to the extent that an open circuit results.
  • An antifuse is a structure which when unprogrammed does not electrically couple its first and second terminals, but which, when programmed by applying sufficient voltage between the first and second terminals, permanently electrically connects the first and second terminals.
  • One type of antifuse comprises an amorphous silicon which forms conductive polysilicon when heated.
  • PROM devices for example, the advantages of the antifuse technology over fuse technology include scalability and reduced programming current requirement.
  • Various antifuses are disclosed in United States Patent No. 3,675,090, issued July 4, 1972 to Neale, and United States Patent No. 3,792,319, issued February 12, 1974 to Tsang.
  • amorphous silicon in the fabrication of semiconductor threshold and switch devices is well known.
  • various semiconductor switch devices comprise a "pore" filled with amorphous silicon, which contacts a lower electrode forming surface and an upper electrode forming surface.
  • Neale recognized the two important objectives were to obtain switch devices with a very low leakage current in the preprogrammed condition and a fairly consistent programming voltage value.
  • An aspect of the Neale invention was to fabricate the semiconductor switch device so as to present a very small cross-sectional area of semiconductor material for current flow to minimize leakage current paths therethrough.
  • Antifuses have been used successfully in programmable interconnect substrates, memories, and some types of PLDs. See, for example, U.S. Patent No. 4,458,297, issued July 3, 1984 to Stopper et al.
  • first metal comprising aluminum conductor 14 and barrier metal 10 and 11 is provided on an oxide layer 13 overlaying substrate 12.
  • a thick oxide layer 18 is provided over conductor 14 as insulation from second metal.
  • a via etched into oxide layer 18 is lined with a thin film of amorphous silicon 15, which fully overlays and contacts the barrier metal 11 under the via.
  • Second metal comprising barrier metal 16 and aluminum conductor 17 is provided over the via, in contact with the amorphous silicon 15.
  • the contact antifuse of Figure 2 is formed over a transistor comprising collector 20, base 21, and emitter 22. Emitter contact is made to a platinum suicide region 23 through a contact hole in oxide 24, which is lined with amorphous silicon film 25.
  • Barrier metal 26 and aluminum conductor 27 overlay the amorphous silicon 25, and are protected by oxide 28.
  • the deposition of the amorphous silicon was a critical step in the process, as the thickness of the film 15 ( Figure 1) and film 25 ( Figure 2) was thought to control the programming voltage.
  • the pre-programmed leakage current was reduced to about 6 microamperes at 2 volts by a high temperature anneal at 450 degrees C.
  • Other factors thought to influence leakage current in the undoped amorphous silicon antifuse were feature size (leakage current proportional) and film thickness (leakage current inversely proportional) .
  • Certain techniques have been employed in PLDs using antifuse technology to overcome the problems created by antifuse leakage.
  • One technique uses active semiconductor devices such as diodes or transistors to block the leakage current, an approach which can also be used in memories having leaky antifuses. While this approach is satisfactory in memories and in the logic configuration circuits of PLDs, the technique is not satisfactory for use in the routing circuits of such integrated circuits as the field programmable gate array (“FPGA”) .
  • FPGA field programmable gate array
  • the FPGA which is distinguished from conventional gate arrays by being user programmable, otherwise resembles a conventional gate array in having an interior matrix of logic blocks and a surrounding ring of I/O interface blocks.
  • Logic functions, I/O functions, and routing of interconnect networks are all user configurable, which affords high density and enormous flexibility suitable for most logic designs.
  • User logic for example, conventionally is implemented by interconnecting two-input NAND gates into more complex functions.
  • Extensive user configurability of the FPGA is achieved by incorporating a large number of programmable elements into the logic and the I/O blocks and the interconnect network.
  • the leakage requirement of the programmable elements is stringent, due to the large number of possible connections generally involved and the numerous failure modes that leakage can cause.
  • leaky programmable elements in the routing areas contribute to high supply current problems, cross talk problems, and performance degradation.
  • Some embodiments of the amorphous silicon antifuses of the present invention have a simple structure, a small size, small capacitance in the unprogrammed condition, small leakage current, and highly reproducible and controllable physical and electrical characteristics. Their manufacture requires very few process steps, and the process sequence provides a planar top surface for almost all the steps.
  • the amorphous silicon is planar in some embodiments so that a high quality, uniform thickness deposition thereof is facilitated.
  • the electrode overlaying the amorphous silicon is also planar in some embodiments, and the electrode fabrication is thereby facilitated.
  • the structure generally includes a dielectric layer having an opening therethrough; a conductive plug filling the opening, a top surface of the plug being substantially coplanar with a top surface of the dielectric layer; an amorphous silicon layer overlaying and contacting the plug; and a conductor overlaying and contacting the amorphous silicon layer. Further, a method is provided for fabricating an antifuse structure.
  • the method generally includes the steps of fabricating an insulating layer; fabricating an opening through the insulating layer at a selected location; fabricating a plug of conductive material in the opening so that a top surface of the plug is substantially coplanar with a top surface of the insulating layer; fabricating a layer of amorphous silicon overlaying and contacting the plug; and fabricating a conductor overlaying and contacting the amorphous silicon layer.
  • the invention further provides a programmable interconnect structure, a field programmable gate array, and a method for fabricating a field programmable gate array.
  • Figures 1 and 2 are cross-section illustrations of prior art amorphous silicon antifuse structures
  • Figures 3-5 are cross-section illustrations of intermediary structures of the processes of manufacturing an amorphous silicon antifuse according to the present invention.
  • Figure 6 is a cross-section illustration of an amorphous silicon antifuse of the present invention.
  • Figure 7 is a cross-section illustration of a portion of a programmable CMOS integrated circuit having an amorphous silicon antifuse in accordance with the present invention.
  • Figures 3-6 illustrate the basic steps of fabricating an antifuse structure that can be used, among other things, with programmable semiconductor devices.
  • the final structure, an amorphous silicon antifuse 30, is illustrated in Figure 6.
  • a first dielectric layer 34 typically of silicon dioxide, is formed on a silicon substrate (not shown) , and patterned to expose portions of the substrate. Alternatively, the dielectric layer 34 may be formed over other film layers (not shown) or features such as conductors (not shown) rather than directly on the substrate.
  • a first conductive layer 38 is formed on dielectric layer 34 and patterned to form appropriate interconnects. In one embodiment, the first conductive layer 38 is a layer of aluminum. In another embodiment, the first conductive layer 38 is TiW.
  • the first conductive layer 38 comprises various conductive layers (not shown) , including a thin layer of titanium covered by a thicker layer of aluminum. Other conductive.layers are suitable as well.
  • a second dielectric layer 40 is formed on the first conductive layer 38.
  • the second dielectric layer 40 is patterned to form vias, such as via 44, exposing the first conductive layer 38. Some of these vias, in particular via 44, will serve as sites for antifuses. Other vias, not shown, may allow for direct connection between first conductive layer 38 and a to-be-formed second conductive layer.
  • a plug 45 of conductive material is formed in via 44 so as to fill the via.
  • Plug 45 provides the bottom electrode of the antifuse.
  • the top surface of the plug 45 is substantially coplanar with the top surface of the second dielectric layer 40.
  • the plug 45 is made of tungsten. Tungsten plugs have been used to provide interlevel contacts between different conductive layers. Any suitable tungsten plug deposition technique may be used.
  • the plug 45 is formed by selective chemical vapor deposition ("CVD") of tungsten in the via 44. At the bottom of via 44, the material of first conductive layer 38 reacts with gaseous reactants so as to form tungsten in via 44. No tungsten is deposited, however, on top of the second dielectric layer 40 during the selective CVD. Selective CVD of tungsten is described generally in R.V.
  • the plug 45 is formed by a blanket CVD of tungsten followed by etch-back. As shown in Figure 5, the blanket CVD of tungsten provides tungsten layer 45 with a planar top surface. The layer 45 is etched until tungsten is etched off the top of the second dielectric layer 40. In a variation, a thin adhesion layer of TiW (not shown) is sputtered on the surface of the via 44 before the blanket CVD of the tungsten layer 45 of Figure 5. In another variation, a sacrificial layer of silicon nitride (not shown) is deposited on top of the second dielectric layer 40 before the via 44 is formed.
  • the silicon nitride protects the surface of the second dielectric layer 40 and reduces the loading effects during the etch of the tungsten layer 45 of Figure 5. After the etch, the remaining silicon nitride is removed.
  • Tungsten plug formation by blanket CVD and etch-back is generally described in J.M.F.G. van Laarhoven et al., "A Novel Blanket Tungsten Etchback Scheme," VMIC Conference, June 12-13, 1989, pp. 129-135, available from IEEE and hereby incorporated herein by reference thereto.
  • the plug 45 is formed by selective CVD of tungsten into the lower portion of the via 44 and then by the blanket CVD of tungsten and an etch-back so as to fill up the via 44. See generally T. Ohba et al. , supra.
  • layer 46 of amorphous silicon is deposited and patterned over the via 44.
  • Layer 46 is planar, and deposition of high quality amorphous silicon having uniform thickness and consistent, easily reproducible physical and electrical characteristics is thereby facilitated.
  • the thickness of amorphous silicon layer 46 in contact with the plug 45 is an important factor in controlling the programming voltage and leakage current of the antifuse.
  • the thickness of amorphous silicon layer 46 is about 1,600 angstroms. Of course, other thicknesses are suitable depending on the programming voltage desired.
  • amorphous silicon layer 46 is deposited using plasma enhanced chemical vapor deposition ("PECVD") .
  • PECVD plasma enhanced chemical vapor deposition
  • a suitable reactor is the Concept One reactor available from the Novellus Systems, Inc., San Jose, California. Suitable reactants and process parameters are described generally in the above-mentioned application Serial No. 07/447,969.
  • the second electrode of the antifuse 30 is formed by sputter depositing an about 2,000 angstrom layer 70 of titanium tungsten (TiW) and an about 8000 angstrom layer 72 of aluminum-copper (AlCu) .
  • TiW layer 70 and AlCu layer 72 are patterned to form the second electrode.
  • the mask used for patterning the second electrode layers 70 and 72 is smaller than the mask used to pattern the amorphous silicon 46 so that, in the worst misalignment case, the entire second electrode is above amorphous silicon 46. Portions of the amorphous silicon 46 that are exposed by the second electrode mask are etched away when layers 70 and 72 are etched during the second electrode formation.
  • Layers 70 and 72 are planar above the amorphous silicon layer 46. The planarity facilitates deposition of layers 70 and 72.
  • TiW layer 70 is a barrier layer that serves to prevent the aluminum of AlCu layer 72 from spiking into the amorphous silicon 46. Aluminum spikes would increase the leakage current or might even cause a short across the antifuse 30.
  • the antifuse 30 can be fabricated using fairly few process steps. Further, the process sequence provides a planar top surface for the amorphous silicon deposition and the top electrode formation. Since the amorphous silicon layer 46 and the second electrode layers 70 and 72 are planar, a high quality uniform deposition of layers 46, 70 and 72 is facilitated. Further, if plug 45 is made of tungsten, no barrier layer between the amorphous silicon 46 and the first conductive layer 38 is needed even if aluminum is used in the first conductive layer 38.
  • plug 45 as the bottom electrode allows to reduce the overall area of the antifuse 30 because a high quality plug with a good contact to first conductive layer 38 can be formed even when via 44 is narrow relative to the thickness of the second dielectric layer 40. Because of the small area of antifuse 30, leakage current and the capacitance of the unprogrammed antifuse are reduced. Further, in field programmable gate arrays with thousands or millions of antifuses, even a small size reduction of each antifuse may provide a significant overall size reduction of the FPGA.
  • the second dielectric layer 40 can be made quite thick so as to reduce the capacitance between the first conductive routing channels formed from the first conductive layer 38 and the second conductive routing channels formed from TiW layer 70 and AlCu layer 72.
  • FIG. 7 A cross-sectional view of a portion of a CMOS programmable gate array structure having an antifuse in accordance with the embodiment of Figure 6 is illustrated in Figure 7.
  • CMOS processes are well known and commercially available, and the particular CMOS structure shown is exemplary.
  • the antifuse 30 of Figure 6 can be used in integrated circuit structures of any type formed by any process, whether memory, logic, digital or analog, and including NMOS, PMOS, Bipolar, BICMOS, Gallium Arsenide, and others.
  • Substrate 100 is provided with a P-doped substrate region 104.
  • An NMOS device 162 that forms part of logic or I/O circuits of the gate array comprises source and drain regions 112 and 114 and gate 116.
  • Patterned oxide layers 118, 119 and 120 (shown in cross hatch) also are present.
  • oxide layer 118 is a field oxide
  • boro-phosphosilicate glass layer 119 is a contact oxide
  • oxide layer 120 comprises various oxide layers (not shown) formed in the fabrication of gate 116.
  • the oxide layers 118, 119 and 120 are suitably patterned and etched to form contact holes down to the various source and drain regions including regions 112 and 114.
  • Aluminum film 38 corresponds to the first conductive layer 38 of Figures 3-6.
  • First metal lines are formed by patterning and etching aluminum film 38 using a BC13, C12, CHC13 standard aluminum dry etch.
  • the intermetal dielectric is a thick oxide layer 40 of about 9,000 angstroms thickness, deposited using any suitable standard technique such as, for example, plasma enhanced chemical vapor deposition.
  • Layer 40 corresponds to the second dielectric layer 40 of Figures 3-6.
  • the layer 40 comprises two oxide layers (not shown) .
  • the first oxide layer is deposited to the selected thickness and planarized.
  • the planarization step involves spinning a resist layer over the deposited oxide and reflowing the resist with a postbake, after which the surface is planarized in an RIE etch-back adjusted for equal resist and oxide etch rates.
  • a second oxide layer then is deposited to ensure dielectric integrity and the 9,000 angstrom thickness over the irregular topography.
  • Antifuse vias 44a and 44b are now formed through the oxide 40 down to the aluminum film 38.
  • An antifuse via mask having the same dimension as the metal opening mask is used to pattern the oxide, and vias are etched to the Al film 38 using standard RIE techniques.
  • Conductive plugs 45a, 45b are formed in the respective vias 44a, 44b.
  • Plugs 45a, 45b provide bottom electrodes for the respective antifuses 30a, 30b.
  • the top surface of plugs 45 is substantially coplanar with the top surface of the oxide layer 40.
  • Planar amorphous silicon layer 46 of about 1,600 angstrom thickness is deposited and patterned over the antifuse vias 44. In some embodiments, amorphous silicon layer 46 is deposited by PECVD as described above in connection with Figure 6.
  • An about 2000 angstrom layer 70 of TiW and an about 8,000 angstrom layer 72 of aluminum-copper are sputter deposited and patterned by standard techniques to form the second metal lines.
  • the portions of layers 70 and 72 over vias 44 form the top electrodes of the respective antifuses 30.
  • Aluminum layer 38 provides first level routing channels connected to selected circuit elements of the gate array.
  • TiW layer 70 and AlCu layer 72 provide second level routing channels that are connected to selected circuit elements of the gate array. No additional metal layers are needed to form electrodes of antifuses 30 since the second level channels provide the top electrodes and plugs 45 provide the bottom electrodes.
  • the overall structure of the gate array is thereby simplified, and the number of process steps is reduced.
  • the second level routing channels extend generally orthogonally to the first level routing channels in a conventional layout shown, for example, in U.S. Patent No. 4,914,055, issued April 3, 1990 to Gordon et al., the disclosure of which patent is hereby incorporated herein by reference thereto.
  • the thick oxide 40 serves to reduce the capacitance between the first level routing channels and the second level routing channels.
  • vias 44 can be made narrow because good quality plugs 45. providing a good contact to aluminum layer 38 can be formed even in narrow vias. Significant size reduction of the gate array is thereby made possible. Leakage current and the capacitance of the unprogrammed antifuse are also reduced thereby.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

On forme un antifusible (30) au silicium amorphe entre deux électrodes. L'électrode inférieure (45) est une fiche, qui est en tungstène dans un mode d'exécution, formée dans un passage prévu dans une couche diélectrique (40). La surface supérieure de la fiche est coplanaire à la surface supérieure de la couche diélectrique. La couche de silicium amorphe située sur la fiche est donc plane, tout comme la couche d'électrode supérieure située sur le silicium amorphe. Par conséquent, la déposition du silicium amorphe (46) et de l'électrode supérieure est plus aisée. Les propriétés électriques de l'antifusible sont précisément contrôlées. Cet antifusible présente une structure simple, une petite taille, une faible capacitance lorsqu'il n'est pas programmé, et un faible courant de fuite. La fabrication de l'antifusible de cette invention ne nécessite que relativement peu d'étapes de traitement. Dans la séquence de traitement, on utilise une surface supérieure plane pour la déposition du silicium amorphe et la formation de l'électrode supérieure (70), (72).
PCT/US1992/003919 1991-05-10 1992-05-06 Antifusibles au silicium amorphe et leurs procedes de fabrication WO1992021154A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51099492A JP3209745B2 (ja) 1991-05-10 1992-05-06 アモルファスシリコンアンチヒューズ及びその製造方法

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US69864891A 1991-05-10 1991-05-10
US698,648 1991-05-10

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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995011524A1 (fr) * 1993-10-18 1995-04-27 Vlsi Technology, Inc. Structure antifusible multiniveau et son procede de fabrication
WO1996038861A1 (fr) * 1995-06-02 1996-12-05 Actel Corporation Antifusible a plot en tungstene sureleve et procede de fabrication
US5723358A (en) * 1996-04-29 1998-03-03 Vlsi Technology, Inc. Method of manufacturing amorphous silicon antifuse structures
US5753540A (en) * 1996-08-20 1998-05-19 Vlsi Technology, Inc. Apparatus and method for programming antifuse structures
US5789764A (en) * 1995-04-14 1998-08-04 Actel Corporation Antifuse with improved antifuse material
US5793094A (en) * 1995-12-28 1998-08-11 Vlsi Technology, Inc. Methods for fabricating anti-fuse structures
US5882997A (en) * 1996-09-30 1999-03-16 Vlsi Technology, Inc. Method for making devices having thin load structures
US6728126B1 (en) 2002-12-20 2004-04-27 Actel Corporation Programming methods for an amorphous carbon metal-to-metal antifuse
US6767769B2 (en) 2001-10-02 2004-07-27 Actel Corporation Metal-to-metal antifuse employing carbon-containing antifuse material
US6965156B1 (en) 2002-12-27 2005-11-15 Actel Corporation Amorphous carbon metal-to-metal antifuse with adhesion promoting layers
US7390726B1 (en) 2001-10-02 2008-06-24 Actel Corporation Switching ratio and on-state resistance of an antifuse programmed below 5 mA and having a Ta or TaN barrier metal layer
US7459763B1 (en) 2001-10-02 2008-12-02 Actel Corporation Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material
US11177213B2 (en) 2020-01-28 2021-11-16 International Business Machines Corporation Embedded small via anti-fuse device

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US4933898A (en) * 1989-01-12 1990-06-12 General Instrument Corporation Secure integrated circuit chip with conductive shield

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US3675090A (en) * 1968-11-04 1972-07-04 Energy Conversion Devices Inc Film deposited semiconductor devices
US4424578A (en) * 1980-07-14 1984-01-03 Tokyo Shibaura Denki Kabushiki Kaisha Bipolar prom
US4499557A (en) * 1980-10-28 1985-02-12 Energy Conversion Devices, Inc. Programmable cell for use in programmable electronic arrays
US4458297A (en) * 1981-01-16 1984-07-03 Mosaic Systems, Inc. Universal interconnection substrate
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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5565703A (en) * 1993-10-18 1996-10-15 Vlsi Technology, Inc. Multi-level antifuse structure
WO1995011524A1 (fr) * 1993-10-18 1995-04-27 Vlsi Technology, Inc. Structure antifusible multiniveau et son procede de fabrication
US5789764A (en) * 1995-04-14 1998-08-04 Actel Corporation Antifuse with improved antifuse material
WO1996038861A1 (fr) * 1995-06-02 1996-12-05 Actel Corporation Antifusible a plot en tungstene sureleve et procede de fabrication
US5804500A (en) * 1995-06-02 1998-09-08 Actel Corporation Fabrication process for raised tungsten plug antifuse
US5793094A (en) * 1995-12-28 1998-08-11 Vlsi Technology, Inc. Methods for fabricating anti-fuse structures
US5962911A (en) * 1996-04-29 1999-10-05 Vlsi Technology, Inc. Semiconductor devices having amorphous silicon antifuse structures
US5723358A (en) * 1996-04-29 1998-03-03 Vlsi Technology, Inc. Method of manufacturing amorphous silicon antifuse structures
US5753540A (en) * 1996-08-20 1998-05-19 Vlsi Technology, Inc. Apparatus and method for programming antifuse structures
US5882997A (en) * 1996-09-30 1999-03-16 Vlsi Technology, Inc. Method for making devices having thin load structures
US6767769B2 (en) 2001-10-02 2004-07-27 Actel Corporation Metal-to-metal antifuse employing carbon-containing antifuse material
US7390726B1 (en) 2001-10-02 2008-06-24 Actel Corporation Switching ratio and on-state resistance of an antifuse programmed below 5 mA and having a Ta or TaN barrier metal layer
US7459763B1 (en) 2001-10-02 2008-12-02 Actel Corporation Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material
US6728126B1 (en) 2002-12-20 2004-04-27 Actel Corporation Programming methods for an amorphous carbon metal-to-metal antifuse
US6965156B1 (en) 2002-12-27 2005-11-15 Actel Corporation Amorphous carbon metal-to-metal antifuse with adhesion promoting layers
US7358589B1 (en) 2002-12-27 2008-04-15 Actel Corporation Amorphous carbon metal-to-metal antifuse with adhesion promoting layers
US11177213B2 (en) 2020-01-28 2021-11-16 International Business Machines Corporation Embedded small via anti-fuse device

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JPH06510634A (ja) 1994-11-24
AU1904992A (en) 1992-12-30
JP3209745B2 (ja) 2001-09-17

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