WO1992021150A1 - Integrated circuit chip carrier - Google Patents
Integrated circuit chip carrier Download PDFInfo
- Publication number
- WO1992021150A1 WO1992021150A1 PCT/US1992/003361 US9203361W WO9221150A1 WO 1992021150 A1 WO1992021150 A1 WO 1992021150A1 US 9203361 W US9203361 W US 9203361W WO 9221150 A1 WO9221150 A1 WO 9221150A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- semiconductor device
- pads
- solder
- active surface
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Definitions
- This invention relates generally to the field of integrated circuits and most particularly to a reduced size integrated circuit chip carrier.
- the integrated circuit chip is brittle and fragile and subject to stress and breakage if the circuit board is bent, vibrated or exposed to wide variations in temperature. Accordingly, in many applications such as two-way radios and other portable communication devices, where the electrical assembly is subject to vibration and severe environmental disturbances, direct connections between the integrated circuit chip and the circuit board are not desirable and can cause reliability problems.
- Conventional ways of protecting and packaging the integrated circuit such as chip carriers or transfer molded integrated circuit devices, provide a buffer substrate or mounting scheme between the integrated circuit and the circuit board, thereby reducing or eliminating the stress imparted to the chip during mechanical and thermal excursions.
- Chip carriers are larger than the integrated circuit and typically require two to three times the area on the circuit board as the integrated circuit. The finished package is typically expensive and not repairable. The inability to repair a rather expensive package becomes a liability in electrical testing.
- chip-on-board technology the density of lines and spaces required on the circuit board is extremely high, thereby creating a very complex printed circuit board with fine lines and spaces that is very expensive to manufacture.
- chip carriers allows one to incorporate printed circuit boards with less stringent line and space requirements, thereby reducing the cost of the printed circuit board. This cost reduction comes at the expense of using a larger chip carrier package which is more expensive and also has a greater height.
- the semiconductor device is attached to the substrate by means of the control-collapse-chip-connection (known as C4).
- C4 control-collapse-chip-connection
- a clean room environment must be utilized during this process. One can easily see that the C4 process is not suitable for a normal manufacturing assembly environment where components are mounted onto circuit boards.
- an integrated circuit device assembly comprising a semiconductor device with interconnecting pads arranged on an active surface of the device.
- the device is bonded to a substrate by attaching the device face down to corresponding circuit pads on the substrate.
- the circuit pads of the substrate are connected to solder pads on the opposite side of the substrate by conductive thru-holes.
- the integrated circuit device is connected to the substrate by electrically conductive bumps between the device pads and the substrate pads such that the device covers at least some of the conductive thru-holes on the substrate.
- the gap between the device and the substrate may be filled with an organic coupling agent such as an epoxy resin.
- FIG. 1 is an isometric cut-away view of the integrated circuit chip carrier in accordance with the invention.
- FIG. 2 is a cross section of the chip carrier of FIG. 1 through section 2-2.
- FIG. 3 is a cross section of an alternate embodiment of the chip carrier of FIG. 1 through section 2-2.
- FIG. 4 is a cross section of an alternate embodiment of the chip carrier of FIG. 1 through section 2-2.
- an integrated circuit or semiconductor device 10 contains an active surface 12 having interconnection pads 14 arranged in a configuration near the perimeter of the device.
- a circuit carrying substrate 16 has an array of interconnection pads 18 that correspond to the interconnect pads 14 of the device.
- the substrate material is typically a printed circuit board. Circuit boards made from materials with low expansion coefficients are preferred (between about 6 and about 18 in/in/ o Cxl0"*-*-).
- One example of a useful material is Thermount E-215/CE laminate from the DuPont Corporation of Wilmington, Delaware. This laminate is an epoxy resin reinforced with aramid fiber. Other types of organic resins such as polyesters, polyamides, polyimides, and modifications or blends of these resins may also be employed in conjunction with the aramid reinforcements.
- the substrate 16 also contains other circuitry 20 that interconnects the pads to conductive thru-holes or vias 22 in the substrate.
- the circuitry 20 may also be connected to semicircular conductive thru-holes 24 on the perimeter of the substrate.
- each of the integrated circuit interconnect pads 14 may be routed to a corresponding solder pad on the bottom of the substrate 16.
- the lines and spaces required for the solder pads are much larger than those on the integrated circuit device since the entire surface of the substrate may be used.
- spaces between interconnect pads on an integrated circuit device are typically 0.004 inches.
- the spacings between the solder pads on the bottom of the substrate may be as great as 0.030 inches.
- the solder pad diameters may be as great as 0.030 inches as opposed to 0.004 inches on the device interconnect pads.
- the semiconductor device 10 is attached to the substrate by facing the active surface 12 of the device 10 toward the upper surface of the substrate 16. Interconnection of the device to the substrate is provided by means of conductive bumps 26 between the pads 14 of the device and the circuitry 18 of the substrate. These bumps may typically be made from solder or be thermocompression bonds, conductive epoxy, or conductive elastomer. If they are made from solder, the device is attached to the substrate by means of the control-collapse-chip-connection (C4). This type of connection is well known to those skilled in the art and has been utilized to achieve high-density circuitry.
- C4 control-collapse-chip-connection
- an organic coupling agent 28 may be applied in the gap between the integrated circuit and the substrate.
- This coupling agent may be, for example, a rigid adhesive such as an epoxy or a softer material such as a silicone.
- Hysol FP 4510 an epoxy from the Dexter Corporation of Industry, California.
- the coupling agent serves to provide additional mechanical bonding between the device and the substrate and also serves as a stress relieving member.
- the third function of the coupling agent is to environmentally protect the active surface of the device and the interconnections. Depending on the application, the coupling agent may cover the entire gap between the device and the substrate or may only cover a portion of the active surface of the device.
- the integrated circuit 10 lies over some of the conductive thru-holes 22.
- Each of the conductive thru-holes 22 connects to a solder pad 23 on the bottom side of the substrate 16.
- the organic coupling agent or underfill material 28 fills the gap between the device 10 and the substrate 16.
- the interconnect pads 14 of the device 10 are connected to the circuitry pads 18 of the substrate by means of a metallic bump 26.
- the overall size of the substrate 16 is only slightly larger than the overall size of the integrated circuit 10.
- the length and width of the substrate is no greater than 0.15 inches greater than the length and width of the device and may be as small as the device itself in some cases.
- the substrate is 0.025 to 0.1 inches greater than the largest dimension of the device.
- the assembled integrated circuit chip carrier may now be electrically tested with conventional testing equipment, without having to resort to expensive and complex semiconductor testing equipment. Since the carrier is tested at a package level, the testing regime can be more thorough, and does not require the complexity and miniaturization necessary for testing at the wafer level.
- an alternate embodiment of the invention comprises attaching the semiconductor device 10 to a substrate 36 containing circuitry patterns 18 on one side only.
- the device 10 is directly attached via solder bumps 26 to the circuitry pattern on the top side of the substrate 36 to create a chip carrier assembly.
- the circuitry pattern extends to a hole 22 in the substrate, and may terminate in an annular ring around the hole or may cover the hole entirely so as to tent the hole.
- the assembly may contain the above referenced organic coupling agent 28 if desired.
- the carrier is soldered to the PCB using additional, usually larger, solder bumps 37.
- the solder bumps 37 are soldered to the circuitry pattern 18 by forming the bumps in the substrate hole 32 so that the solder 37 connects to the back side of the circuitry pattern 18.
- a semiconductor device 10 is attached to a substrate 46 having a circuitry pattern 48 on the back side of the substrate.
- the device is connected to the back side of the circuitry pattern via a series of solder bumps 46 that extend through a hole 42 in the substrate to create a chip carrier assembly.
- the assembly may contain the above referenced organic coupling agent 28 if desired.
- the carrier is soldered to the PCB using additional, usually larger, solder bumps 47.
- the solder bumps 47 are soldered to the circuitry pattern 48 and the PCB 25 using, for example, a C5 process.
- a package created in accordance with the invention provides numerous advantages, amongst which are: a package with a smaller footprint than conventional chip carrier packages, a package with a footprint only slightly larger than the actual size of the integrated circuit itself, a package with significantly reduced height (only slightly greater than the height of the integrated circuit), a package that may be easily tested prior to assembly to a main circuit board, and a package that does not require clean room environments for assembling an integrated circuit to a main circuit board.
- the present invention satisfies a long- existing need for an improved integrated circuit chip carrier that is smaller is size, more reliable, lower cost, easier to manufacture, and is electrically testable.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930702937A KR970011620B1 (en) | 1991-05-23 | 1992-04-23 | Integrated circuit chip carrier |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US70447191A | 1991-05-23 | 1991-05-23 | |
US704,471 | 1991-05-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1992021150A1 true WO1992021150A1 (en) | 1992-11-26 |
Family
ID=24829653
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1992/003361 WO1992021150A1 (en) | 1991-05-23 | 1992-04-23 | Integrated circuit chip carrier |
Country Status (5)
Country | Link |
---|---|
US (1) | US5293067A (en) |
EP (1) | EP0585376A4 (en) |
JP (1) | JP2570498B2 (en) |
KR (1) | KR970011620B1 (en) |
WO (1) | WO1992021150A1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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EP0715348A3 (en) * | 1994-11-29 | 1998-07-15 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices |
US5976912A (en) * | 1994-03-18 | 1999-11-02 | Hitachi Chemical Company, Ltd. | Fabrication process of semiconductor package and semiconductor package |
WO2000035009A1 (en) * | 1998-12-08 | 2000-06-15 | Alexandr Ivanovich Taran | Substrate for ic crystals |
US6138348A (en) * | 1989-12-18 | 2000-10-31 | Polymer Flip Chip Corporation | Method of forming electrically conductive polymer interconnects on electrical substrates |
US6365499B1 (en) | 1995-02-23 | 2002-04-02 | Matsushita Electric Industrial Co., Ltd. | Chip carrier and method of manufacturing and mounting the same |
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---|---|---|---|---|
US7198969B1 (en) * | 1990-09-24 | 2007-04-03 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
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US5501006A (en) * | 1993-09-22 | 1996-03-26 | Motorola, Inc. | Method for connection of signals to an integrated circuit |
US5418471A (en) * | 1994-01-26 | 1995-05-23 | Emulation Technology, Inc. | Adapter which emulates ball grid array packages |
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US5625224A (en) * | 1994-08-10 | 1997-04-29 | Motorola, Inc. | Method and apparatus for an integrated circuit chip carrier having improved mounting pad density |
US5444303A (en) * | 1994-08-10 | 1995-08-22 | Motorola, Inc. | Wire bond pad arrangement having improved pad density |
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US5731709A (en) * | 1996-01-26 | 1998-03-24 | Motorola, Inc. | Method for testing a ball grid array semiconductor device and a device for such testing |
US5637916A (en) * | 1996-02-02 | 1997-06-10 | National Semiconductor Corporation | Carrier based IC packaging arrangement |
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US6007348A (en) | 1996-05-07 | 1999-12-28 | Advanced Intercommunications Corporation | Solder ball terminal |
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US6093971A (en) * | 1996-10-14 | 2000-07-25 | Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. | Chip module with conductor paths on the chip bonding side of a chip carrier |
US5814401A (en) * | 1997-02-04 | 1998-09-29 | Motorola, Inc. | Selectively filled adhesive film containing a fluxing agent |
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US6441487B2 (en) | 1997-10-20 | 2002-08-27 | Flip Chip Technologies, L.L.C. | Chip scale package using large ductile solder balls |
KR100259359B1 (en) | 1998-02-10 | 2000-06-15 | 김영환 | Substrate for semiconductor device package, semiconductor device package using the same and manufacturing method thereof |
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SG75841A1 (en) | 1998-05-02 | 2000-10-24 | Eriston Invest Pte Ltd | Flip chip assembly with via interconnection |
US6406939B1 (en) | 1998-05-02 | 2002-06-18 | Charles W. C. Lin | Flip chip assembly with via interconnection |
US6291776B1 (en) * | 1998-11-03 | 2001-09-18 | International Business Machines Corporation | Thermal deformation management for chip carriers |
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US6544813B1 (en) | 2000-10-02 | 2003-04-08 | Charles W. C. Lin | Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment |
US6492252B1 (en) | 2000-10-13 | 2002-12-10 | Bridge Semiconductor Corporation | Method of connecting a bumped conductive trace to a semiconductor chip |
US6667229B1 (en) | 2000-10-13 | 2003-12-23 | Bridge Semiconductor Corporation | Method of connecting a bumped compliant conductive trace and an insulative base to a semiconductor chip |
US6740576B1 (en) | 2000-10-13 | 2004-05-25 | Bridge Semiconductor Corporation | Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly |
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US6908788B1 (en) | 2000-10-13 | 2005-06-21 | Bridge Semiconductor Corporation | Method of connecting a conductive trace to a semiconductor chip using a metal base |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS599441A (en) * | 1982-07-08 | 1984-01-18 | Yamatake Honeywell Co Ltd | Starting operation of heat source equipment |
JPS61279164A (en) * | 1985-06-05 | 1986-12-09 | Hitachi Ltd | Multiple chip module |
US4821142A (en) * | 1986-06-06 | 1989-04-11 | Hitachi, Ltd. | Ceramic multilayer circuit board and semiconductor module |
US4893172A (en) * | 1987-01-19 | 1990-01-09 | Hitachi, Ltd. | Connecting structure for electronic part and method of manufacturing the same |
US4963414A (en) * | 1989-06-12 | 1990-10-16 | General Electric Company | Low thermal expansion, heat sinking substrate for electronic surface mount applications |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5994441A (en) * | 1982-11-19 | 1984-05-31 | Nippon Denso Co Ltd | Semiconductor device |
JPS60154632A (en) * | 1984-01-25 | 1985-08-14 | Hitachi Ltd | Semiconductor device |
JPS6127667A (en) * | 1984-07-17 | 1986-02-07 | Mitsubishi Electric Corp | Semiconductor device |
JPS6252930A (en) * | 1985-09-02 | 1987-03-07 | Canon Inc | Semiconductor manufacture equipment |
US4933810A (en) * | 1987-04-30 | 1990-06-12 | Honeywell Inc. | Integrated circuit interconnector |
JPS63301552A (en) * | 1987-06-01 | 1988-12-08 | Nec Corp | Wiring substrate |
JPH01132150A (en) * | 1987-11-18 | 1989-05-24 | Hitachi Ltd | Carrier substrate of semiconductor chip |
JP2638089B2 (en) * | 1988-06-20 | 1997-08-06 | 日本電気株式会社 | Semiconductor device |
EP0351581A1 (en) * | 1988-07-22 | 1990-01-24 | Oerlikon-Contraves AG | High-density integrated circuit and method for its production |
JPH0269945A (en) * | 1988-09-05 | 1990-03-08 | Hitachi Ltd | Semiconductor device and manufacture thereof |
US4954878A (en) * | 1989-06-29 | 1990-09-04 | Digital Equipment Corp. | Method of packaging and powering integrated circuit chips and the chip assembly formed thereby |
-
1992
- 1992-04-23 WO PCT/US1992/003361 patent/WO1992021150A1/en not_active Application Discontinuation
- 1992-04-23 JP JP5500049A patent/JP2570498B2/en not_active Expired - Lifetime
- 1992-04-23 KR KR1019930702937A patent/KR970011620B1/en not_active IP Right Cessation
- 1992-04-23 EP EP19920912829 patent/EP0585376A4/en not_active Withdrawn
- 1992-06-12 US US07/898,231 patent/US5293067A/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS599441A (en) * | 1982-07-08 | 1984-01-18 | Yamatake Honeywell Co Ltd | Starting operation of heat source equipment |
JPS61279164A (en) * | 1985-06-05 | 1986-12-09 | Hitachi Ltd | Multiple chip module |
US4821142A (en) * | 1986-06-06 | 1989-04-11 | Hitachi, Ltd. | Ceramic multilayer circuit board and semiconductor module |
US4893172A (en) * | 1987-01-19 | 1990-01-09 | Hitachi, Ltd. | Connecting structure for electronic part and method of manufacturing the same |
US4963414A (en) * | 1989-06-12 | 1990-10-16 | General Electric Company | Low thermal expansion, heat sinking substrate for electronic surface mount applications |
Non-Patent Citations (1)
Title |
---|
See also references of EP0585376A4 * |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6138348A (en) * | 1989-12-18 | 2000-10-31 | Polymer Flip Chip Corporation | Method of forming electrically conductive polymer interconnects on electrical substrates |
US5976912A (en) * | 1994-03-18 | 1999-11-02 | Hitachi Chemical Company, Ltd. | Fabrication process of semiconductor package and semiconductor package |
US6365432B1 (en) | 1994-03-18 | 2002-04-02 | Hitachi Chemical Company, Ltd. | Fabrication process of semiconductor package and semiconductor package |
EP1213754A2 (en) * | 1994-03-18 | 2002-06-12 | Hitachi Chemical Co., Ltd. | Fabrication process of semiconductor package and semiconductor package |
US6746897B2 (en) | 1994-03-18 | 2004-06-08 | Naoki Fukutomi | Fabrication process of semiconductor package and semiconductor package |
EP1213754A3 (en) * | 1994-03-18 | 2005-05-25 | Hitachi Chemical Co., Ltd. | Fabrication process of semiconductor package and semiconductor package |
US7187072B2 (en) | 1994-03-18 | 2007-03-06 | Hitachi Chemical Company, Ltd. | Fabrication process of semiconductor package and semiconductor package |
EP0715348A3 (en) * | 1994-11-29 | 1998-07-15 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices |
US6365499B1 (en) | 1995-02-23 | 2002-04-02 | Matsushita Electric Industrial Co., Ltd. | Chip carrier and method of manufacturing and mounting the same |
WO2000035009A1 (en) * | 1998-12-08 | 2000-06-15 | Alexandr Ivanovich Taran | Substrate for ic crystals |
US6410937B1 (en) | 1998-12-08 | 2002-06-25 | Alexsander Ivanovich Taran | Integrated circuit chip carrier |
Also Published As
Publication number | Publication date |
---|---|
KR970011620B1 (en) | 1997-07-12 |
EP0585376A4 (en) | 1994-06-08 |
US5293067A (en) | 1994-03-08 |
EP0585376A1 (en) | 1994-03-09 |
JP2570498B2 (en) | 1997-01-08 |
JPH06510396A (en) | 1994-11-17 |
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