WO1992020101A1 - Method for mounting an integrated circuit chip on a wiring substrate - Google Patents

Method for mounting an integrated circuit chip on a wiring substrate Download PDF

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Publication number
WO1992020101A1
WO1992020101A1 PCT/FR1992/000327 FR9200327W WO9220101A1 WO 1992020101 A1 WO1992020101 A1 WO 1992020101A1 FR 9200327 W FR9200327 W FR 9200327W WO 9220101 A1 WO9220101 A1 WO 9220101A1
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WIPO (PCT)
Prior art keywords
substrate
chip
conductive
assembly
mounting
Prior art date
Application number
PCT/FR1992/000327
Other languages
French (fr)
Inventor
Michel Massiot
Original Assignee
Societe Rennaise D'electronique Professionnelle (S.O.R.E.P.)
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Application filed by Societe Rennaise D'electronique Professionnelle (S.O.R.E.P.) filed Critical Societe Rennaise D'electronique Professionnelle (S.O.R.E.P.)
Publication of WO1992020101A1 publication Critical patent/WO1992020101A1/en

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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Definitions

  • the present invention relates to a method for mounting an integrated circuit chip on a wiring substrate. It also relates to an assembly constituted by the assembly of integrated circuit chips on a wiring substrate.
  • the low-temperature co-cooking technique of multilayer substrate appears to be an excellent solution to many integration problems, since the density of i ⁇ ter-connection can be extremely high.
  • a conductive material such as gold or silver.
  • the term "conductive channel” will designate such a hole filled with a conductive material, a channel which is commonly called "via”.
  • the diameter of these channels can be of the order of 90 to 110 micrometers, or even less. Line width and the dimensions of the intervals between the lines and the channels are of the same order of magnitude e.
  • Another advantage of this type of multi-layer substrate is that it is easy to increase the number of layers at very reasonable prices, to integrate mass and supply grids, to draw wider tracks if necessary, with conductors of low resistivity.
  • its versatility in terms of its connections and its e ⁇ capsulation that is to say with chips mounted on both sides or chips mounted on one side and resistors on the other side, and the possibility to form resistances thereon by screen printing, are still additional advantages.
  • the co-cuisso ⁇ of the layers takes place at a temperature below 1100 to 1200 ° C, generally of the order of 850 ° C, which is called "low temperature" in opposition to the co-cuisso ⁇ at high temperature which requires the use of temperatures above 1500 ° C and requires the use of refractory materials such as tungsten for example.
  • the first technique is that of traditional wiring, designated by the English term “ire-bo ⁇ di ⁇ g”, according to which the connection between the chip and the substrate is made by gold or aluminum wires whose diameter is generally of the order of 25 micrometers.
  • the major drawback of this technique is that it is necessary to have wiring areas around the chips whose relatively large surface limits the density of the assembly.
  • Another assembly technique is known by the name “TAB”, from the English “tape automated bondi ⁇ g”, which could be translated into French by "automated link to ribbons”.
  • the connections are generally made by copper tapes held on a polyimide support in the form of strips.
  • This technique has the advantage of allowing easy testing of chips before mounting and is advantageous for large series and possibly for very high complexity chips. But in this case too, a relatively large area must be provided around the chips to allow the ribbons to be connected to the substrate.
  • a third technique known to those skilled in the art under the English name "flip-chip” consists of forming small metal bosses, which form contact pads, on the connection pads located on the active faces of the chips.
  • the bosses are generally made of gold or of an alloy based on lead or i ⁇ dium.
  • the bosses are then transferred upside down on the substrate, by direct welding on a metallized area. provided on the substrate. This process was developed in the 1970s but its development has been limited because of the very significant difficulties it presents. It is indeed necessary a great regularity in the manufacture of the bosses, in the positioning of the chips and in the reflow process ensuring the welding.
  • the welds once made, are very subject to thermal fatigue during the operating / stopping cycles of the chips, and even simply during the thermal cycles linked to the environment. On the other hand, if these difficulties are overcome, the performance of such a technology in terms of integration density and signal speed is maximum. Other advantages of this technique are that it offers the possibility of obtaining surface and non-peripheral inputs and outputs as in the two techniques described above.
  • the gain in density of the "flip-chip" compared to traditional wiring or TAB is in a ratio of the order of 1.2 to 1.5, this ratio depending of course on the dimensional characteristics of the chips.
  • the general idea underlying the present invention is to put the "flip-chip" technology back on the agenda, from a new angle, by applying it to a substrate whose channels conductors (vias) open on at least one of the faces of the substrate, which is the case in particular for the substrates obtained by co-cooking at low temperature.
  • Such a substrate can indeed include a complex i ⁇ ter-co ⁇ exio ⁇ and be an integral part of a complete encapsulation, which allows maximum performance to be obtained at lower cost.
  • Such a substrate also has excellent flatness, easily controllable, which makes it compatible with a process requiring high dime ⁇ sio ⁇ nelles precision.
  • the metallic material constituting the "vias" can be modified so that there is a large latitude of choice as a function of the characteristics not only of metal but also mechanical properties of the material.
  • the invention therefore relates to a method for mounting an integrated circuit chip on a wiring substrate, at least one of the faces of which has a set of through conductive channels, for example cylindrical, this substrate being advantageously, but not necessarily , a multi-layer type substrate which, preferably, is obtained by the co-cuisso ⁇ process at low temperature.
  • the method is characterized by the following stages: a) the substrate is produced in such a way that the location of said conductive channels strictly coincides with that of the conductive pads arranged on the active face of the chip and intended for its electrical connection with the substrate; b) an approximately hemispherical boss is deposited on each of these conductive pads, the diameter of which is slightly less than the dimensions of the cross section of the conductive channels, in this case their diameter if these channels are cylindrical; c) the chip is positioned on the substrate, active side facing the mounting face, so that each boss is placed in abutment on the through end of a channel; d) applying a pressure tending to bring the chip closer to the substrate so as to partially penetrate each of the bosses in the conductive material of the channel associated with it by making an electrical connection at this level.
  • step c) When dealing with a substrate of the multi-layer type, it is advantageous to mount the chip inside an opening formed in at least one of the constituent layers of the substrate, by fixing it to the underlying layer. ; this arrangement makes it possible to drown the chip inside the substrate.
  • step c) during which a pressure is applied which tends to bring the chip closer to the substrate, is carried out with the application of heat and ultra-so ⁇ s.
  • - - -2 -2 conductor is preferably between 9.8.10 and 29.4.10 Newton (10 and 30 gf).
  • boss-shaped conductive parts it is preferable to operate from a wire, the end of which is melted, giving it the shape of a ball which is deposited on the chip, after which the wire is cut. flush with the ball.
  • This technique is directly derived from the traditional wiring technique in which the connection of the chip with the substrate is made by a wire of which one end has the shape of a ball deposited on the chip and the other, in the shape of a crescent, is deposited on the substrate.
  • Such a technique is usually designated by the English name "ball-bo ⁇ ding", which could be translated as "binding to ball ". It is thus possible to use standard chips, without special preparation, the fitting of bosses can be done on demand directly on the chips.
  • the bosses have an average diameter between 50 and 100 micrometers, while the conductive channels have a diameter between 80 and 150 micrometers.
  • the mechanical connection between the chip and the substrate which results from the partial penetration of the bosses into the material of the conductive channels, is generally sufficient for the chip / substrate assembly to be able to be used under normal conditions. It is possible and advantageous, to improve the mechanical connection and / or the quality of the heat transfer between the chip and the substrate, to interpose between these two elements an organic compound; this could be spread between the two opposite faces during the application of the pressure in step c); it could also be applied after assembly by impregnation.
  • the invention makes it possible to obtain a mounting in which the active face of the chip is very slightly spaced from the mounting face of the substrate, which further facilitates heat dissipation from the chip to the substrate.
  • the invention finally makes it possible to mount chips on both sides of the substrate, which in theory makes it possible to double the integration density.
  • the invention also relates to an assembly constituted by the assembly of integrated circuit chips on a wiring substrate.
  • this assembly is remarkable by the fact that the active face of the chips is furnished with a set of conductive bosses, of approximately hemispherical shape, which are directly and partially inserted each in a channel filled with a conductive material (malleable ) and opening onto one of the faces of the substrate.
  • this assembly comprises an organic compound interposed between the two faces opposite the chips and the substrate; this compound ensures, or at least consolidates, the mechanical bond between chips and substrate while promoting the transfer of heat from the chips to the substrate.
  • the substrate is a multilayer ceramic substrate obtained by co-firing at low temperature.
  • FIG. 1 is a detail view on a large scale illustrating the operation of depositing a conductive boss on the active face of a chip
  • FIG. 2 is a general view illustrating the principle of assembly of the chip to the substrate
  • FIG. 4 is a detail view showing the connection of the boss of Figure 1 with the associated conductive channel of the substrate;
  • FIG. 5 is a partial view of a similar assembly between a chip and a substrate, in which the interposition of an organic compound is provided;
  • - Figure 6 is a partial top view on a large scale of a substrate having a number of through conductive channels;
  • - Figure 7 is a view of the active face of a chip, on which are arranged conductive bosses whose location coincides with the through channels of the substrate of Figure 6;
  • FIGS. 8 and 9 are partial views intended to show respectively the possibilities of mounting chips on the two faces of the substrate, and mounting a chip in an opening of the outer layer of a multi-layer substrate.
  • an integrated circuit chip this being seen from the side.
  • the substrate is first of all designed and manufactured in such a way that the conduc ⁇ tor channels which open onto their mounting face have rigorously the same geometric distribution as those of the metallized areas lining the (or the) chip (s) that the substrate must receive.
  • a co ⁇ ductor pad 3 is deposited on each of the pads 10.
  • This operation is advantageously done by a method and using a device already known, used in the traditional wire cabling technique ("ball-bonding" ").
  • the chip is placed on a heating support, active face 100 facing upwards.
  • a ceramic capillary tool is used which is vibrated by means of an ultrasonic generator via an appropriate transducer.
  • the capillary is a tube through which passes a small diameter gold wire, for example 17 micrometers.
  • the end of the wire is first of all fused, which has the effect of forming a ball 31 of generally hemispherical shape.
  • this ball is applied under pressure on track 10, with emission of heat and ultrasound, so that it is fixed on track 10.
  • the tool is then removed and the wire 30 sectioned flush with the ball. This gives a boss.
  • its average diameter ⁇ is of the order of 60 micrometers and its height _h_ of the order of 50 micrometers.
  • FIG. 7 shows the arrangement of a set of bosses 31 on the active face of the chip 1. This is for example a chip with rectangular outline of dimensions 5 mm x 4 mm.
  • the substrate 2 is a multi-layer substrate.
  • the substrate is composed of four ceramic sheets referenced 20a, 20b, 20c, 20d, which form a one-piece assembly following a so-called low temperature firing (of the order of 850 ° C).
  • each layer has a certain number of cylindrical holes which pass through them.
  • These holes 400 are then filled by screen printing with a conductive material, for example gold, which makes it possible to obtain conductive channels 4 (see FIG. 4 ).
  • the subsequent stacking and baking will allow the chips to be linked together (or with the outside) via conductive channels ("vias") and conductive tracks, most often passing through the internal layers.
  • FIG. 6 represents the holes which open onto one of the external faces of the substrate, in this case, the mounting face 200 which is intended to receive the chip 1.
  • the arrangement of these conductive channels corresponds strictly to that of the bosses 3 so that, if the chip 1 is positioned on the substrate, its active face 100 facing the mounting face 200, each boss 3 is positioned exactly opposite a conductive channel 4.
  • the boss referenced 32 after turning the chip 1 over on the substrate, is intended to come into correspondence with the conductive channel marked 42.
  • the contour in broken lines C_ represents the chip 1 when it is positioned on the substrate 2. It will be noted that at four angles of this contour are provided for conducting channels 40. These have no function in the wiring of the assembly, but serve for the correct positioning, by means of appropriate detection means, of the chip on the substrate for the assembly operation, operation illustrated in FIG. 2.
  • connection pads 10 (and, correlatively, the bosses 3 with which these pads are provided) are arranged at the periphery of the chip.
  • connection pads in certain areas of the chip remote from its edges.
  • the substrate 2 is placed on a heating base 5.
  • the heating means are for example electrical resistors integrated inside the base 5. They are adapted to develop, at the level of the connection between the boss 3 and the conductive channels 4, a temperature between 100 and 200 ° C, for example 150 ° C.
  • the chip 1 is positioned correctly on the substrate 2, this positioning being helped by means of detector means not shown referring to the reference channels 40.
  • the assembly device roughly shown in Figure 2 includes a pressing tool 6. It is for example a ceramic rod whose end is provided with a pressing plate 60, for example discoid, abutting against the central region of the chip 1.
  • An ultrasonic generator 70 makes it possible, via the ediary of a transducer member 7, to vibrate the tool 6 at an ultrasonic frequency. This vibration is represented by the double arrow G.
  • the vibration is preferably multidirectional. It has for example two perpendicular components located in the horizontal plane, that is to say in the plane of the chip (one £ in the plane of the sheet of drawings, and the other perpendicular to the plane of the sheet , with reference to Figure 2).
  • a force is applied to the tool 6 so as to exert on the chip 1 a pressure tending to bring it closer to the substrate 2.
  • the force is generated by suitable means not shown, for example by a calibrated spring. This force is such that at each connection between a boss 31 and a conductive channel 4, the
  • the force will be 3.92 Newton (0.4 kgf ), for example
  • the duration of application of the ultrasound is, for information, between 0.1 and 0.5 seconds, for example 0.3 seconds.
  • each boss 3 is slightly flattened, and its lower end 33 has partially penetrated inside the material, in this case gold, constituting the conductive channel 4.
  • the malleable nature of the metals constituting both the boss 3 and the conductor 4 allows an interlocking of its two elements and a mechanical and metallurgical connection, which ensures ultimately good electrical conduction.
  • the final distance e between the chip 1 and the substrate 2 is of the order of 25 micrometers.
  • connection thus obtained is good, but however insufficient to ensure satisfactory mechanical strength of the chip 1 on the substrate 2.
  • the layer 8 could be added by impregnation, after assembly of the chip on the substrate.
  • the implementation of the invention is particularly advantageous when dealing with a multi-layer substrate co-cooked at low temperature, because this type of substrate has very good pla ⁇ éotti and, during cooking, is subjected to a relatively small and above all very regular retraction (dimensional shrinkage of the order of 12% linear).
  • the determination of the location of the holes which are intended to form the conductive channels, and their drilling in each of the sheets which will constitute the multi-layer substrate is made before baking taking into account the subsequent shrinkage which will take place during cooking. Tests have shown that this determination can be made with sufficient precision.
  • the differences in expansion between the material constituting the chip, in general silicon, and the material constituting the substrate, remain within limits compatible with good resistance over time and with the use of the chip / assembly. substrate.
  • the malleable nature of the constituent materials and boss 3 and / or conductive channels 4 is also a very favorable factor.
  • soft materials such as gold or silver are particularly advantageous for lining the conductive channels 4 of the substrate; to constitute the bosses 3, the use of materials other than gold can be envisaged, which have good metallurgical compatibility with the material of the channels 4, for example alloys based on lead and indium.
  • FIG. 8 illustrates the fact that, by applying the method according to the invention, the two faces of the substrate 2 with a set of chips 1, l ', 1 ".
  • the mounting of the chips can be done in the through conductive channels provided on the two faces 200 (upper face of the first layer 20a) and 201 (lower face of the last layer 20e).
  • the upper layer 20a has an opening 21. That This constitutes a cavity of dimensions slightly greater than that of the chip.
  • the assembly of the chip 1 is done by means of bosses 3 with the conductive channels 4 provided in the underlying layer 20b.
  • the chip is therefore located embedded in a cavity and thus perfectly integrated into the substrate. Of course, the cavity could pass through several layers, which would make it possible to drown relatively thick chips inside the substrate.

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  • Wire Bonding (AREA)

Abstract

According to the method, there is provided for the substrate (2) an assembly of conductor channels (4) which open out to a mounting face (200) whose geometrical distribution corresponds exactly to that of connection ranges provided on the active face (100) of the chip, and each of said ranges is lined with a pad (3) made of conductor material and whose diameter is slightly smaller than that of the channels (4). The assembly is carried out by pressing the chip on the substrate, each of the pads (3) penetrating partially in the conductor material of the channel (4) associated therewith by making an electric connection at that level.

Description

PROCEDE DE MONTAGE D'UNE PUCE A CIRCUIT INTEGRE SUR UN SUBSTRAT DE CABLAGE METHOD FOR MOUNTING A CHIP WITH INTEGRATED CIRCUIT ON A WIRING SUBSTRATE
La présente invention concerne un procédé de montage d'une puce à circuit intégré sur un substrat de câblage. Elle concerne aussi un ensemble constitué par l'assemblage de puces à circuit intégré sur un substrat de câblage.The present invention relates to a method for mounting an integrated circuit chip on a wiring substrate. It also relates to an assembly constituted by the assembly of integrated circuit chips on a wiring substrate.
L'assemblage à très haute densité de puces à circuit intégré complexe (pastilles de semi-conducteur) est devenu, au cours de ces dernières années, de plus en plus nécessaire dans de nombreux domaines, pour des raisons principalement de diminution de l'encom¬ brement et d'amélioration des performances.The very high density assembly of complex integrated circuit chips (semiconductor wafers) has become, in recent years, more and more necessary in many fields, for reasons mainly of decrease in the encom ¬ brement and performance improvement.
En ce qui concerne le substrat de câblage, qui réalise l 'inter-connection entre les différentes puces et circuits, la technique de co-cuisson à basse température de substrat multi- couches apparaît comme une excellente solution à de nombreux problèmes d'intégration, dans la mesure où la densité d'iπter- connexion peut être extrêmement élevée. A cet égard, il faut noter qu'il est possible de réaliser dans les couches constitutives du substrat des trous de très petit diamètre, qui sont remplis ensuite par sérigraphie d'un matériau conducteur tel que de l'or ou de l'argent. Dans toute la description et dans les revendications qui suivent, on désignera par le terme "canal conducteur" un tel trou rempli d'un matériau conducteur, canal qui est couramment dénommé "via". Le diamètre de ces canaux peut être de l'ordre de 90 à 110 micromètres, voire moins. La largeur des lignes et les dimensions des intervalles entre les lignes et les canaux sont du même ordre de grandeur.As far as the wiring substrate is concerned, which realizes the interconnection between the different chips and circuits, the low-temperature co-cooking technique of multilayer substrate appears to be an excellent solution to many integration problems, since the density of iπter- connexion can be extremely high. In this regard, it should be noted that it is possible to make holes in the constituent layers of the substrate of very small diameter, which are then filled by screen printing with a conductive material such as gold or silver. Throughout the description and in the claims which follow, the term "conductive channel" will designate such a hole filled with a conductive material, a channel which is commonly called "via". The diameter of these channels can be of the order of 90 to 110 micrometers, or even less. Line width and the dimensions of the intervals between the lines and the channels are of the same order of magnitude e.
Un autre avantage de ce type de substrat multi-couches est qu'il est facile d'augmenter le nombre de couches à des prix très raisonnables, pour intégrer des grilles de masse et d'alimentation, pour dessiner des pistes plus larges si nécessaire, et ce avec des conducteurs de faible résistivité. En outre, sa versatilité sur le plan de ses connexions et de son eπcapsulation, c'est-à-dire avec des puces montées des deux cδtés ou des puces montées d'un côté et des résistances de l'autre côté, et la possibilité d'y former des résistances par sérigraphie, sont encore des avantages supplémen¬ taires.Another advantage of this type of multi-layer substrate is that it is easy to increase the number of layers at very reasonable prices, to integrate mass and supply grids, to draw wider tracks if necessary, with conductors of low resistivity. In addition, its versatility in terms of its connections and its eπcapsulation, that is to say with chips mounted on both sides or chips mounted on one side and resistors on the other side, and the possibility to form resistances thereon by screen printing, are still additional advantages.
La co-cuissoπ des couches s'effectue à une température infé¬ rieure à 1100 à 1200° C, généralement de l'ordre de 850° C, qui est appelée "basse température" en opposition à la co-cuissoπ à haute température qui nécessite la mise en oeuvre de températures supérieures à 1500° C et oblige à utiliser des matériaux réfractai- res tels que le tungstène par exemple.The co-cuissoπ of the layers takes place at a temperature below 1100 to 1200 ° C, generally of the order of 850 ° C, which is called "low temperature" in opposition to the co-cuissoπ at high temperature which requires the use of temperatures above 1500 ° C and requires the use of refractory materials such as tungsten for example.
En ce qui concerne les technologies de connexion des puces sur le substrat, elles sont essentiellement au nombre de trois, briève¬ ment exposées ci-après.As regards the technologies for connecting the chips to the substrate, there are essentially three of them, briefly described below.
La première technique est celle du câblage traditionnel, désigné par le terme anglais " ire-boπdiπg", selon laquelle la liaison entre la puce et le substrat se fait par des fils en or ou en aluminium dont le diamètre est généralement de l'ordre de 25 micromètres. L'inconvénient majeur de cette technique est qu'il est nécessaire de disposer autour des puces de plages de câblage dont la surface relativement grande limite la densité de l'assemblage. Une autre technique d'assemblage est connue sous l'appelation "TAB", de l'anglais "tape automated bondiπg", qui pourrait se traduire en français par "liaison automatisée à rubans". Selon cette technique, les connexions sont réalisées en général par des rubans de cuivre maintenus sur un support polyimide sous forme de bandes. Cette technique a l'avantage de permettre un test facile des puces avant montage et est intéressante pour les grandes séries et éventuellement pour les puces de très haute complexité. Mais dans ce cas encore, il faut prévoir un zone relativement importante autour des puces pour permettre le raccordement des rubans sur le substrat.The first technique is that of traditional wiring, designated by the English term "ire-boπdiπg", according to which the connection between the chip and the substrate is made by gold or aluminum wires whose diameter is generally of the order of 25 micrometers. The major drawback of this technique is that it is necessary to have wiring areas around the chips whose relatively large surface limits the density of the assembly. Another assembly technique is known by the name "TAB", from the English "tape automated bondiπg", which could be translated into French by "automated link to ribbons". According to this technique, the connections are generally made by copper tapes held on a polyimide support in the form of strips. This technique has the advantage of allowing easy testing of chips before mounting and is advantageous for large series and possibly for very high complexity chips. But in this case too, a relatively large area must be provided around the chips to allow the ribbons to be connected to the substrate.
Une troisième technique, connue par l'homme du métier sous la dénomination anglaise "flip-chip", consiste à former des petits bossages métalliques, qui forment des plots de contact, sur les plages de connexion situées sur les faces actives des puces. Les bossages sont généralement en or ou dans un alliage à base de plomb ou d'iπdium. Les bossages sont ensuite reportés à l'envers sur le substrat, par soudure directe sur une zone métallisée. prévue sur le substrat. Ce procédé a été développé dans les années 1970 mais son développement a été limité à cause des difficultés très importantes qu'il présente. 11 faut en effet une grande régularité dans la fabrication des bossages, dans le positionnement des puces et dans le processus de refusion assurant la soudure. Les soudures, une fois réalisées, sont très sujettes à des fatigues thermiques lors des cycles de fonctionnement / arrêt des puces, et même simplement lors des cycles thermiques liés à l'environnement. En revanche, si ces difficultés sont surmontées, les performances d'une telle technologie en densité d'intégration et en vitesse de signaux, sont maximales. D'autres avantages de cette technique sont qu'elle offre la possibilité d'obtenir des entrées et des sorties surfaciques et non périphériques comme dans les deux techniques exposées précédemment. Le gain en densité du "flip-chip" par rapport au câblage traditionnel ou au TAB, se situe dans un rapport de l'ordre de 1,2 à 1,5, ce rapport dépendant bien entendu des caractéris¬ tiques dimensionπelles des puces.A third technique, known to those skilled in the art under the English name "flip-chip", consists of forming small metal bosses, which form contact pads, on the connection pads located on the active faces of the chips. The bosses are generally made of gold or of an alloy based on lead or iπdium. The bosses are then transferred upside down on the substrate, by direct welding on a metallized area. provided on the substrate. This process was developed in the 1970s but its development has been limited because of the very significant difficulties it presents. It is indeed necessary a great regularity in the manufacture of the bosses, in the positioning of the chips and in the reflow process ensuring the welding. The welds, once made, are very subject to thermal fatigue during the operating / stopping cycles of the chips, and even simply during the thermal cycles linked to the environment. On the other hand, if these difficulties are overcome, the performance of such a technology in terms of integration density and signal speed is maximum. Other advantages of this technique are that it offers the possibility of obtaining surface and non-peripheral inputs and outputs as in the two techniques described above. The gain in density of the "flip-chip" compared to traditional wiring or TAB, is in a ratio of the order of 1.2 to 1.5, this ratio depending of course on the dimensional characteristics of the chips.
L'idée générale à la base de la présente invention est de remettre la technologie du "flip-chip" à l'ordre du jour, sous un nouvel angle, en l'appliquant à un substrat dont les canaux conducteurs (vias) débouchent sur l'une au moins des faces du substrat, ce qui est le cas notamment pour les substrats obtenus par co-cuisson à basse température.The general idea underlying the present invention is to put the "flip-chip" technology back on the agenda, from a new angle, by applying it to a substrate whose channels conductors (vias) open on at least one of the faces of the substrate, which is the case in particular for the substrates obtained by co-cooking at low temperature.
Un tel substrat peut en effet inclure une iπter-coππexioπ complexe et faire partie intégrante d'un encapsulage complet, ce qui permet d'obtenir à moindre coût des performances maximales. Un tel substrat présente en outre une excellente planéité, facilement contrôlable, ce qui le rend compatible avec un procédé requérant de hautes précisions dimeπsioπnelles. De plus, il est possible de réaliser des canaux conducteurs de très petit diamètre (inférieur à 100 micromètres), très rapprochés les uns des autres (avec un entre-axe inférieur à 200 micromètres) , de qualité et de précision de positionnement excellentes. Ceci permet donc d'obtenir une densité élevée car on atteint le même ordre de grandeur géométrique que celle des plages d'entrées et de sorties des puces elles-mêmes. Enfin, il faut noter que le matériau métallique constitutif des "vias" peut être modifié si bien qu'il existe une grande latitude de choix en fonction des caractéristiques non seulement métal¬ lurgiques mais aussi mécaniques du matériau.Such a substrate can indeed include a complex iπter-coππexioπ and be an integral part of a complete encapsulation, which allows maximum performance to be obtained at lower cost. Such a substrate also has excellent flatness, easily controllable, which makes it compatible with a process requiring high dimeπsioπnelles precision. In addition, it is possible to produce conductive channels of very small diameter (less than 100 micrometers), very close to each other (with a center distance less than 200 micrometers), of excellent positioning quality and precision. This therefore makes it possible to obtain a high density since the same geometric order of magnitude is reached as that of the input and output ranges of the chips themselves. Finally, it should be noted that the metallic material constituting the "vias" can be modified so that there is a large latitude of choice as a function of the characteristics not only of metal but also mechanical properties of the material.
Partant de l'ensemble de ces considérations, il est apparu au demandeur qu'il était possible d'assembler les puces sur des substrats à "vias" débouchants en mettant en oeuvre la technique du "flip-chip" directement sur ces "vias".Based on all of these considerations, it appeared to the applicant that it was possible to assemble the chips on substrates with "vias" opening out by implementing the technique of "flip-chip" directly on these "vias" .
L'invention concerne donc un procédé de montage d'une puce 'à circuit intégré sur un susbtrat de câblage dont l'une au moins des faces présente un ensemble de canaux conducteurs débouchants, par exemple cylindriques, ce substrat étant avantageusement, mais non nécessairement, un substrat de type multi-couches qui, de préfé¬ rence, est obtenu par le procédé de co-cuissoπ à basse température. Le procédé se caractérise par les étapes suivantes : a) on réalise le substrat de telle manière que l'emplacement desdits canaux conducteurs coïncide rigoureusement avec celui des plages conductrices disposées sur la face active de la puce et destinées à sa connexion électrique avec le substrat ; b) on dépose sur chacune de ces plages conductrices un bossage approximativement hémisphérique dont le diamètre est légèrement inférieur aux dimensions de la section transversale des canaux conducteurs, en l'occurence à leur diamètre si ces canaux sont cylindriques ; c) on positionne la puce sur le substrat, face active tournée vers la face de montage, de telle façon que chaque bossage se place en appui sur l'extrémité débouchante d'un canal ; d) on applique une pression tendant à rapprocher la puce du substrat de manière à faire pénétrer partiellement chacun des bossages dans la matière conductrice du canal qui lui est associé en réalisant une liaison électrique à ce niveau. Lorsqu'on a affaire à un substrat du type multi-couches, on peut avantageusement monter la puce à l'intérieur d'une ouverture ménagée dans au moins l'une des couches constitutives du substrat, en la fixant à la couche sous-jacente ; cet arrangement permet en effet de noyer la puce à l'intérieur du substrat. Avantageusement, la mise en oeuvre de l'étape c), au cours de laquelle on applique une pression tendant à rapprocher la puce du substrat, est réalisée avec application de chaleur et d'ultra-soπs.The invention therefore relates to a method for mounting an integrated circuit chip on a wiring substrate, at least one of the faces of which has a set of through conductive channels, for example cylindrical, this substrate being advantageously, but not necessarily , a multi-layer type substrate which, preferably, is obtained by the co-cuissoπ process at low temperature. The method is characterized by the following stages: a) the substrate is produced in such a way that the location of said conductive channels strictly coincides with that of the conductive pads arranged on the active face of the chip and intended for its electrical connection with the substrate; b) an approximately hemispherical boss is deposited on each of these conductive pads, the diameter of which is slightly less than the dimensions of the cross section of the conductive channels, in this case their diameter if these channels are cylindrical; c) the chip is positioned on the substrate, active side facing the mounting face, so that each boss is placed in abutment on the through end of a channel; d) applying a pressure tending to bring the chip closer to the substrate so as to partially penetrate each of the bosses in the conductive material of the channel associated with it by making an electrical connection at this level. When dealing with a substrate of the multi-layer type, it is advantageous to mount the chip inside an opening formed in at least one of the constituent layers of the substrate, by fixing it to the underlying layer. ; this arrangement makes it possible to drown the chip inside the substrate. Advantageously, the implementation of step c), during which a pressure is applied which tends to bring the chip closer to the substrate, is carried out with the application of heat and ultra-soπs.
La force développée au niveau de chaque liaison bossage / canalThe force developed at each boss / channel link
- - -2 -2 conducteur est de préférence comprise entre 9,8.10 et 29,4.10 Newton (10 et 30 gf).- - -2 -2 conductor is preferably between 9.8.10 and 29.4.10 Newton (10 and 30 gf).
Pour réaliser les parties conductrices en forme de bossage, on opère de préférence à partir d'un fil dont on fond l'extrémité en lui donnant la forme d'une boule que l'on dépose sur la puce, après quoi on sectionne le fil au ras de la boule. Cette technique est directement dérivée de la technique de câblage traditionnelle dans laquelle la liaison de la puce avec le substrat se fait par un fil dont une extrémité a la forme d'une boule déposée sur la puce et l'autre, en forme de croissant, est déposée sur le substrat. Une telle technique est usuellement désignée sous la dénomination anglaise "ball-boπding", qui pourrait se traduire par "liaison à boule". Il est ainsi possible d'utiliser des puces standard, sans préparation spéciale, la pose des bossages pouvant se faire à la demande directement sur les puces.To make the boss-shaped conductive parts, it is preferable to operate from a wire, the end of which is melted, giving it the shape of a ball which is deposited on the chip, after which the wire is cut. flush with the ball. This technique is directly derived from the traditional wiring technique in which the connection of the chip with the substrate is made by a wire of which one end has the shape of a ball deposited on the chip and the other, in the shape of a crescent, is deposited on the substrate. Such a technique is usually designated by the English name "ball-boπding", which could be translated as "binding to ball ". It is thus possible to use standard chips, without special preparation, the fitting of bosses can be done on demand directly on the chips.
Avantageusement, les bossages ont un diamètre moyen compris entre 50 et 100 micromètres, tandis que les canaux conducteurs ont un diamètre compris entre 80 et 150 micromètres.Advantageously, the bosses have an average diameter between 50 and 100 micrometers, while the conductive channels have a diameter between 80 and 150 micrometers.
La liaison mécanique entre la puce et le substrat, qui résulte de la pénétration partielle des bossages dans le matériau des canaux conducteurs, est généralement suffisante pour que l'ensemble puce / substrat puisse être utilisé dans des conditions normales. 11 est possible et avantageux, pour améliorer la liaison mécanique et/ou la qualité du transfert thermique entre la puce et le substrat, d'interposer entre ces deux éléments un composé organique ; celui-ci pourrait être étalé entre les deux faces en regard au cours de l'application de la pression à l'étape c) ; il pourrait aussi être appliqué après assemblage par imprégnation.The mechanical connection between the chip and the substrate, which results from the partial penetration of the bosses into the material of the conductive channels, is generally sufficient for the chip / substrate assembly to be able to be used under normal conditions. It is possible and advantageous, to improve the mechanical connection and / or the quality of the heat transfer between the chip and the substrate, to interpose between these two elements an organic compound; this could be spread between the two opposite faces during the application of the pressure in step c); it could also be applied after assembly by impregnation.
En outre, l'invention permet d'obtenir un montage dans lequel la face active de la puce est très faiblement écarté de la face de montage du substrat, ce qui facilite encore la dissipation thermique de la puce vers le substrat.In addition, the invention makes it possible to obtain a mounting in which the active face of the chip is very slightly spaced from the mounting face of the substrate, which further facilitates heat dissipation from the chip to the substrate.
L'invention permet enfin de monter des puces sur les deux faces du substrat, ce qui permet en théorie de doubler la densité d'intégration.The invention finally makes it possible to mount chips on both sides of the substrate, which in theory makes it possible to double the integration density.
L'invention concerne aussi un ensemble constitué par l'assem- blage de puces à circuit intégré sur un substrat de câblage.The invention also relates to an assembly constituted by the assembly of integrated circuit chips on a wiring substrate.
Cet ensemble est remarquable par le fait que la face active des puces est garnie d'un ensemble de bossages conducteurs, de forme approximativement hémisphérique, qui sont directement et par¬ tiellement enfoncés chacun dans un canal rempli d'un matériau con- ducteur (malléable) et débouchant sur l'une des faces du substrat. De préférence, cet ensemble comprend un composé organique intercalé entre les deux faces en regard des puces et du substrat ; ce composé assure, ou du moins consolide, la liaison mécanique puces/substrat tout en favorisant le transfert de la chaleur des puces au substrat. Dans un mode de réalisation préférentiel, le substrat est un substrat en céramique multicouches obtenu par co-cuisson à basse température.This assembly is remarkable by the fact that the active face of the chips is furnished with a set of conductive bosses, of approximately hemispherical shape, which are directly and partially inserted each in a channel filled with a conductive material (malleable ) and opening onto one of the faces of the substrate. Preferably, this assembly comprises an organic compound interposed between the two faces opposite the chips and the substrate; this compound ensures, or at least consolidates, the mechanical bond between chips and substrate while promoting the transfer of heat from the chips to the substrate. In a preferred embodiment, the substrate is a multilayer ceramic substrate obtained by co-firing at low temperature.
D'autres caractéristiques et avantages de l'invention apparaî- tront de la description et des dessins annexés qui en présentent, à titre d'exemples non limitatifs, des modes de réalisation préférentiels.Other characteristics and advantages of the invention will appear from the description and the appended drawings which present, by way of nonlimiting examples, preferred embodiments.
Sur ces dessins :In these drawings:
- la figure 1 est une vue de détail à grande échelle illus- trant l'opération de dépδt d'un bossage conducteur sur la face active d'une puce ;- Figure 1 is a detail view on a large scale illustrating the operation of depositing a conductive boss on the active face of a chip;
- la figure 2 est une vue générale illustrant le principe d'assemblage de la puce au substrat ;- Figure 2 is a general view illustrating the principle of assembly of the chip to the substrate;
- la figure 3 montre l'ensemble puce / substrat après assemblage ;- Figure 3 shows the chip / substrate assembly after assembly;
- la figure 4 est une vue de détail montrant la liaison du bossage de la figure 1 avec le canal conducteur associé du substrat ;- Figure 4 is a detail view showing the connection of the boss of Figure 1 with the associated conductive channel of the substrate;
- la figure 5 est une vue partielle d'un assemblage similaire entre une puce et un substrat, dans lequel est prévue l'interposi¬ tion d'un composé organique ;- Figure 5 is a partial view of a similar assembly between a chip and a substrate, in which the interposition of an organic compound is provided;
- la figure 6 est une vue de dessus partielle à grande échelle d'un substrat présentant un certain nombre de canaux conducteurs débouchants ; - la figure 7 est une vue de la face active d'une puce, sur laquelle sont disposés des bossages conducteurs dont l'emplacement coïncide avec les canaux débouchants du substrat de la figure 6 ;- Figure 6 is a partial top view on a large scale of a substrate having a number of through conductive channels; - Figure 7 is a view of the active face of a chip, on which are arranged conductive bosses whose location coincides with the through channels of the substrate of Figure 6;
- les figures 8 et 9 sont des vues partielles destinées à montrer respectivement les possibilités de montage de puces sur les deux faces du substrat, et de montage d'une puce dans une ouverture de la couche externe d'un substrat multi-couches.- Figures 8 and 9 are partial views intended to show respectively the possibilities of mounting chips on the two faces of the substrate, and mounting a chip in an opening of the outer layer of a multi-layer substrate.
Sur la vue partielle de la figure 1 , on a désigné par la référence 1 une puce à circuit intégré, celle-ci étant vue de côté. Sur l'une des faces 100 de la puce, qui par la suite sera appelée "face active", sont prévues un certain nombre de plages de câblage métallisées 10, comme cela est bien connu. Ces plages, qui sont destinées à assurer la connexion électrique de la puce avec l'extérieur, sont disposées selon une certaine répartition géométrique.In the partial view of FIG. 1, we have designated by reference 1 an integrated circuit chip, this being seen from the side. On one of the faces 100 of the chip, which will hereinafter be called "active face", a number of metallized wiring areas 10 are provided, as is well known. These areas, which are intended to ensure the electrical connection of the chip with the outside, are arranged in a certain geometric distribution.
Elles sont généralement situées à la périphérie de la puce. Dans le* procédé selon l'invention, le substrat est tout d'abord conçu et fabriqué de telle manière que les canaux conduc¬ teurs qui débouchent sur leur face de montage aient rigoureusement la même répartition géométrique que celles des plages métallisées garnissant la (ou les) puce(s) que le substrat doit recevoir.They are generally located at the periphery of the chip. In the * method according to the invention, the substrate is first of all designed and manufactured in such a way that the conduc¬ tor channels which open onto their mounting face have rigorously the same geometric distribution as those of the metallized areas lining the (or the) chip (s) that the substrate must receive.
Ensuite, on dépose sur chacune des plages 10 un plot coπduc- teur 3. Cette opération se fait avantageusement par un procédé et à l'aide d'un dispositif déjà connus, utilisés dans la technique de câblage traditionnel à fil ("ball-bonding"). Pour cela, la puce est placée sur un support chauffant, face active 100 tournée vers le haut. On utilise un outil capillaire en céramique qui est mis en vibration au moyen d'un générateur ultrasonique via un transducteur approprié. Le capillaire est un tube dans lequel passe un fil d'or de faible diamètre, par exemple de 17 micromètres. L'extrémité du fil est tout d'abord mise en fusion, ce qui a pour effet de former une boule 31 de forme générale hémisphérique. Ensuite cette boule est appliquée sous pression sur la plage 10, avec émission de chaleur et d'ultra-sons, de sorte qu'elle se fixe sur la plage 10. L'outil est ensuite retiré et le fil 30 sectionné au ras de la boule. On obtient ainsi un bossage. A titre indicatif, son diamètre moyen ^ est de l'ordre de 60 micromètres et sa hauteur _h_ de l'ordre de 50 micromètres.Next, a coπductor pad 3 is deposited on each of the pads 10. This operation is advantageously done by a method and using a device already known, used in the traditional wire cabling technique ("ball-bonding" "). For this, the chip is placed on a heating support, active face 100 facing upwards. A ceramic capillary tool is used which is vibrated by means of an ultrasonic generator via an appropriate transducer. The capillary is a tube through which passes a small diameter gold wire, for example 17 micrometers. The end of the wire is first of all fused, which has the effect of forming a ball 31 of generally hemispherical shape. Then this ball is applied under pressure on track 10, with emission of heat and ultrasound, so that it is fixed on track 10. The tool is then removed and the wire 30 sectioned flush with the ball. This gives a boss. As an indication, its average diameter ^ is of the order of 60 micrometers and its height _h_ of the order of 50 micrometers.
La figure 7 montre la disposition d'un ensemble de bossages 31 sur la face active de la puce 1. Il s'agit par exemple d'une puce à contour rectangulaire de dimensions 5 mm x 4 mm.FIG. 7 shows the arrangement of a set of bosses 31 on the active face of the chip 1. This is for example a chip with rectangular outline of dimensions 5 mm x 4 mm.
Comme déjà dit plus haut, l'emplacement des plages 10 ainsi que des bossages 3 garnissant ces plages, ont une répartition identique à celle des canaux conducteurs qui débouchent dans la face de montage 200 du substrat 2 sur lequel doit être fixée la puce 1. Le substrat 2 est un substrat multi-couches. Le substrat est composé de quatre feuilles de céramique référencées 20a, 20b, 20c, 20d, qui forment un ensemble monobloc à la suite d'une cuisson dite à basse température (de l'ordre de 850° C). Comme cela est bien connu, chaque couche présente un certain nombre de trous cylin¬ driques qui les traversent. Ces trous 400, de très petit diamètre, de l'ordre de 90 micromètres par exemple, sont ensuite remplis par sérigraphie d'un matériau conducteur, par exemple d'or, ce qui permet d'obtenir des canaux conducteurs 4 (voir figure 4). Une sérigraphie de pistes conductrices, par exemple en or, est ensuite réalisée sur chacune des couches. L'empilage et la cuisson ultérieurs permettront de relier les puces entre elles (ou avec l'extérieur) par l'intermédiaire des canaux conducteurs ("vias") et des pistes conductrices, en passant le plus souvent par les couches internes.As already said above, the location of the pads 10 as well as the bosses 3 lining these pads have a distribution identical to that of the conductive channels which open into the mounting face 200 of the substrate 2 on which the chip 1 is to be fixed. The substrate 2 is a multi-layer substrate. The substrate is composed of four ceramic sheets referenced 20a, 20b, 20c, 20d, which form a one-piece assembly following a so-called low temperature firing (of the order of 850 ° C). As is well known, each layer has a certain number of cylindrical holes which pass through them. These holes 400, of very small diameter, of the order of 90 micrometers for example, are then filled by screen printing with a conductive material, for example gold, which makes it possible to obtain conductive channels 4 (see FIG. 4 ). A screen printing of conductive tracks, for example in gold, is then carried out on each of the layers. The subsequent stacking and baking will allow the chips to be linked together (or with the outside) via conductive channels ("vias") and conductive tracks, most often passing through the internal layers.
La figure 6 représente les trous qui débouchent sur l'une des faces externes du substrat, en l'occurence, la face de montage 200 qui est destinée à recevoir la puce 1. La disposition de ces canaux conducteurs correspond rigoureusement à celle des bossages 3 de sorte que, si on positionne la puce 1 sur le substrat, sa face active 100 tournée vers la face de montage 200, chaque bossage 3 se trouve positionné exactement en vis-à-vis d'un canal conducteur 4. Ainsi, si on observe les figures 6 et 7, le bossage référencé 32, après retournement de la puce 1 sur le substrat, est destiné à venir en correspondance avec le canal conducteur repéré 42. A la figure 6, le contour en traits interrompus C_ représente la puce 1 lorsqu'elle est positionnée sur le substrat 2. On remarquera qu'aux quatre angles de ce contour, sont prévus des canaux conducteurs 40. Ceux-ci n'ont pas de fonction dans le câblage de l'ensemble, mais servent au positionnement correct, grâce à des moyens de détection appropriés, de la puce sur le substrat en vue de l'opération d'assemblage, opération illustrée à la figure 2.FIG. 6 represents the holes which open onto one of the external faces of the substrate, in this case, the mounting face 200 which is intended to receive the chip 1. The arrangement of these conductive channels corresponds strictly to that of the bosses 3 so that, if the chip 1 is positioned on the substrate, its active face 100 facing the mounting face 200, each boss 3 is positioned exactly opposite a conductive channel 4. Thus, if one observe FIGS. 6 and 7, the boss referenced 32, after turning the chip 1 over on the substrate, is intended to come into correspondence with the conductive channel marked 42. In FIG. 6, the contour in broken lines C_ represents the chip 1 when it is positioned on the substrate 2. It will be noted that at four angles of this contour are provided for conducting channels 40. These have no function in the wiring of the assembly, but serve for the correct positioning, by means of appropriate detection means, of the chip on the substrate for the assembly operation, operation illustrated in FIG. 2.
Traditionnellement, les plages de connexion 10 (et, corrélati¬ vement, les bossages 3 dont ces plages sont pourvues) sont disposées en périphérie de la puce.Traditionally, the connection pads 10 (and, correlatively, the bosses 3 with which these pads are provided) are arranged at the periphery of the chip.
Il est possible toutefois d'envisager, et ceci devient particu- lierement intéressant grâce à l'invention, de prévoir des plages de connexion en certaines zones de la puce éloignées de ses bords.It is however possible to envisage, and this becomes particularly interesting thanks to the invention, to provide connection pads in certain areas of the chip remote from its edges.
Ceci est symbolisé à la figure 7 par l'ensemble de bossages référencé 35 (représentés en traits interrompus) qui sont disposés dans la région centrale de la puce 1. Un ensemble correspondant 45 de canaux débouchants est bien entendu prévu sur le substrat 2 (figure 6).This is symbolized in FIG. 7 by the set of bosses referenced 35 (shown in dashed lines) which are arranged in the central region of the chip 1. A corresponding set 45 of through channels is of course provided on the substrate 2 (figure 6).
Un tel arrangement permet d'obtenir une interconnexion surfacique, et non plus seulement périphérique, ce qui permet d'améliorer la compacité du montage. Le substrat 2 est mis en place sur un socle chauffant 5. Les moyens de chauffage, non représentés, sont par exemple des résistan¬ ces électriques intégrées à l'intérieur du socle 5. Ils sont adaptés pour développer, au niveau de la liaison entre le bossage 3 et les canaux conducteurs 4, une température comprise en 100 et 200° C, par exemple de 150° C.Such an arrangement makes it possible to obtain a surface interconnection, and no longer only a peripheral one, which makes it possible to improve the compactness of the assembly. The substrate 2 is placed on a heating base 5. The heating means, not shown, are for example electrical resistors integrated inside the base 5. They are adapted to develop, at the level of the connection between the boss 3 and the conductive channels 4, a temperature between 100 and 200 ° C, for example 150 ° C.
La puce 1 est positionnée correctement sur le substrat 2, ce positionnement étant aidé grâce à des moyens détecteurs non représentés faisant référence aux canaux repères 40.The chip 1 is positioned correctly on the substrate 2, this positioning being helped by means of detector means not shown referring to the reference channels 40.
Le dispositif d'assemblage sommairement représenté à la figure 2 comporte un outil presseur 6. 11 s'agit par exemple d'une tige de céramique dont l'extrémité est pourvue d'un plateau presseur 60, par exemple discoïde, venant en appui contre la région centrale de la puce 1. Un générateur d'ultra-sons 70 permet, par l'inter- édiaire d'un organe transducteur 7, de faire vibrer l'outil 6 à une fréquence ultrasonique. Cette vibration est figurée par la double flèche G. La vibration est de préférence multidirection- nelle. Elle présente par exemple deux composantes perpendiculaires situées dans le plan horizontal, c'est-à-dire dans le plan de la puce (l'une £ dans le plan de la feuille de dessins, et l'autre perpendiculaire au plan de la feuille, en référence à la figure 2). Elle se fait de préférence à une puissance comprise entre 5 et 15 Watts, par exemple de l'ordre de 10 Watts, et à une fréquence comprise entre 40 et 80 kHz, par exemple de 60 kHz. Simultanément, une force est appliquée à l'outil 6 de manière à exercer sur la puce 1 une pression tendant à la rapprocher du substrat 2. La force _ est générée par des moyens appropriés non représentés, par exemple par un ressort taré. Cette force est telle qu'au niveau de chaque liaison entre un bossage 31 et un canal conducteur 4, laThe assembly device roughly shown in Figure 2 includes a pressing tool 6. It is for example a ceramic rod whose end is provided with a pressing plate 60, for example discoid, abutting against the central region of the chip 1. An ultrasonic generator 70 makes it possible, via the ediary of a transducer member 7, to vibrate the tool 6 at an ultrasonic frequency. This vibration is represented by the double arrow G. The vibration is preferably multidirectional. It has for example two perpendicular components located in the horizontal plane, that is to say in the plane of the chip (one £ in the plane of the sheet of drawings, and the other perpendicular to the plane of the sheet , with reference to Figure 2). It is preferably done at a power between 5 and 15 Watts, for example of the order of 10 Watts, and at a frequency between 40 and 80 kHz, for example 60 kHz. Simultaneously, a force is applied to the tool 6 so as to exert on the chip 1 a pressure tending to bring it closer to the substrate 2. The force is generated by suitable means not shown, for example by a calibrated spring. This force is such that at each connection between a boss 31 and a conductive channel 4, the
-2 -2 force appliquée soit comprise entre 9,8.10 et 29,4.10 Newton-2 -2 applied force is between 9.8.10 and 29.4.10 Newton
(10 et 30 gf), par exemple de 19,6.10"2 Newton (20 gf). Ainsi, si le nombre de bossages dont est munie la puce est de vingt, la force sera de 3,92 Newton (0,4 kgf), par exemple. La durée d'application des ultra-sons est, à titre indicatif comprise entre 0,1 et 0,5 seconde ; il est par exemple de 0,3 seconde.(10 and 30 gf), for example 19.6.10 "2 Newton (20 gf). Thus, if the number of bosses with which the chip is provided is twenty, the force will be 3.92 Newton (0.4 kgf ), for example The duration of application of the ultrasound is, for information, between 0.1 and 0.5 seconds, for example 0.3 seconds.
A l'issue de cette opération, comme cela est visible à la figure 4, chaque bossage 3 s'est légèrement aplati, et son extrémité basse 33 a partiellement pénétré à l'intérieur du matériau, en l'occurence de l'or, constitutif du canal conducteur 4. A cet égard, il faut noter que le caractère malléable des métaux constituant aussi bien le bossage 3 que le conducteur 4, permet une imbrication de ses deux éléments et une liaison d'ordre mécanique et métallurgique, ce qui assure finalement une bonne conduction électrique.At the end of this operation, as can be seen in FIG. 4, each boss 3 is slightly flattened, and its lower end 33 has partially penetrated inside the material, in this case gold, constituting the conductive channel 4. In this regard, it should be noted that the malleable nature of the metals constituting both the boss 3 and the conductor 4, allows an interlocking of its two elements and a mechanical and metallurgical connection, which ensures ultimately good electrical conduction.
Après écrasement, le diamètre moyen A__ du bossage 3 a légère¬ ment augmenté ; à titre indicatif ce diamètre est passé de A = 60 micromètres, à A' = 80 micromètres. L'écartement final e entre la puce 1 et le substrat 2 est de l'ordre de 25 micromètres.After crushing, the average diameter A__ of the boss 3 has slightly increased; as an indication, this diameter increased from A = 60 micrometers, to A '= 80 micrometers. The final distance e between the chip 1 and the substrate 2 is of the order of 25 micrometers.
Généralement, si le nombre de connexions est assez élevé, la liaison ainsi obtenue est bonne, mais cependant insuffisante pour assurer une tenue mécanique satisfaisante de la puce 1 sur le substrat 2.Generally, if the number of connections is high enough, the connection thus obtained is good, but however insufficient to ensure satisfactory mechanical strength of the chip 1 on the substrate 2.
Comme cela est illustré à la figure 5, il est par conséquent souhaitable d'améliorer la qualité de la liaison entre la puce et le substrat, en prévoyant d'interposer entre la puce et le substrat une couche d'un matériau organique pouvant jouer le rôle d'une colle. Cette couche, qui est référencée 8 à la figure 5, peut être placée avant pressage en certaines zones de la face de montage sur le substrat.As illustrated in FIG. 5, it is therefore desirable to improve the quality of the connection between the chip and the substrate, by making provision for interposing between the chip and the substrate a layer of organic material capable of playing the role of an adhesive. This layer, which is referenced 8 in FIG. 5, can be placed before pressing in certain zones of the mounting face on the substrate.
Elle a aussi pour effet de faciliter l'échange thermique entre la puce et le substrat, ceci d'autant mieux que l'écartement e_ entre ces deux éléments est extrêmement faible.It also has the effect of facilitating the heat exchange between the chip and the substrate, this all the better since the spacing e_ between these two elements is extremely small.
Dans une variante de mise en oeuvre, la couche 8 pourrait être rapportée par imprégnation, après assemblage de la puce sur le subtrat.In an implementation variant, the layer 8 could be added by impregnation, after assembly of the chip on the substrate.
Enfin, après montage, il est possible, si on le souhaite, de protéger la puce en la recouvrant d'une goutte de résine organique. La mise en oeuvre de l'invention est particulièrement avanta¬ geuse quand on a affaire à un substrat multi-couches co-cuit à basse température, car ce type de substrat présente une très bonne plaπéité et, en cours de cuisson, est soumis à une rétraction relativement faible et surtout très régulière (retrait dimensioπnel de l'ordre de 12 % linéaire). Bien entendu, la détermination de l'emplacement des trous qui sont destinés à former les canaux conducteurs, et leur perçage dans chacune des feuilles qui consti¬ tueront le substrat multi-couches, est fait avant cuisson en tenant compte du retrait ultérieur qui aura lieu en cours de cuisson. Des essais ont montré que cette détermination pouvait se faire avec une précision suffisante. De même, les différences de dilatation entre le matériau constitutif de la puce, en général du silicium, et le matériau constitutif du substrat, demeurent dans des limites compatibles avec une bonne tenue dans le temps et à l'usage de l'assemblage puce / substrat. A cet égard, le caractère malléable des matériaux constitutifs et bossage 3 et/ou des canaux conducteurs 4, est également un facteur très favorable.Finally, after assembly, it is possible, if desired, to protect the chip by covering it with a drop of organic resin. The implementation of the invention is particularly advantageous when dealing with a multi-layer substrate co-cooked at low temperature, because this type of substrate has very good plaπéité and, during cooking, is subjected to a relatively small and above all very regular retraction (dimensional shrinkage of the order of 12% linear). Of course, the determination of the location of the holes which are intended to form the conductive channels, and their drilling in each of the sheets which will constitute the multi-layer substrate, is made before baking taking into account the subsequent shrinkage which will take place during cooking. Tests have shown that this determination can be made with sufficient precision. Likewise, the differences in expansion between the material constituting the chip, in general silicon, and the material constituting the substrate, remain within limits compatible with good resistance over time and with the use of the chip / assembly. substrate. In this regard, the malleable nature of the constituent materials and boss 3 and / or conductive channels 4 is also a very favorable factor.
Comme déjà dit, des matériaux mous tels que l'or ou l'argent sont particulièrement intéressants pour garnir les canaux conducteurs 4 du substrat ; pour constituer les bossages 3, l'usage de matériaux autre que de l'or, peut être envisagé,qui ont une bonne compatibilité métallurgique avec le matériau des canaux 4, par exemple des alliages à base de plomb et d'indium.As already said, soft materials such as gold or silver are particularly advantageous for lining the conductive channels 4 of the substrate; to constitute the bosses 3, the use of materials other than gold can be envisaged, which have good metallurgical compatibility with the material of the channels 4, for example alloys based on lead and indium.
La figure 8 illustre le fait qu'il est possible de garnir, en appliquant le procédé selon l'invention, les deux faces du substrat 2 d'un ensemble de puces 1, l', 1". Pour cela, le montage des puces peut se faire dans les canaux conducteurs débouchants prévus sur les deux faces 200 (face supérieure de la première couche 20a) et 201 (face inférieure de la dernière couche 20e). A la figure 9, la couche supérieure 20a présente une ouverture 21. Celle-ci constitue une cavité de dimensions légèrement supérieures à celle de la puce. L'assemblage de la puce 1 se fait par l'intermédiaire de bossages 3 avec les canaux conducteurs 4 prévus dans la couche sous-jacente 20b. La puce se trouve donc noyée dans une cavité et ainsi parfaitement intégrée au substrat. Bien entendu, la cavité pourrait traverser plusieurs couches, ce qui permettrait de noyer à l'intérieur du substrat des puces relativement épaisses. FIG. 8 illustrates the fact that, by applying the method according to the invention, the two faces of the substrate 2 with a set of chips 1, l ', 1 ". For this, the mounting of the chips can be done in the through conductive channels provided on the two faces 200 (upper face of the first layer 20a) and 201 (lower face of the last layer 20e). In FIG. 9, the upper layer 20a has an opening 21. That This constitutes a cavity of dimensions slightly greater than that of the chip. The assembly of the chip 1 is done by means of bosses 3 with the conductive channels 4 provided in the underlying layer 20b. The chip is therefore located embedded in a cavity and thus perfectly integrated into the substrate. Of course, the cavity could pass through several layers, which would make it possible to drown relatively thick chips inside the substrate.

Claims

REVENDICATIONS
1. Procédé de montage d'une puce à circuit intégré (1) sur un substrat de câblage (2) dont l'une au moins (200) des faces - dite face de montage - présente un ensemble de canaux conducteurs débouchants (4) par exemple cylindriques, selon lequel : a) on réalise le susbtrat (2) de telle manière que l'empla¬ cement desdits canaux conducteurs (4) coïncide rigoureusement avec celui des plages conductrices (10) disposées sur la face active (100) de la puce (1) et destinées à sa connexion électrique avec le substrat (2) ; b) on dépose sur chacune de ces plages conductrices (10) un bossage (3) approximativement hémisphérique dont le diamètre (A) est légèrement inférieur aux dimensions de la section transversale des canaux conducteurs (4), en l'occurence à leur diamètre (B) si ces canaux sont cylindriques ; c) on positionne la puce (1) sur le substrat (2), face active (100) tournée vers la face de montage (200), de telle façon que chaque bossage (3) se place en appui sur l'extrémité débouchante d'un canal (4) ; d) on applique une pression (F) tendant à rapprocher la puce (1) du substrat (2) de manière à faire pénétrer partiellement chacun des bossages (3) dans la matière conductrice du canal (4) qui lui est associé en réalisant une liaison électrique à ce niveau.1. Method for mounting an integrated circuit chip (1) on a wiring substrate (2) of which at least one (200) of the faces - called mounting face - has a set of through conductive channels (4) for example cylindrical, according to which: a) the substrate (2) is produced in such a way that the location of said conductive channels (4) coincides strictly with that of the conductive pads (10) arranged on the active face (100) of the chip (1) and intended for its electrical connection with the substrate (2); b) an approximately hemispherical boss (3) is deposited on each of these conductive pads (10), the diameter (A) of which is slightly less than the dimensions of the cross section of the conductive channels (4), in this case their diameter ( B) if these channels are cylindrical; c) the chip (1) is positioned on the substrate (2), active face (100) facing the mounting face (200), so that each boss (3) is placed in abutment on the through end d 'a channel (4); d) applying a pressure (F) tending to bring the chip (1) closer to the substrate (2) so as to partially penetrate each of the bosses (3) in the conductive material of the channel (4) which is associated with it by producing a electrical connection at this level.
2. Procédé de montage selon la revendication 1, caractérisé par le fait que le substrat (1) est de type multicouches, de préférence obtenu par le procédé de co-cuisson à basse température.2. Assembly method according to claim 1, characterized in that the substrate (1) is of the multilayer type, preferably obtained by the co-cooking process at low temperature.
3. Procédé de montage selon la revendication 2, caractérisé par le fait qu'on monte la puce (1) à l'intérieur d'une ouverture (21) ménagée dans au-moins l'une (20a) des couches constitutives du substrat (1), et qu'on la fixe à la couche sous-jacente (20b). 4. Procédé de montage selon l'une des revendications 1 à 3, caractérisé par le fait que la force qui est développée à l'étape c) au niveau de chaque liaison bossage (3) / canal (4) est comprise3. Mounting method according to claim 2, characterized in that the chip (1) is mounted inside an opening (21) formed in at least one (20a) of the constituent layers of the substrate (1), and that it is fixed to the underlying layer (20b). 4. Assembly method according to one of claims 1 to 3, characterized in that the force which is developed in step c) at each boss (3) / channel (4) link is included
-7 -2 entre 9,8.10 et 29,-7 -2 between 9.8.10 and 29,
4.10 Newton.4.10 Newton.
5. Procédé de montage selon l'une des revendications 1 à 4, caractérisé par le fait que l'étape c) est réalisée avec applica- tion de chaleur.5. Assembly method according to one of claims 1 to 4, characterized in that step c) is carried out with the application of heat.
6. Procédé de montage selon l'une des revendications 1 à 5, caractérisé par le fait que l'étape c) est réalisée avec applica¬ tion d'ultra-soπs.6. Mounting method according to one of claims 1 to 5, characterized in that step c) is carried out with applica¬ tion of ultra-soπs.
7. Procédé de montage selon l'une des revendications 1 à 6, caractérisé par le fait que les parties conductrices en forme de bossages (3) sont obtenues au cours de l'étape a) à partir d'un fil7. Mounting method according to one of claims 1 to 6, characterized in that the conductive parts in the form of bosses (3) are obtained during step a) from a wire
(30) dont on fond l'extrémité en lui donnant la forme d'une boule(30) the end of which is melted, giving it the shape of a ball
(31) que l'on dépose sur la puce (1), après quoi on sectionne le fil (30) au ras de la boule (31). (31) which is deposited on the chip (1), after which the wire (30) is cut flush with the ball (31).
8. Procédé de montage selon l'une des revendications 1 à 7, caractérisé par le fait que les bossages (3) ont un diamètre moyen (A) compris entre 50 et 100 micromètres, tandis que les canaux conducteurs (4) ont un diamètre (B) compris entre 80 et 150 micromètres. 8. Mounting method according to one of claims 1 to 7, characterized in that the bosses (3) have an average diameter (A) between 50 and 100 micrometers, while the conductive channels (4) have a diameter (B) between 80 and 150 micrometers.
9. Procédé de montage selon l'une des revendications 1 à 8, caractérisé par le fait qu'on interpose entre la face de montage (200) du substrat (2) et la face active (100) de la puce (1) un composé organique (8) apte à améliorer la liaison mécanique et/ou les transferts thermiques entre la puce (1) et le substrat (2). 9. Mounting method according to one of claims 1 to 8, characterized in that interposed between the mounting face (200) of the substrate (2) and the active face (100) of the chip (1) a organic compound (8) capable of improving the mechanical bond and / or the heat transfers between the chip (1) and the substrate (2).
10. Procédé de montage selon l'une des revendications 1 à 9, caractérisé par le fait qu'on monte des puces (1, l', 1") sur les deux faces (200, 201) du substrat (2).10. The mounting method according to one of claims 1 to 9, characterized in that the chips (1, l ', 1 ") are mounted on the two faces (200, 201) of the substrate (2).
11. Ensemble constitué par l'assemblage de puces à circuit intégré (1) sur un substrat de câblage (2), caractérisé par le fait que la face active (100) des puces est garnie d'un ensemble de bossages conducteurs (3), de forme approximativement hémisphérique, qui sont directement et partiellement enfoncés chacun dans un canal (4) rempli d'un matériau conducteur et débouchant sur l'une des faces (200) du substrat.11. Assembly constituted by the assembly of integrated circuit chips (1) on a wiring substrate (2), characterized in that the active face (100) of the chips is provided with a set of conductive bosses (3) , of approximately hemispherical shape, which are directly and partially inserted each in a channel (4) filled with a conductive material and opening onto one of the faces (200) of the substrate.
12. Ensemble selon la revendication 11, caractérisé par le fait qu'il comprend un composé organique (8) intercalé entre les deux faces en regard (100, 200) des puces (1) et du substrat (2).12. The assembly of claim 11, characterized in that it comprises an organic compound (8) interposed between the two opposite faces (100, 200) of the chips (1) and the substrate (2).
13. Ensemble selon la revendication 11 ou 12, caractérisé en ce que le substrat (2) est un substrat en céramique multicouches obtenu par co-cuisson à basse température. 13. An assembly according to claim 11 or 12, characterized in that the substrate (2) is a multilayer ceramic substrate obtained by co-firing at low temperature.
PCT/FR1992/000327 1991-04-25 1992-04-14 Method for mounting an integrated circuit chip on a wiring substrate WO1992020101A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR91/05368 1991-04-25
FR9105368A FR2675946B1 (en) 1991-04-25 1991-04-25 METHOD FOR MOUNTING A CHIP WITH INTEGRATED CIRCUIT ON A WIRING SUBSTRATE.

Publications (1)

Publication Number Publication Date
WO1992020101A1 true WO1992020101A1 (en) 1992-11-12

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PCT/FR1992/000327 WO1992020101A1 (en) 1991-04-25 1992-04-14 Method for mounting an integrated circuit chip on a wiring substrate

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FR (1) FR2675946B1 (en)
WO (1) WO1992020101A1 (en)

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JPS61133637A (en) * 1984-12-03 1986-06-20 Nec Corp Method for forming connecting electrode
EP0191434A2 (en) * 1985-02-15 1986-08-20 International Business Machines Corporation Improved solder connection between microelectronic chip and substrate and method of manufacture
JPS62111457A (en) * 1985-11-11 1987-05-22 Nec Corp Multiple chip package
JPS62122258A (en) * 1985-11-22 1987-06-03 Nec Corp Multiple-chip package
EP0329133A2 (en) * 1988-02-19 1989-08-23 Microelectronics and Computer Technology Corporation Flip substrate for chip mount
EP0376924A2 (en) * 1987-05-21 1990-07-04 RAYCHEM CORPORATION (a Delaware corporation) Gold compression bonding
EP0414204A2 (en) * 1989-08-21 1991-02-27 Hitachi, Ltd. Multilayer interconnection substrate and semiconductor integrated circuit device using the same

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Publication number Priority date Publication date Assignee Title
JPS61133637A (en) * 1984-12-03 1986-06-20 Nec Corp Method for forming connecting electrode
EP0191434A2 (en) * 1985-02-15 1986-08-20 International Business Machines Corporation Improved solder connection between microelectronic chip and substrate and method of manufacture
JPS62111457A (en) * 1985-11-11 1987-05-22 Nec Corp Multiple chip package
JPS62122258A (en) * 1985-11-22 1987-06-03 Nec Corp Multiple-chip package
EP0376924A2 (en) * 1987-05-21 1990-07-04 RAYCHEM CORPORATION (a Delaware corporation) Gold compression bonding
EP0329133A2 (en) * 1988-02-19 1989-08-23 Microelectronics and Computer Technology Corporation Flip substrate for chip mount
EP0414204A2 (en) * 1989-08-21 1991-02-27 Hitachi, Ltd. Multilayer interconnection substrate and semiconductor integrated circuit device using the same

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PATENT ABSTRACTS OF JAPAN vol. 11, no. 341 (E-554)(2788) 7 Novembre 1987 & JP,A,62 122 258 ( NEC ) 3 Juin 1987 *

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Publication number Publication date
FR2675946A1 (en) 1992-10-30
FR2675946B1 (en) 1993-08-20

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