WO1992001281A1 - Synchronisation selective du contenu de tampons d'images multiples - Google Patents

Synchronisation selective du contenu de tampons d'images multiples Download PDF

Info

Publication number
WO1992001281A1
WO1992001281A1 PCT/US1991/004692 US9104692W WO9201281A1 WO 1992001281 A1 WO1992001281 A1 WO 1992001281A1 US 9104692 W US9104692 W US 9104692W WO 9201281 A1 WO9201281 A1 WO 9201281A1
Authority
WO
WIPO (PCT)
Prior art keywords
update
frame buffer
rendering engine
rendering
update block
Prior art date
Application number
PCT/US1991/004692
Other languages
English (en)
Inventor
Jonathan D. Garman
Original Assignee
Athenix Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Athenix Corporation filed Critical Athenix Corporation
Publication of WO1992001281A1 publication Critical patent/WO1992001281A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1454—Digital output to display device ; Cooperation and interconnection of the display device with other functional units involving copying of the display data of a local workstation or window to a remote workstation or window so that an actual copy of the data is displayed simultaneously on two or more displays, e.g. teledisplay
    • G06F3/1462—Digital output to display device ; Cooperation and interconnection of the display device with other functional units involving copying of the display data of a local workstation or window to a remote workstation or window so that an actual copy of the data is displayed simultaneously on two or more displays, e.g. teledisplay with means for detecting differences between the image stored in the host and the images displayed on the remote displays

Definitions

  • This invention relates to the control of multiple remote display stations; in particular, relates to the method of providing pixels ("rendering") at the remote display stations from a centralized controller.
  • a system with a central controller (“rendering engine”) controlling a remote display may transmit rendered pixels to the display.
  • These methods include direct transmission of video signals, pixel by pixel updating, and periodic retransmission of the entire display. All of these methods require very high information bandwidth, which is both difficult and expensive to achieve.
  • a common method to reduce the bandwidth requirement is to perform some rendering at the remote display itself, transmitting codes representing considerably more information than the pixels themselves. For example, a line (vector) is transmitted as a pair of end-point coordinates (or triples, for 3-dimensional lines) .
  • the X Window System a product of the MIT X Consortium, is an example of a standardized method for performing rendering remotely from a processor running an application program ("application engine") .
  • the purpose of the X Window System is to allow efficient rendering at the remote display, even though the application program is executed at a location separated from the rendering location by a great distance.
  • An ' efficient set of high level (in general, higher than pixel level) objects are defined and known by name to both the application and the rendering engines. The need to send complete objects pixel by pixel is eliminated by transmitting object names and parametric descriptions.
  • a system which provides a rendering engine between the application engine and multiple displays. Both the displays and the application engine are remotely connected to the rendering engine.
  • a frame buffer (“rendering frame buffer”) into which the rendering engine directly draws (i.e. provides the pixels represented as bits) is associated with each display.
  • the content of each rendering frame buffer is transferred from the rendering engine to the respective display, which has a local frame buffer (“display frame buffer”) within it.
  • display frame buffer To reduce the bandwidth required to transfer the pixels from the rendering frame buffer to the remote display frame buffer, only the portion of the rendering frame buffer in which the rendering engine has drawn is transferred.
  • Figure 1 is a block diagram showing a scheme by which rendering engine 101 periodically updates remote displays, in accordance with the present invention.
  • Figure 2 shows, for one display, the contents of the rendering frame buffer and the display frame buffer at various times during the execution of an application program, in accordance with the present invention.
  • Figure 1 is a block diagram showing a scheme by which a rendering engine 101 of a Z-controller or Z-node supporting multiple remote display stations achieves a lower cost by sharing the required resources of the X Window System at the rendering and display locations, in accordance with the present invention.
  • the Z-controller or Z-node updates each supported display periodically or when requested, but updates only that portion of each display which has changed since the last update.
  • the rendering engine 101 receives data for central processing unit (CPU) 100. These data may be rendering commands and high level graphical object descriptions sent to the rendering engine.
  • CPU 100 may be the application engine, or may be a network receiver of commands from a remote application engine.
  • the rendering engine 101 which and CPU 100 may form parts of one computer, converts high level graphical object descriptions into pixels, and draws the pixel values into frame buffer 102 at the addresses computed during the rendering operations.
  • a high level object may be as simple as a vector (straight line) specified by the coordinates of its end-points.
  • the rendering engine 101 Upon receiving the vector, the rendering engine 101 renders the vector by writing the vector value (color) into the pixel addresses located between the end-points. This is a one-to-many type operation, where the number of pixel write operations depends upon the distance between the end-points, and also whether more complicated functions such as anti-aliasing are required.
  • Frame buffer 102 holds the pixel values for the displayed image, with each value stored at an addressable location in frame buffer 102 corresponding to a pixel on the physical display. This correspondence must be one-to-one (unique and unambiguous) , but need not be in the same organizational form or number of dimensions or type of contiguity.
  • Frame buffer 102 is written into by the rendering engine 101 and read by the update block refresh controller 112. When anti-aliasing is required, frame buffer 102 may also be read by the rendering engine 101.
  • update block coordinate monitors 108-111 there are four update block coordinate monitors 108-111 corresponding to four update block coordinate registers 104-107.
  • the update block coordinate registers 104-107 contain the four pixel values Xmin, Ymin, Xmax and Ymax, being respectively the minimum X pixel address, the minimum Y pixel address, the maximum X pixel address, and the maximum Y pixel address, which collectively define the smallest area ("update block") on the display bounding all pixels written since the last update cycle.
  • This arrangement presumes that addresses are available in 2-dimensional Cartesian coordinate form, although not necessary for the practice of the present invention. The same comparison can be accomplished with a min/max pair operating in a single dimension, though that will not allow the update block to be as small as in the 2-dimensional case.
  • the cost of using one coordinate system is often determined by the cost of address comparison (during writing) and address generation (during refresh) , both at the rendering engine and at the display.
  • the benefit is the possibility of having the smallest number of pixels in the update area relative to the number of updates within the area. Pixels which are in the update area but are not written will be transmitted redundantly to the remote display, and it is fundamental to the present invention that the number of redundant pixels transmitted during update be much less than the number of bits required to independently specify the address of each updated pixel.
  • the similarity of pixels makes the redundant pixels easily compressible for efficient transmission, whereas addresses would be much less compressible.
  • Each update block coordinate monitor compares each pixel address as it is written by the rendering engine 101 with the value stored in the corresponding update block coordinate register, to determine whether the pixel being written lies within the currently defined update block coordinates, or whether any of the values stored in the update block coordinate registers 104-107 must be updated to include the pixel address being written (the pixel value is ignored, and only the address is used for comparison) .
  • Update block refresh controller 112 reads all the pixels within the update block using the values in the update block coordinate registers 104-107 and sends the pixels within the update block to the remote display. This operation can be performed after the rendering engine 101 completes a group of rendering operations, or upon receiving a command from the application program, such as a "flush buffer" command, or under control of a periodic timer, or a combination of these events, whichever occurs first. In any case, updating must be done often enough to provide the user at the display a fair degree of interactivity. A fair degree would be 5-10 times per second, for example, and preferably more frequent than that.
  • the pixel transmitter 113 provides the mechanism for moving the pixel data between the update refresh controller 112 and a remote display (not shown) .
  • the transfer may be over a network, or a dedicated interface. In either case, it must support a transmission facility capable of the required bandwidth and covering the distance between the rendering engine and the display unit.
  • the update area is nil.
  • the first pixel written creates an area (a rectangle in this embodiment) of size 1 (1 pixel) .
  • the address of this pixel is stored in the update block coordinate registers 104-107 as the minimum and maximum coordinates of the update block.
  • the pixel's address is compared to the update block (pixel values are not compared) , and if the pixel's address lies outside of the update block, the update block is increased to include that pixel address. Accordingly, the new value of the update block is written into the update block coordinate registers 104-107. This process continues until the end of the update cycle when the pixels in the updated block are transferred to the remote display by pixel transmitter 113.
  • the update block coordinates (the contents of update block coordinate registers 104-107) are first sent to the remote display, followed by the pixel values within the update block.
  • the pixel values may be sent in a compressed form in order to reduce transmission time.
  • Both linear or 2-dimensional compression algorithms may be used (there is no 3-dimensional information remaining at this point) , and can involve the dynamic determination of subblocks which can be repeated to further reduce the transmission time, such as possible with images containing background texture "fill" patterns.
  • Another simplification may be achieved by treating the 2-dimensional data as linear, with the conversion determined from the dimensions of the update area.
  • the area could be considered as a single vector composed of a linearly contiguous set of y vectors of length x, if the update area has dimensions of x by y. This serves to reduce the amount of location information attached to the data.
  • the update block coordinate registers 104-107 are re-set to nil, and writing into the frame buffer 102 by rendering engine 101 is again enabled.
  • the nil update block is a special condition to be recognized: while in this condition, the values in the update block coordinate registers 104-107 must not be construed as address values.
  • One method to recognize this special condition of the nil state is to set the values of the update block coordinate registers 104-107 to values outside the display address limits, e.g. set the nil value of Xmin to a value greater than or equal to the largest possible value of X, so whatever value of X is next written will pass the A ⁇ B comparison in update block coordinate monitor 108 and get written into the update block coordinate register 104.
  • set Xmax to zero, or less than or equal to the smallest value of X possible to ensure the first value is written into the corresponding register.
  • the treatment for the Y registers are exactly alike.
  • Figure 2 is provided to illustrate the states of the update and display frame buffers during execution of an application program in a sequence of snapshots covering eight time periods (tl to t8) .
  • tl to t8 time periods covering eight time periods
  • both update and the display frame buffers are at initial states.
  • the update block coordinates have grown to be the smallest rectangle 250r which just encompasses the area into which the pixels were written.
  • the rectangle 250r is aligned with the axes of the display because the 2-dimensional addressing scheme is used.
  • the refresh controller 112 initiates a update operation to transfer the pixels within the update block to the display frame buffer in the remote display.
  • the pixel transmitter 113 performs compression on the pixels in rectangle 251r before transmission. (It is of course possible, in another embodiment, to have the refresh controller rather than the pixel transmitter, perform compression on the pixels before transmission) .
  • the refresh controller 112 During the transmission of the update block to the remote display, the refresh controller 112 must take control of the update frame buffer 102 from the rendering engine 101, and prevents further rendering into the update frame buffer 102 for the duration of the update operation.
  • the means for exchanging control of a resource such as a frame buffer is well known in the art. If for any reason, control is lost during a refresh or update operation, the refresh or update operation must be aborted and restarted. It is critical that the addresses in the block update coordinate registers 104-107 not be re-set to their nil values until the update operation is successful, unless care is taken to incrementally reduce the update block; such care is not taken in this embodiment.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

Système dans lequel un contrôleur central (101) se situe entre le contrôleur d'application (100) et des affichages multiples. A la fois les affichages et le contrôleur d'application sont connectés à distance au contrôleur central. Au niveau du contrôleur central, un tampon d'images (102) ("tampon d'images central") dans lequel le contrôleur central (101) effectue une introduction directe (c'est-à-dire qu'il transmet les pixels représentés par des bits) est associé à chaque affichage. Périodiquement, le contenu de chaque tampon d'images central est transféré du contrôleur central à l'affichage respectif, lequel comporte un tampon d'images local ("tampon d'images d'affichage"). Afin de réduire la largeur de bande nécessaire au transfert des pixels du tampon d'images central (102) au tampon d'images d'affichage à distance, seule la partie du tampon d'images central dans laquelle le contrôleur central a effectué une introduction est transférée.
PCT/US1991/004692 1990-07-10 1991-07-02 Synchronisation selective du contenu de tampons d'images multiples WO1992001281A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US55159490A 1990-07-10 1990-07-10
US551,594 1990-07-10

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WO1992001281A1 true WO1992001281A1 (fr) 1992-01-23

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0590817A1 (fr) * 1992-09-15 1994-04-06 International Business Machines Corporation Mise à jour de l'écran d'une station de travail périphérique d'ordinateur
WO1995033255A1 (fr) * 1994-05-27 1995-12-07 Hughes Aircraft Company Mise a jour rapide d'objets graphiques dans un affichage de controle de circulation aerienne
EP0803798A1 (fr) * 1996-04-22 1997-10-29 International Business Machines Corporation Système d'imagerie informatisé avec un transfert efficace de données graphiques vers un sous-système graphique en utilisant un accès direct masqué en mémoire de trame
NL1021652C2 (nl) * 2002-10-15 2004-04-16 Johan Ritser Kuipers Systeem voor het produceren van een medium, zoals een beeld.
WO2005045737A2 (fr) 2003-10-23 2005-05-19 Microsoft Corporation Donnees graphiques et de zone synchronisees pour systemes de commande graphique a distance
CN100368984C (zh) * 2004-06-11 2008-02-13 精工爱普生株式会社 利用描绘命令的钩挂的图像供给装置及方法
WO2011004233A3 (fr) * 2009-07-09 2011-03-24 Nokia Corporation Procédé et appareil adaptés pour exécuter l'affichage d'un tampon de trames
EP3032492A1 (fr) * 2014-12-12 2016-06-15 Samsung Electronics Co., Ltd. Appareil et procede de traitement d'images
US9690599B2 (en) 2009-07-09 2017-06-27 Nokia Technologies Oy Method and apparatus for determining an active input area
EP4086793A4 (fr) * 2019-12-31 2023-12-06 Korea Advanced Institute of Science and Technology Procédé de distribution d'interface utilisateur sécurisé pour une interaction multidispositif hétérogène

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106095366B (zh) * 2016-06-07 2019-01-15 北京小鸟看看科技有限公司 一种缩短图像延迟的方法、装置和虚拟现实设备

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862164A (en) * 1988-02-09 1989-08-29 The United States Of America As Represented By The Secretary Of The Army Infrared aircraft landing system
US5008747A (en) * 1987-10-19 1991-04-16 British Telecommunications Public Limited Company Signal coding

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5008747A (en) * 1987-10-19 1991-04-16 British Telecommunications Public Limited Company Signal coding
US4862164A (en) * 1988-02-09 1989-08-29 The United States Of America As Represented By The Secretary Of The Army Infrared aircraft landing system

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0590817A1 (fr) * 1992-09-15 1994-04-06 International Business Machines Corporation Mise à jour de l'écran d'une station de travail périphérique d'ordinateur
US5491780A (en) * 1992-09-15 1996-02-13 International Business Machines Corporation System and method for efficient computer workstation screen updates
WO1995033255A1 (fr) * 1994-05-27 1995-12-07 Hughes Aircraft Company Mise a jour rapide d'objets graphiques dans un affichage de controle de circulation aerienne
AU682268B2 (en) * 1994-05-27 1997-09-25 Raytheon Company Low latency update of graphic objects in an air traffic control display
US5760793A (en) * 1994-05-27 1998-06-02 Raytheon Company Low latency update of graphic objects in an air traffic control display
EP0803798A1 (fr) * 1996-04-22 1997-10-29 International Business Machines Corporation Système d'imagerie informatisé avec un transfert efficace de données graphiques vers un sous-système graphique en utilisant un accès direct masqué en mémoire de trame
NL1021652C2 (nl) * 2002-10-15 2004-04-16 Johan Ritser Kuipers Systeem voor het produceren van een medium, zoals een beeld.
EP1695256A2 (fr) * 2003-10-23 2006-08-30 Microsoft Corporation Donnees graphiques et de zone synchronisees pour systemes de commande graphique a distance
WO2005045737A2 (fr) 2003-10-23 2005-05-19 Microsoft Corporation Donnees graphiques et de zone synchronisees pour systemes de commande graphique a distance
EP1695256A4 (fr) * 2003-10-23 2010-03-03 Microsoft Corp Donnees graphiques et de zone synchronisees pour systemes de commande graphique a distance
CN100368984C (zh) * 2004-06-11 2008-02-13 精工爱普生株式会社 利用描绘命令的钩挂的图像供给装置及方法
WO2011004233A3 (fr) * 2009-07-09 2011-03-24 Nokia Corporation Procédé et appareil adaptés pour exécuter l'affichage d'un tampon de trames
US9690599B2 (en) 2009-07-09 2017-06-27 Nokia Technologies Oy Method and apparatus for determining an active input area
EP3032492A1 (fr) * 2014-12-12 2016-06-15 Samsung Electronics Co., Ltd. Appareil et procede de traitement d'images
US9824667B2 (en) 2014-12-12 2017-11-21 Samsung Electronics Co., Ltd. Image processing apparatus and method
EP4086793A4 (fr) * 2019-12-31 2023-12-06 Korea Advanced Institute of Science and Technology Procédé de distribution d'interface utilisateur sécurisé pour une interaction multidispositif hétérogène

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