WO1991018365A1

WO1991018365A1 - Method and apparatus for generating an analogue signal from an encoded digital signal

Info

Publication number: WO1991018365A1
Application number: PCT/GB1991/000767
Authority: WO
Inventors: Vernon Thomas Seymour Howell
Original assignee: Hi-Med Instruments Limited
Priority date: 1990-05-16
Filing date: 1991-05-16
Publication date: 1991-11-28
Also published as: AU7866191A; GB9010970D0

Abstract

A digital audio signal generator (30) includes an EPROM memory (32) containing a digitally encoded audio signal sampled at a fixed rate. An address counter (48) retrieves the digital values sequentially from the memory, and the data is fed to a segment generator which generates a segment of a predetermined wavefuction. The audio signal is generated by joining together consecutive segments. The segment generator includes output DACs (66, 70) and reference DACs (60, 62) which control the output amplitudes of the output DACs. A summing amplifier (72) combines the outputs from the output DACs to produce the output audio signal. A counter (44) generates a sequence of values representing a straight line wave function, which values are fed to the output DACs.

Description

_ _χ _

METHOD AND APPARATUS FOR GENERATING AN ANALOGUE SIGNAL FROM AN ENCODED DIGITAL SIQflAL

FIELD OF TEE ]_NVENTION

The present invention relates to a method and apparatus for generating an analogue signal from an encoded digital signal. In one aspect the invention relates to generating an audio signal from an encoded digital signal.

BACKGROUND OF THE INVENTION

A conventional method for storing an audio signal is to sample the waveform periodically, and quantise each instantaneous sampled value as a digital value using an analogue to digital converter (ADC) . The bandwidth of the encoded signal is determined by the rate at which the audio signal is sampled, the max__ι^**um frequency detectable being half the sampling frequency. Typically, for a good quality audio encoder, the πaximum encodeable frequency may be around 16kHz, requiring a sampling frequency of 32kHz. Figure 1 illustrates a portion of an audio signal 10 being sampled at periods 12a-12f, and encoded as conresponding digital values 14a-14f, respectively. To keep the amount of encoded digital information to a manageable level capable of being stored in an integrated circuit memory, the resolution of the ADC is typically 8 bits, allowing 256 quantisation values.

To regenerate the audio signal from the encoded digital signal, the digital values are fed back into a digital to analogue converter (DAC) at the same rate as they were originally sampled. Figure 2 illustrates the digital signal encoded in figure 1 being regenerated using this ]-^*e_hod. Referring to figure 2, the output from the DAC is in the form of a stepped voltage 16, each new digital value 14a- 14f resulting in a corresponding voltage step level 18a-18f, respectively. The output from the DAC therefore approximates to the shape of the original audio waveform, however, the output signal contains serious high frequency cc∑mponents which are caused by the sharp corners in the step shape of the output signal.

In conventional digital audio systems, filters are used to remove the high frequency components, and thereby smooth the output waveform to more closely approximate to the original audio signal. One form of filter is an analogue filter which smoothes the waveform ^■after it has been produced by the DAC. Such filters are necessarily expensive and ooπplicated, and introduce undesirable phase and amplitude distortions in the generated audio signal. Another form of filter is a digital "over sampling" filter which mathematically interpolates between consecutive digital values to synthesize a small number of intermediate values which are fed to the DAC as part of the digital signal. Such digital filters are also necessarily complicated and expensive since they involve circuits for performing high-speed mathematical operations on the digital signal. A further disadvantage with digital filters is that they do not improve the output quantisation of the DAC, ie. in the example discussed above, only 256 quantised values can be produced from the DAC. This problem is illustrated in figure 2, where, even with oversampling, the quantised values 18e and 18f cannot reproduce the original waveform faithfully because the values of the points 14e and 14f are only a single quantisation value apart.

Analogue waveform generators are also known from other applications where special waveforms are required. An application note published by Analog Devices, entitled "Methods For Generating Complex Waveforms and Vectors Using M ltiplying D/A Converters" by Phil Burton, reference E671-15-9/81, describes an interpolation method of joining together straight lines between predete_^*ined amplitude level points to generate a waveform. tjhough of general application, the method is particularly suited to a graphics generator which is described, in which the length of each straight line is controlled by the generator, and depends on the difference between the amplitude levels joined by the line. The generator includes multiplying DACs which are loaded with the aπplitude data, and supplied with an analogue variable frequency triangle waveform, for producing the straight lines. The amplitude level data is supplied by a main processor rather than from a memory device, the processor batch loading data into FIFO (first in, first out) input buffers provided in the DACs. This method has the advantage that the number of predeteπnined amplitude levels can be reduced compared to a conventional step-output DAC system. However, as explained hereinbefore, in audio recording and playback applications the number, or rate of encoding, of predetermined amplitude levels is determined by the desired bandwidth of the audio signal.

SUMMARY OF THE INVENTION

The present invention is defined in the claims.

The principle of the invention is to smooth the signal represented by the digital amplitude points by generating a ramp segment extending between each adjacent pair of digitally encoded points. The ramp segment may be a straight line segment, or some other wavefunction.

With the invention, the need for complicated analogue or digital filtering can be avoided.

A feature of one aspect of the invention is to convert the digital values of each pair of adjacent points into corresponding analogue reference signals which represent the amplitude levels of the initial and final end points of the ramp segment to be generated. The analogue ramp segment is generated to extend from the initial amplitude level to the final aπplitude level.

A feature of another aspect of the invention is to generate a digital reference signal for use in producing the ramp segment. The digital reference signal coπprises digital values representing points on a staircase raπp segment extending between a zero value and a maximum value. The duration of the reference ramp signal determines the duration of the generated ramp segment. The reference signal may comprise digital up-raπps or down-raπps, but in a preferred embcx__irrent the reference signal coπprises alternate up-raπps and down-raπps. One technique for generating the reference signal is to use a digital counter which is repeatedly incremented or decremented by a clock signal. In the preferred eiiibodiment, the counter is reversible so as to be able to generate the alternate up-ramps and down-ramps. The counter is an 8-bit counter giving a possible 256 output values. This has been found to provide adequately smooth analogue output signals, in particular for audio signals.

The smoothness of the generated signal will depend on the smooth¬ ness of the ramp segments. By using a high quality ramp segment generator, a smooth signal can be generated regardless of the resolution or quantisation range of the encoded digital values. Word lengths of 8-bits for the digitally encoded signal have been found to produce very acceptable audio signals, despite the apparent low resolution available with 8-bit encoding. Conventional good quality digital audio systems use at least 14 or 16 bit words to encode the digital values. The use of shorter length data words improves the coπpression of the encoded digital data, and makes it more suitable for storage in an integrated circuit memory.

DESCRIPTION OF THE DRAWINGS

An en±xx-liment of the invention will now be described by way of example, with reference to the re_^**a__ning figures of the accoπpanying drawings, in which:

Figure 3 is a block diagram of the parts of an apparatus for generating an audio signal from an encoded digital signal stored in an integrated circuit memory; and

Figures 4 to 7 show examples of waveforms generated by the apparatus. DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to figure 3, an audio signal generating apparatus 30 includes an integrated circuit memory in the form of an EPRCM 32. The EPROM contains digital values of an audio signal to be generated, the digital values representing points on the audio signal waveform sampled at a fixed rate. In the present eiiibodiment, the saπple rate is 32kHz, and the digital values are stored as 8 bit numbers. The EPRCM memory 32 is organised as four sections, each of which can be accessed individually. Up to four different audio signals can be stored in the EPRCM 32, and any one can be selected for generation by the apparatus.

The EPROM has a data output 34, and address input 36 and a memory section select input 38. The section select input 38 is coupled to a manually operable switch 40. The select input 38 controls from which section of memory the output data is retrieved, and the switch 40 therefore allows an operator to control which of the four encoded signals the apparatus generates.

A free running crystal controlled clock oscillator 42 is coupled to a 256-step counter 44. The counter 44 is bidirectional, ie. it can count up from zero and it can count down to zero, and it has an 8-bit output 45. The counter 44 includes control logic (not shown) for controlling the count direction, and for generating an "end pulse" at an output 41 when the counter reaches its πexiiπum value of 255 or its m__n_utιum value of zero. In use, the counter will initially be set for counting up from zero, -and the counter output 45 will be incremented on every pulse from the oscillator 42. When the counter output 45 reaches the max__r^**__m value of 255, an "end pulse" is generated and the count direction is reversed, ie. to count down to 2ero. When the output 45 again reaches zero, a further "end pulse" is generated, and the count direction is again reversed, ie. to count up from zero. Thus the output 45 cycles through alternate increasing and decreasing values, and an "end pulse" is generated at intervals of every 256 pulses from the oscillator. The counter 44 and the clock oscillator 42 together form a digital reference generator, and the output 45 forms a digital reference signal in the form of alternate digital up-raπp and down-ramp straight line segments.

The output 41 from the step counter 44 is coupled to the increment input 46 of a memory address counter 48. The output from the address counter 48 is coupled to the address input 36 of the EPRCM 32. In the present eπibcdiment, the oscillator 42 generates a frequency of 256 times the saπpling frequency of the encoded digital values, ie. 256 x 32kHZ = 8.192MHZ. In use, the oscillator generates the 8.192MHz clock frequency which is divided by the step counter 44 to the 32KHz sampling frequency, .and fed to the address counter 48 to increment the address value held in the address counter 48 at a rate of 32KHz. The address counter 48 accesses the data held in the EPRCM 32, and therefore causes the data to be sent to the data ouput 34 at the correct rate of 32KHz.

The data output 34 is connected in parallel to a first data latch 50 and to a second data latch 52. The output 41 from the step counter 44 is connected to a flip-flop 54, in parallel with the connection to the address counter 48. The flip-flop has cαπplementary outputs 56a and 56b, connected to control inputs of the first and second data latches 50 and 52, respectively. In use, when data is being read out from the EPRCM 32, the flip flop acts as a controlling means to determines which latch 50, 52 accepts data from the data output 34. When output 56a is high and output 56b low, the first latch 50 accepts the data, and when output 56b is high and output 56a low, the second latch 52 accepts the data.

The sections of the circuit enclosed by the box 69 form supplying means for supplying the sequence of digitally encoded aπplitude levels at the appropriate rate to an output ramp segment described below.

The output from the first latch 50 is connected to the input of a first reference DAC 60, and the output from the second latch 52 is cOnnected to the input of a second reference DAC 62. The analogue output from the first reference DAC 60 is connected _hrough a first buffer amplifier 64 to the upper reference voltage input Vmax of a first output DAC 66, and the analogue output from the second reference DAC 62 is connected t_hrough a second buffer amplifier 68 to the lower voltage reference input Vmin of a second output DAC 70. The output 45 from the step counter 44 is connected in parallel to the digital inputs of the first .and second output DACs 66, 70, respectively. The analogue outputs from the output third and fourth DACs 66 and 70 are connected to respective inputs of a linear cx_3^*±)ining means in the form of a s^*-_mr_ι__ng amplifier 72, whose output forms an analogue audio output 74 from the generator.

The sections of the circuit enclosed by the box 71 form the ra p segment generator for generating an analogue ramp segment extending between the end point aπplitude levels supplied as analogue inputs from the first and second reference DACs. The first output DAC produces a third analogue signal from the digital reference signal, and the Vmax and Vπiin inputs control the Aπplitude of the third analogue signal in response to the first reference signal. The second output DAC produces a fourth .analogue signal coπple entary to the third analogue signal, and the Vmax and Vmin inputs control the amplitude of the fourth signal in response to the second analogue reference signal.

The upper and lower reference voltage inputs of the output DACs control the output voltage levels of the DACs. The lower reference Vmin input sets the voltage that is generated by the DAC when the digital input is zero, and the upper reference Vmax input sets the voltage that is generated by the DAC when the digital input is at its ιτBX__mum value, ie. 255. The input Vmin of the first output DAC 66, and the Vmax input of the second output DAC 70 are connected to a zero-reference level zero volt line. Therefore the output DACs 66 and 70 are arranged in coπplementary fashion, with the output from the first output DAC 66 being a πraximum when its digital input is 255, and the output from the second output DAC 70 being a _τ_ax__π__ιm when its digital input is zero.

In use, to generate an audio signal, the operator first selects which of the four stored signals to generate, using the switch 40. The address counter 48 and the step counter 44 are initially reset. As explained hereinbefore, the 8.192MHz clock signal from the oscillator 42 is fed to the step counter 44 which produces a train of "end pulses" at a frequency of 32KHz. Each "end pulse" increments the value in the address counter 48, which causes the digital value corresponding to the next point in the audio signal waveform to be sent to the data output 34. Depending on the state of the flip-flop 54, the data will either be stored in the first latch 50 or in the second latch 52. Each "end pulse" toggles the state of the flip-flop 54 so that data is stored alternately in the first and second latches 50 and 52, respectively.

The digital values in the latches 50 and 52 are converted into analogue referenced voltage levels by the first and second DACs 60 and 64, respectively, and fed to the reference voltage inputs of the first and second output DACs 66 and 70, respectively. The reference voltage inputs determine the initial and final aπplitude level points of an analogue straight line segment.

Between each "end pulse", the step counter 44 runs through a cαπplete cycle of counting up or down through 256 values. Referring to the figures, and considering generation of the audio signal 81 between the encoded points 80 and 82 in figure 4, say that for example the digital aπplitude data for the point 80 is stored in the second latch 52, and the digital aπplitude data for the point 82 is stored in the first latch 50. With this order of data in the latches, as the step counter 44 runs through a cycle of 256 counts between consecutive "end pulses", the output 45 increases linearly as a digital up-raπp from zero to 255, as shown in figure 5.

Referring to figure 6, the digital values contained in the latches 50 and 52 modulate the output levels from the first and second output DACs 66, 70, respectively. The output from the first output DAC 66 in the form of an up-ra p is as shown by the line 86, increasing from its Vmin level of zero volts to its Vmax level determined by the aπplitude data for the point 82 stored in the first latch 50. The output from the second output DAC 70 is in the form of a down-raπp as shown by the line 84, decreasing from its Vmin level which is deteπriined by the aπplitude data for the point 80 stored in the second latch 52, to its Vmax level of zero volts. The sum "analogue output from the suτ^**ming aπplifier 72 is as shown by the line 88, which is a straight line segment joining the initial final points 80 and 82. Thus the audio signal waveform is generated as a series of straight line ramp segments joining the digitally encoded points.

Once the waveform has reached the point 82, a further "end pulse" is generated. The digital value for the next point 83 in the waveform is loaded into the second latch 50, the count-direction in the step counter 44 is reversed, to generate a digital down raπp. During generation of this segment, the first output DAC 66 produces an analogue down-raπp and the second output DAC 70 produces an analogue up-ramp, and the next straight line segment is generated between the points 82 and 83. Consecutive segments are joined together at the encoded points, and there are no discontinuities or large steps in the output waveform. Each segment comprises 256 small steps, and the duration of the segment is therefore 256 times the duration of each step. Consecutive segments are therefore generated at a rate of 8.192 MHz / 256, ie. at a rate of 32KHz which is the sampling rate of the original audio signal.

The flip-flop 54 is toggled each time an "end pulse" is generated, such that new aπplitude data is loaded alternately into the latches 50, 52. The counter 44 counts alternatively up and down througji 256 values, such that the roles of the first and second output DACs 66 and 70 as count-up and count-down DACs are effectively reversed for each new point in the digitally encoded signal. The flip-flop 54 and the step counter 44 act as control means for aligning and joining together consecutive segments to produce the output audio signal. In the present eι >od__ment_/ the output waveform is generated as a series of points at a frequency of 256 x 32Khz = 8.192 MHz. This frequency is far higher than any audio frequency, and therefore no filtering of the output is necessary since there are no undesirable high frequency components produced which may interfere with the audio signal. Even though the output does in fact consist of a large number of very small steps, the signal is adaquately smooth and no output filters are required. Modified embodiments could use either more or less steps in each wavefunction segment, however, 256 steps allows the use of conventional 8-bit address circuits.

A further advantage of the present en^*bodiment is that 256 different values are generated between consecutive digitally encoded points, regardless of the difference between the amplitude values of those points. For example, figure 7a illustrates two points 90 and 92 in a waveform 94, which are only a single quantisation value apart. As illustrated in figure 7b, even with a conventional digital over- sampling filter, the output from the DAC cannot approximate very closely to the waveform since the resolution of the output signal cannot be better than the quantisation of the output DAC. However, as illustrated in figure 7c, with the present embodiment, a straight line segment comprising 256 minutely different steps is generated which closely approximates the original signal. Thus the resolution of the generated audio signal is improved over the 8-bit digital encoding resolution. This overcomes the problem of having to use more quantisation values to generate a smooth signal, as in conventional digital audio systems.

It will also be appreciated that the reference voltages supplied to the output DACs 66 and 70, respectively, are only altered when the output from the respective DAC is zero. This avoids any glitches which could otherwise be present in the audio signal.

In^*the present embodiinent, the saπpling frequency of the encoded digital values stored in the EPRCM is 32kHZ with 8-bit resolution. The output rate of data from the EPRCM is therefore 32 Kbytes per second, which limits the _^**axi_^*πum duration of the audio signal to less than a minute with a conventional EPRCM. However, inexpensive very high capacity RCM packages are now becoming readily available and, for exaπple, a currently available 16 Mbit masked ROM allows up to 64 seconds of audio to be played. It will be appreciated that the memory may comprise several banks of integrated circuit inemories which may be addressed sequentially so that a lengthy waveform can be stored. Alternatively, the banks nay be addressed selectively so that several different waveforms may be stored.

The emb-xiiment described above uses a sampling rate of 32KHz, since this is a standard specified for broadcast quality apparatus. It will be appreciated that lower saπpling rates could also be used, with a corresponding reduction in the bandwidth of the encoded signal. For exaπple, speech signals contain frequency components which are predominantly below 4KHz, and therefore speech signals can be encoded with adaquate fidelity using a saπpling rate of 8KHz. This would give four times the recording/playback time for the digital memory compared with the 32KHz saπpling rate, ie. with a 16 Mbit RCM, over 4 minutes of good quality speech signals could be stored.

Although in the preferred embod_Lment a single reference signal generator is used, an alternative embodiment might use two generators, generating digital values representing anti-phase ramps. In such an er^*ιbc^*d__πιent, each reference generator would feed its output signal directly to one output DAC, to generate the simultaneous up-ramp and down-raπp signals. The outputs from the first and second reference DACs would be coupled respectively to the Vmax inputs of the first and second output DACs. The Vmin inputs would be set to the zero reference value.

The preferred embodiment described above is particularly suitable in a portable digital audio playback apparatus. Recorded music or speech can be stored in an integrated circuit mairory cartridge which can be plugged in to the player. The player can be built very cαπpactly so that it can be carried around in someone's pocket or in a small bag. The player can also be very robust as there are no mechanical moving parts.

In such a playback apparatus, the recorded content can be arranged in separate tracks, each track being stored in a separate section of memory. This would allow instanteous random access to the beginriing of any track, without the annoying delay often encountered with conventional audio playback apparatus.

Claims

1. Apparatus for generating an analogue waveform signal from a digitally encoded signal, the digitally encoded signal comprising a sequence of digital values representing aπplitude levels at points in the waveform, the apparatus coπprising means for supplying the sequence of digital values representing the points, first and second reference digital to analogue converter means for converting the digital values of each adjacent pair of points into corresponding analogue reference signals, which signals represent initial and final analogue aπplitude levels of a segment of the waveform to be generated, and a ra p segment generator for generating an output analogue signal in the form of a ramp segment extending from an initial level determined by the initial aπplitude reference signal, to a final level dete:_-mined by the final aπplitude reference signal.

2. Apparatus according to claim 1, wherein the ramp segment generator comprises means for producing a down-raπp signal extending fr n a first output level to a zero reference level, the first output level being determined by the value of the analogue initial aπplitude signal, means for producing an up-raπp signal s_Lmultaneously with the down-raπp signal, the up-raπp signal extending from a zero reference value to a second output level determined by the value of the analogue final aπplitude reference signal, and combining means for linearly combining the up-ramp and the down-ramp signals to produce the generated output signal.

3. Apparatus according to claim 2, further comprising a digital reference signal generator for supplying the ramp segment generator with a reference signal in the form of digital values representing points on a staircase ramp waveform, the ramp having a duration equal to the duration of the segment to be generated, and the ramp extending

SUBSTITUTESHEET between a zero reference value and a maxi_rπ__m value.

4. Apparatus according to claim 3, wherein the reference signal generator coπprises a digital counter, and clock means for clocking the counter to repeatedly increment or decrement the counter.

5. Apparatus according to claim 2, 3 or 4, wherein the means for producing the analogue up-raπp signal and the means for producing the analogue 'down-raπp signal together comprise first and second output digital to analogue converter means.

6. Apparatus according to claim 5, wherein the digital reference generator generates digital reference signals corresponding to up-raπps and down-raπps, and when the reference signal corresponds to an up-raπp the first output digital to analogue converter generates the analogue up- raπp signal and the second output digital to analogue converter generates the analogue down-raπp signal, and when the reference signal corresponds to a down-raπp the first output digital to analogue converter generates the analogue down-raπp signal and the second output digital to analogue converter generates the analogue up-raπp signal.

7. Apparatus according to claim 6, wherein the digital input of the first output digital to analogue-converter means is coupled to the digital reference input of the ramp segment generator, the converter means including means for controlling the level of the output signal from the first output digital to analogue converter means to vary between zero when the digital input is zero, and a peak level when the digital input equals the max__π^*um value.

8. Apparatus according to claim 7, wherein the first output digital to analogue converter means has an analogue upper reference input for setting the output level when the digital input equals the πexirπum value, .and the output from the first reference digital

SUBSTITUTE SHEET to analogue converter is coupled to the analogue upper reference input.

9. Apparatus according to claim 6, 7 or 8, wherein the digital input of the second output digital to analogue converter means is coupled to the digital reference input of the ramp segment generator, the converter means including means for controlling the output level from the second output digital to analogue converter means to vary between zero when the digital input equals the maximum value, and a peak level when the digital input is zero.

10. Apparatus according to claim 9, wherein the second output digital to analogue converter means has an analogue lower reference input for setting the output level when the digital input is zero and an analogue upper reference for setting the output level when the digital input equals the maximum value, the upper reference input being coupled to the zero reference level, and the lower reference input being coupled to the output from the second reference digital to analogue converter means.

11. Apparatus according to any of claims 6 to 10 , wherein the supply means includes control means responsive to the digital reference signal generator for sending the digital values for the current and preceding points to the reference first and second digital to analogue converter means, respectively, when the digital reference signal is about to begin an up-raπp, and for sending the digital values for the current and preceding points to.the reference second and first digital to analogue converter means, respectively, when the digital reference signal is about to start a down-raπp.

12. .Apparatus according to any of claims 6 to 11, wherein the digital reference generator generates a continuous waveform ^*hich comprises alternate up-raπps and down-raπps.

13. Apparatus according to claim 12, further coπprising first and

SUBSTITUTESHEET second data latches for buffering the digital inputs to the first and second reference digital to analogue converter means, the controlling means feeding the digital aπplitude values alternately to the first and second latches.

14. Apparatus according to any of claims 1 to 13, wherein the cximbining means coπprises means for summing the analogue up-raπp and down-raπp signals.

15. A method for generating an analogue waveform signal from a digitally encoded signal, the digitally encoded signal ccπprising a sequence of digital values representing aπplitude levels at points on the waveform, the irethod coπprising supplying the sequence of the digital values representing the points, converting the digital values of each pair of adjacent points into corresponding analogue reference signals, which signals represent initial and final analogue aπplitude levels of a segment of the waveform to be generated, and generating an analogue signal in the form of an analogue raπp segment extending from an initial level deteπnined by the initial analogue reference signal, to a final level deteππined by the analogue final reference signal.

16. A method according to claim 15, wherein the generation of each ramp segment coπprises producing an analogue down-raπp signal extending from a first cutout level to a zero reference value, the first output level being deteαrained by the the value of the analogue initial aπplitude reference signal, producing an analogue up-raπp signal siitiultaneously with the down-ramp signal, the up-raπp signal extending from a zero-reference value to a second output level determined by the value of the analogue final aπplitude reference signal, and linearly α3±ι_Lning the analogue uprairp and down-raπp signals to produce the generated analogue output signal.

17. A method according to claim 16, wherein the analogue up-ramp and down-raπp signals are derived from a digital reference signal,

SUBSTITUTESHEET the reference signal coπprising digital values representing points on a staircase raπp waveform extending between zero and a ^***ax___πum value, the duration of the reference raπp waveform being the same as the duration of the raπp segment to be generated.

18. A method according to claim 17, wherein the digital reference signal is a continuous signal conprising alternate up-raitps and down-raπps.

19. A method according to any of claims 15 to 18, wherein the cx_τιbi_r_ng of the analogue up-raπp and down-raπp signals ccπprises si-mming the signals.

20. Apparatus for generating an analogue waveform signal from a digitally encoded signal, the digitally encoded signal conprising a sequence of digital values representing aπplitude levels at points in the waveform, the apparatus coπprising means for supplying the aπplitude levels for each adjacent pair of points in the sequence, each pair of aπplitude levels representing end points of a segment of the wave to be generated, means for generating for each segment a digital reference signal in the form of digital values representing points on a sta rcase raπp waveform, the staircase raπp having a duration equal to the duration of the segment to be generated, and the staircase ramp extending between a zero reference value and a maximum value, the apparatus further coπprising a raπp segment generator coupled to the supply means and to the reference generator, for generating an output analogue signal in the form of an analogue ramp segment extending between the end points represented by the pair of aπplitude levels.

21. Apparatus according to claim 20, v^*here_Ln the ramp segment generator includes means for producing for each segment an analogue down-ramp signal extending from a first output level to a zero reference level, the first output level being

by the value of the initial amplitude level of the segment, means for producing for each segment an analogue up-raπp signal

SUBSTITUTESHEET simultaneously with the down-raπp signal, the up-raπp signal extending from a zero reference level to a second output level determin€-d by the first aπplitude level of the segment, and coπbining means for linearly combining the analogue up-raπp and down-raπp signals to produce the output segment.

22. Apparatus according to claim 20 or 21, wherein the reference signal generator coπprises a digital counter, and clock means for clocking the counter to repeatedly increment or decrement the counter.

23. Apparatus according to claim 20, 21 or 22, wherein the ra p segment generator has first and second analogue inputs for .inputting the values of the end point amplitude levels of the segment to be generated, the apparatus further conprising first and second reference digital to analogue converter means for converting each pair of digitally encoded aπplitude points into corresponding analogue reference signals for input to the raπp segment generator.

24. Apparatus according to claim 23, wherein the means for producing the up-raπp signal and the means for producing the down-ramp signal together comprise first and second output digital-to-analogue converter means.

25. Apparatus according to claim 24, wherein the digital reference generator generates up-raπps and down-raπps, and when the reference signal is a digital down-ramp signal, the first output digital to analogue converter means produces the down-raπp analogue signal and the second output digital to analogue converter means produces the up-raπp analogue signal, and when the reference signal is a digital up-raπp signal, the first output digital to analogue converter means produces the up-raπp analogue signal and the second digital to analogue converter means produces the down-raπp analogue signal.

26. Apparatus according to claim 24 or 25, wherein the digital

SUBSTITUTESHEET input of the first output digital to analogue converter means is coupled to the digital reference input of the raπp segment generator, the converter means including means for controlling the level of the output signal from the first output digital to analogue converter means to vary between zero when the digital input is zero, and a peak level when the digital input equals the iipaximum value.

27. Apparatus according to claim 26, wherein the first output digital to analogue converter means has an analogue upper reference input for setting the output level when the digital input equals the max-Lmum value, and the output from the first reference digital to analogue converter means is coupled to the analogue upper reference input.

28. Apparatus according to claim 24, 25, 26 or 27, wherein the digital input of the second output digital to analogue converter means is coupled to the digital reference input of the ramp segment generator, the converter means including means for controlling the level of the output signal from the second output digital to analogue converter means to vary between zero when the digital input equals the πaximum value, and a peak level when the digital input is zero.

29. Apparatus according to claim 28, wherein the second output digital to analogue converter means has an analogue upper reference input for setting the output level when the digital input equals the πexiπium value, and a lower reference level for setting the output level when the digital input is zero, the upper reference input being coupled to the zero reference level, and the lower reference input being coupled to the output from the second reference digital to analogue converter means.

30. Apparatus according to any of claims 24 to 29, wherein the supply means includes controlling means responsive to the digital reference signal generator for sending digital values representing

SUBSTITUTESHEET the inital and final end point aπplitude levels to the first and second reference digital to analogue converter means, respectively, when the reference signal is about to start an up-raπp, and for sending the digital values representing the initial and final end point aπplitude levels to the second and first reference digital to analogue converter means, respectively, when the reference signal is about to start a down-raπp.

31. Apparatus according to claim 30, wherein the digital reference generator generates a continuous waveform which coπprises alternate up-ramps and down-ramps.

32. Apparatus according to claim 31, further conprising first and second data latches for buffering the digital inputs to the first and second reference digital to analogue converter means, the controlling means feeding the digital aπplitude values alternately to the first and second latches.

33. Apparatus according to any of claims 20 to 32, wherein the cx-rrbining means coπprises summing means for summing the up-raπp and down-ramp analogue signals.

34. A method for generating an analogue waveform signal from a digitally encoded signal, the digitally encoded signal comprising a sequence of digital values representing aπplitude levels at points on the waveform, the method comprising supplying the aπplitude values of each pair of adjacent points in the sequence, the pair of aπplitude levels representing end points of a segment of the waveform to be generated, generating for each segment a digital reference signal in the form of digital values representing points . on a staircase raπp waveform, the raπp having a duration equal to the duration of the segment to be generated and the ramp extending between a zero reference value and a maximum value, the method further conprising deriving from the reference signal and the aπplitude levels for each segment an analogue output signal in the form of a raπp segment extending between the end points represented

SUBSTITUTE SHEET by the pair of aπplitude levels.

35. A method according to claim 34, wherein the generation of the raπp segment includes producing for each segment an analogue down-ramp signal extending from a first output level to a zero reference level, the first output level being determined by the value of the initial amplitude level for the segment, producing an analogue up-rairp signal simultaneously with the down-raπp signal, the up-ramp signal extending from a zero reference level to a second output level deteππined by the first aπplitude level for the segment, and linearly combining the analogue up-raπp and down-raπp signals to produce the output segment.

36. A method according to claim 34 or 35, further including converting the digital values of each pair of adjacent points into co-_respoι^*-±Lng analogue aπplitude signals which represent the initial and final aπplitude levels of the segment.

37. A method according to claim 34, 35 or 36, wherein the digital reference signal is a continuous signal coπprising alternate digital up-raπps and digital down-ramps.

38. A method according to claims 34, 35, 36 or 37, wherein the cc-τt)iι_ing of the analogue up-raπp and down-raπp signals coπprises summing the signals.

39. Apparatus for generating an analogue signal in the form of a line segment extending from a first digitally encoded aπplitude level to a second digitally encoded amplitude level, conprising means for converting the first digitally encoded aπplitude level to an analogue first reference signal, means for converting the second digitally encoded amplitude level to an analogue second reference signal, digital counting means for generating digital values representing points on a line extending between zero and a maximum value, means for converting the digital values to a third analogue signal, and to a fourth analogue signal ccπplementary to the third

SUBSTITUTESHEET analogue signal, means for controlling the aπplitude of the third analogue signal in response to the first reference signal, means for controlling the aπplitude of the fourth analogue signal in response to the second reference signal, and means for coπtoining the third and fourth analogue signals to produce the generated analogue signal.

40. Apparatus according to claim 39, wherein the digital ∞unting means coπprises a digital counter and means for incrementing or decrementing the value in the counter to generate the sequence of values.

41. Apparatus according to claim 39 or 40, wherein the counter counts t_hrough 256 values between the zero and maximum values.

42. Apparatus according to claim 39, 40 or 41, wherein the line is a straight line.

43. A method of generating an analogue signal in the form of a line segment extending from a first digitally encoded aπplitude level to a second digitally encoded aπplitude level, comprising converting the first digitally encoded aπplitude level to a first analogue reference level, converting the second digital aπplitude level to a second analogue reference level, using a digital counter to generate a sequence of digital values representing consecutive points on a line extending between zero and a π__-ximum value, converting the digital values to a third analogue signal and to a fourth analogue signal cαrplementary to the third analogue signal, controlling the aπplitude of the third analogue signal in response to the first reference signal, controlling the aπplitude of the fourth analogue signal in response to the second reference signal, and combining the third and fourth analogue signals to produce the generated analogue signal.

44. A method according to claim 43, wherein the line is a straight line.

^SUBSTITUTESHEET

45. Apparatus according to any of claims 1 to 14, or 20 to 33, or 39 to 42, wherein the generated analogue output signal is an audio signal.

46. A method according to any of claims 15 to 19, or 34 to 38, or 43 wherein the generated analogue output signal is an audio signal.

SUBSTITUTESHEET