WO1991005408A1

WO1991005408A1 - Injector control

Info

Publication number: WO1991005408A1
Application number: PCT/EP1990/001607
Authority: WO
Inventors: Thierry Meunier
Original assignee: Deutsche Thomson-Brandt Gmbh
Priority date: 1989-09-30
Filing date: 1990-09-21
Publication date: 1991-04-18
Also published as: AU6422290A; DE3932792A1

Abstract

Injector control for integrated circuits. When several signals are taken further within a I2L circuit at the same time, a logic in tree-like structure is used to control the corresponding gates on account of a maximum fan-out of 4. This control method is, however, slow and requires a correspondingly greater chip area. The use of injector-controlled switches, the injectors of which are integrated into a common injector on the chip enables the signals to be controlled rapidly and with the use of a small chip area through the current control of this common injector. For I2-L technology integrated circuits.

Description

Injector control

The invention relates to an injector control for integrated circuits.

For certain purposes, it is necessary to adapt a circuit family, for example I2L circuits, at the inputs or outputs to another circuit family, for example TTL circuits, in order, for example, to use one TTL control signal to produce several I2L output signals switch on simultaneously. ^• An example of this can be found in "Handbook of digital circuits", EA Zuiderveen, 1981, Francis-Verlag, Munich, pages 96 and 97. I2L means: I-Quadrat-L, integrated injection logic. I2L circuits require only a very small chip area and have short switching times. An I2L switching element consists of an npn transistor, which functions as a switch, and a pnp transistor, which functions as a current source.

In I2L circuits, however, the number of parallel outputs per transistor is normally limited to four. If the logic state of many I2L circuit outputs is to be switched on at the same time, control logic is required for the I2L circuit output transistors with a correspondingly large number of parallel outputs. Because of the limitation of the number to four, a known control logic has a ne tree structure with a corresponding time delay due to several cascaded logic gates (Fig.l).

The invention is based on the object of specifying a method and a circuit for the simultaneous switching of signals of a plurality of I2L circuit outputs with a short time delay within an I2L circuit. The input signal of the logic control does not have to be compatible with I2L technology.

This object is solved by the features specified in patent claim 1. ^■. Advantageous developments of the invention are described in the subclaims.

The solution is that electronic switches in I2L technology are connected to corresponding outputs of an I2L logic on the same circuit substrate, which can be switched via a common control input. The input signal of the control input and the I2L-compatible output signals of the electronic switches together form an 'AND' logic.

An exemplary embodiment of the invention is explained below with reference to the drawings. These show in:

Fig. 1 outputs a known switch control for I2L logic

Fig. 2 shows a switch control according to the invention for I2L logic outputs

1 shows an integrated circuit (1) using I2L technology. A logic block (10) with one or more inputs (15) and one or is located on the circuit (1) several outputs (16), which internally has several outputs (171 to 176) at one point, which are to be switched simultaneously and with a short delay to the respective internal inputs (181 to 186).

For this purpose, a gate (111 to 116) is arranged between an internal output (171 to 176) and a corresponding internal input (181 to 186). The gates (111 to 116) are actuated by a control signal (14) which is supplied to the integrated circuit (1) from the outside. The control signal (14) is first converted in a converter circuit (12) to be I2L-compatible and controls a first gate (131), this first gate (131), further gates (132 and 133), and finally these further gates (132 and 133) Gate (111 to 116) on. The control signal (14) and the input signals of the gates (111 to 116) together with the output signals of the gates (111 to 116) form a logical 'AND' function. This means that the output signal of one of the gates (111 to 116) only has the logical value 'true' or '1' if both the input signal of the corresponding gate (111 to 116) and the control signal (14) have the logical value 'true' or '1'. In all other logical combinations of the input signals of the corresponding gate (111 to 116), the output signal of the corresponding gate (111 to 116) has the logical value 'false' or '0'.

Because an I2L gate can normally only drive a maximum of four other gates, a first gate (131) is not sufficient to directly drive six gates (111 to 116), for example. Additional gates (132 and 133) must therefore be interposed, but these cause a time delay in the action of the control signal (14) and require additional space on the substrate of the circuit (1). FIG. 2 shows a circuit (2) according to the invention corresponding to the circuit (1) from FIG. 1. Logic block (20) corresponds to logic block (10), internal outputs (271 to 276) correspond to internal outputs (171 to 176), internal inputs (281 to 286) correspond to internal inputs (181 to 186), control signal ( 24) corresponds to control signal (14) and input signal (25) or output signal (26) corresponds to input signal (15) or output signal (16).

Electronic switches (211 to 216) in I2L technology are arranged between the internal outputs (271 to 276) and the internal inputs (281 to 286), which have a common injector line (234) which is connected to a current source ( 232) and a switch (231) is connected. The switch (231) is controlled by the control signal (24) adapted in a converter circuit (22), which advantageously does not have to be I2L compatible. Depending on its switching state, a current I (233) flows from a current source (232) into the injector line (234) or to ground. Correspondingly, the electronic switches (211 to 216) pass on the signals of the internal outputs (271 to 276) to the internal inputs (281 to 286) or block them. The control signal (24) and the input signals of the electronic switches (211 to 216) together with the output signals of the electronic switches (211 to 216) again form a logical 'AND' function.

Due to the omission of control gates connected in series (corresponding to 131 to 133 in FIG. 1) for the control of the electronic switches (211 to 216), the delay between the control signal (24) and the reaction of the electronic switches (211 to 216) advantageously shortened. In particular in the case of a large number of electronic switches (211 to 216) to be controlled, the area required for their control is on the substrate of the circuit advantageously significantly smaller than for the known circuit (1) according to FIG. 1.

By means of the common injector line (234) of the electronic switches (211 to 216), the signals of the internal outputs (271 to 276) can advantageously be simultaneously sent to the internal inputs (281 to 286) without additional substrate area for control gates. forwarded if the signals of the internal outputs (271 to 276) are partially or totally inverted.

In this case, the circuit according to FIG. 1 would have to accept the simultaneous forwarding of the signals of the internal outputs (171 to 176) and / or additional gates for time compensation with corresponding space requirements in the control logic would be required ( Gates 131 to 133) or to adapt the logic function. _*

Claims

Patent claims

1. A method for essentially simultaneously controlling a plurality of signals within an integrated logic circuit (2), in each of which a transistor function of a logic gate forms a current injector for a second transistor function in this logic gate, the signals from outputs of logic Gates (271 to 276) within the logic circuit are forwarded on the basis of a control signal (24) by components (211 to 216) to corresponding inputs of logic gates (281 to 286) within the logic circuit (2) in accordance with a logic function and each component (211 to 216) is assigned to one of these outputs (271 to 276) or inputs (281 to 286), characterized in that each component (211 to 216) can be controlled by an injector and the injectors ¬ ren of the components (211 to 216) to a common injector (234) are connected, which, triggered by the control signal (24), the components (211 to 216) stale ¬ tet.

2. The method according to claim 1, characterized in that the signals at the input of the components (211 to 216) together with the control signal (24) and the signals at the output of the "components (211 to 216) an 'AND' logic function form.

3. The method according to claim 1 or 2, characterized in that the components (211 to 216) actuated by the common injector (234) are switched between the functions "let through" or "block". Integrated circuit (2) for a method according to one or more of the preceding claims, in which outputs of logic gates (271 to 276) within the circuit (2) by switches (211 to 216) with corresponding inputs of logic Gates (281 to 286) are connected, each switch (211 to 216) having an injector and the injectors of the switches being connected to a common injector (234) which, triggered by a control signal (24 ), the switches (211 to 216) switch essentially simultaneously into a pass or blocking state.