Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
  • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
  • G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
  • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
  • H03M7/3002—Conversion to or from differential modulation
  • H03M7/3004—Digital delta-sigma modulation
  • H03M7/3015—Structural details of digital delta-sigma modulators
  • H03M7/3031—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path
  • H03M7/3042—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator being of the error feedback type, i.e. having loop filter stages in the feedback path only
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
  • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
  • H03M7/3002—Conversion to or from differential modulation
  • H03M7/3004—Digital delta-sigma modulation
  • H03M7/3015—Structural details of digital delta-sigma modulators
  • H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
  • H03M7/3024—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
  • H03M7/3028—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a single bit one

Definitions

• the invention relates to a system for converting a PCM input signal with uniform noise spectrum, comprising a series of digital words each of K-bits appearing with a predetermined repetition frequency, into an PCM output signal with a non-uniform noise spectrum comprising a series of digital words each of L-bits, L being small than K
• system comprises at least a 1-bit coder embodied to provide a shaped noise profile and to convert the K-L least significant bits of each word from the input signal into a series of 1-bit words, and an accumulator for combining said 1-bit words with the L most significant bits resulting into the desired
• the therein described system comprises besides the already mentioned 1-bit coder a second 1-bit coder which is used for coding the residual value words generated by the first 1-bit coder.
• the resulting series of 1-bit words is, after differentiation in a thereto suitable circuit, combined with the series of signals at the output of the first summing circuit and is thereafter supplied to a filter to filter out the desired baseband.
• the second 1-bit coder operates at a frequency which is a multiple of the repetition frequency the PCM input signal.
• the cascade circuit provides a shaping of the quantization noise with a spectrum having a slope of +12 dB/octave.
• An object of the invention is now to indicate in which manner, especially for videotransmission applications, use can be made of 1-bit coders for processing an PCM video input signal in such a manner that a reduction of the necessary transmission bandwidth can be realized thereby maintaining, however, an acceptable perception quality and without the necessity to use very high switching frequencies.
• the invention now provides a system for converting a PCM input signal with uniform noise spectrum, comprising a series of digital words each of K-bits appearing with a predetermined repetition frequency, into an PCM output signal with a non-uniform noise spectrum comprising a series of digital words each of L-bits, L being small than K
• system comprises at least a 1-bit coder embodied to provide a shaped noise profile and to convert the K-L least significant bits of each word from the input signal into a series of 1-bit words, and an accumulator for combining said 1-bit words with the L most significant bits resulting into the desired PCM output signal, characterized in that the frequency with which said K-L least significant bits of the words of the input signal are converted by said 1-bit coder is equal to said earlier mentioned repetition frequency.
• the system according to the invention does not use oversampling.
• the used apparatuses do not have to be adapted in any way.
• the signal, received at the reception end through the transmission path can be processed by the usual PCM decoder.
• the transmission side relatively low switching frequencies are necessary in the coder, because in principle these switching frequencies are equal to the repetition frequency in the PCM input signal.
• An important additional advantage is that, when the invention is applied, after a bit error on the transmission path no bit error propagation will occur, in contrast to other prior art systems for restricting the number of bits in a videosignal. Bit error propagation will in general lead to annoying disturbing lines in the displayed picture. Said disturbing lines will not appear when the invention is applied, because an eventual bit error has at the very worsed only influence on one single pixel.
• the invention uses the fact that the human eyesight as it were comprises a filter for higher video frequencies. In a videosignal the larger part of the relevant information which is observable for the human eye is situated in the lower frequency section of the base band. Disturbing signals or noise in the higher frequency section of the baseband are not or hardly visible if the video information is displayed to a viewer.
• the invention provides in this respect a system which furthermore comprises a second 1-bit coder, embodied to provide a shaped noise profile and to convert the residual words, which are generated together with said 1-bit words in the first 1-bit coder into a second series of 1-bit words, a differential stage for differentiating the second series of 1-bit words and a second accumulator circuit in which the differentiated 1-bit words are combined with the words produced by the first accumulator to obtain the desired PCM output signal, which system according to the invention is characterized in that also the frequency with which the residual words are converted by said second 1-bit coder is equal to said earlier mentioned repetition frequency.
• This embodiment provides a "noise-shaping" of 12 dB/octave. Further embodiments and therewith obtained advantages will be discussed in more detail with reference to the attached drawings. The invention will be explained in more detail with reference to the attached drawings.
• Figure 1 illustrates a first embodiment of a system according to the invention comprising a 1-bit coder yielding into a noise profile with a slope of 6 dB/octave.
• Figure 4 illustrates an embodiment of a system according to the invention comprising two cascaded 1-bit coders, by means of which a profile of 12 dB/octave can be realized.
• Figure 5 illustrates a further development of the system according to figure 4.
• Figure 6 illustrates a number of different ways to process the information concerning pixels in a video image, using the system according to the invention.
• Figure 7 illustrates a system destined to carry out the processes of which examples are illustrated in figure 6.
• Figure 8 illustrates a simplified embodiment of a system for carrying out the processes of the type illustrated in figure 6.
• Figure 1 illustrates a first simple embodiment of a system according to the invention.
• the system comprises a register 10 for intermediately storing a series of PCM input words, supplied through the transmission path 11.
• the register is clocked with a frequency f «, which is also the repetition frequency of the K-bit words in the PCM input signal.
• f the K-bits of each word are separated in the L most significant bits and the K-L least significant bits.
• the K-L least significant bits are subjected to a coding operation using a 1-bit coder 12.
• the coder 12 contains therefore a summing means 13 and a feedback register 14.
• Each word of K—bits, supplied to the circuit 12, is in the summing means 13 added to a word derived from the register 1 .
• the K-L least significant bits of the resulting sum word are supplied again to register 14 and are temporarily stored therein whereas the most significant bit (the carry bit) f-unctions as output signal of the 1-bit coder 12 and is supplied to a further summing means 15, in which this 1-bit carry signal is combined with the L most significant bits of the PCM input signal.
• the sum signal resulting therefrom forms in fact the desired PCM output signal, which is supplied to the output transmission path 16.
• This PCM output signal comprises words of L-bits.
• the result of the operation in the system according to figure 1 is therefore a reduction of K-bits per word to L-bits per word (L ⁇ K) . Because the system uses no oversampling the incoming PCM signal on the transmission path 11 as well as the outgoing PCM signal on the transmission path 16 are situated within the baseband which extends between 0 Hz and 1/2 f» Hz.
• the register 14, which is clocked with the same repetition frequency f « as the register 10, functions together with the summing means 13 in fact as a first order feedback filter.
• the result of the filter operation, which is carried out by this first order filter, is that the uniform noise spectrum in the K-bit PCM input signal in the input transmission path 11 is converted into a non-uniform noise spectrum on the output signal on the output path 16, which spectrum has an inclining character with a slope of 6 dB/octave.
• the figures 2A and 2B supply more details about the noise power density S in the resulting PCM signal on the output transmission path 16. Both figures provides in essence the same information, however, with the difference that in both figures differing scale divisions are applied.
• a linear scall division is selected both for the horizontal axis as well as for the vertical axis.
• figure 2B the same curves as in figure 2A are illustrated, however, in this case with a logarithmic division along both the horizontal axis and the vertical axis.
• the power density S is plotted against the frequency for a number of different situations which will be discussed hereinafter.
• the linear curve I applies for the situation that the 1-bit coder does not carry out any filter operation. In that case a uniform noise spectrum over the complete frequency range will result. In figure 2A it is assumed that in that case the noise power density has value P. In figure 2B the corresponding curve I coincides with the 0-dB line.
• the power density level of the noise in the lower frequency section of the baseband is strongly decreased.
• FIG. 3 An improvement of the already very useful system according to figure 1 can be realized by steepening the slope in the noise profile, in other words, by effecting a stronger shift of noise power to the higher frequencies.
• a 1-bit coder with stronger filter action is illustrated in the figure 3.
• the coder 22 in figure 3 comprises between the input 20 and the output 21 a summing means 19, a first adder 23, a second adder 24, a comparator 26 and a time delay element 25.
• the sum signal of the first adder 23 is fed back through the time delay element 27 to the second input of the adder 23.
• the sum signal of the adder 24 is through a time delay element 28 and through an attenuation element 29 supplied to the second input of the adder 24.
• the output signal of the time delay element 25 is fed back to the summing point 19.
• a filter function as realized which in the Z-transform can be written as (l-Z -1 ) -1 .
• the second loop comprising the adder 24, the delay element 28 and the attenuation element 29 also realizes a filter function which, in the Z-transform can be written as (1-aZ- n ) _1 . If for "a" a value is selected within the range 0 ⁇ a s 1/2 then a noise shaping with a slope of 9 dB/octave will be obtained when this 1-bit coder is applied. In the figures 2A and 2B the possible noise profile is indicated by the curve III.
• FIG. 2B The improvement of the noise profile is specifically clear in figure 2B. From the state of the art (US 4,593,271) a cascade circuit is known comprising two 1-bit coders in a series circuit. A similar cascade circuit can also be used within the scope of the invention.
• Figure 4 illustrates an embodiment which will be discussed in more detail hereinafter.
• FIG 4 a series circuit is illustrated of two 1-bit coders 32 and 42, both comprising a register 34, respectively 44 and both comprising an adder 33, respectively 43. Furthermore the system comprises an input register 30 destined to temporarily store the K-bit input words which will be supplied through the input transmission path 3 . Both the register 30 as well as the registers 34 and 44 are clocked with the same clock pulse frequency f «. which clock pulse frequency is equal to the repetition frequency which is used in the PCM input signal. Just like the register 10 in figure 1 , also the register 30 takes care of separating the K-L least significant bits from the L most significant bits.
• the K-L least significant bits are supplied to the 1-bit coder 32 and the functioning of this part of the circuit in figure 4 is completely identical to the function of the coder 12 in figure 1.
• the carry bit at the output of the adder 33 is, in a similar manner as in figure 1, supplied to the adder 35 and combined with the L most significant bit resulting into a new L-bit output signal which, as is illustrated in figure 4 is supplied to the adder 36.
• the output signal of the adder 33 is supplied to the second 1-bit coder 42.
• this 1-bit coder 42 the signal is again subjected to a 1-bit coding operation and the therefrom resulting carry bit is supplied to a filter circuit 37 formed by a register 38 and a subtractor 39.
• the circuit 37 carries out the filter function (1-Z ⁇ 1 ).
• the two bits resulting therefrom are combined in the adder 36 with the output signal of the adder 35 resulting into the desired PCM output signal of L-bits, which is delivered to the output transmission path 40.
• the register 38 is clocked with the same repetition frequency f» with which also the words in the input signal on the input transmission path 31 are supplied.
• the 1-bit coder 42 can be replaced by an embodiment of a coder as illustrated in figure 3.
• a coder as illustrated in figure 3.
• an even steeper increase of the noise profile can be realized with a slope of +15 dB/octave.
• the noise profile which is obtained in that case is illustrated with the curve V in the figure 2A and 2B.
• the figures 3 and 4 offer enough support for the expert in this field to enable him to realize such a circuit and therefore this embodiment is not illustrated in a separate figure.
• the embodiment of figure 5 is for the major part identical to the embodiment in figure 4.
• the first difference is to be found in the signal path along which the residual value words from the 1-bit coder 32 are transported to the 1-bit coder 42.
• a further adder 41 is inserted in this signal path, the purpose of this adder being to add a constant value of an halve bit to the digital values which from the coder 32 are supplied to the coder 42.
• the addition of an halve bit is carried out by alternatively adding nothing and adding a least significant bit to the words in the signal string.
• a further difference between figures 4 and 5 is formed by the application of only one single summing means 35/36 instead of both adders 35 and 36 in figure 4. It will be clear that the combination of both adders may lead to an hardware saving. It is furthermore remarked that with the application of the circuit according to figure 5 there is not correlation anymore between the quantization noise and the input signal.
• FIG 6 some image lines K, L, M and N are schematically illustrated, being positioned directly underneath each other.
• the pixels in each line are arranged in vertical columns, of which the columns 10 until 20 are illustrated in figure 6.
• FIG 6A in a PCM television signal, configurated according to the generally accepted television standard, successive words are received which are representing the pixels K10, K11, K12 ,
• the circuit 81 can be a circuit as illustrated in figure 1, figure 3, figure 4 or figure 5, being a circuit suitable for converting the K-bit words, supplied through the route 80, into L-bit words which are delivered to path 82.
• the addressing units 85 respectively 86 related to each image memory 75, respectively 76 are functioning preferably such that during the storing of PCM words related to a new image in the respective image memory locations are addressed in a predetermined order such that the words are successively stored in the normal frame order. After storing these words, related to a complete image, in the memory said words are read out during the following image reception period, whereby the order in which they are read out, can be different from the order in which they were stored, dependent on the manner in which the operation has to be carried out.
• the related memory for instance 75
• the corresponding addresssing 85 such that successively the PCM words corresponding to the pixels K10, L10, M10, N10, K11 , L11 , M11 , N11 , are read out and supplied through the path 77, the multiplexer 79 and the path 80 to the conversion system 81.
• the respective other memory in this example the memory 76 is through the multiplexer 72 and the path 74 loaded with PCM words which are related to the next image and which are received through the path 71.
• the L-bit words at the output of the circuit 81 are not appearing in the correct time sequence for controlling a television receiver.
• the words through the path 82 supplied to a further multiplexer 83 which sends all words, related to a complete image, through route 87 to a memory 88 or through route 89 to a memory 90.
• the one memory (88 or 90) is filled, the respective other memory (90 or 88) is read out and the read out information is through the path 91 or 92 and through the multiplexer 93 supplied to the output path 94.
• Both memories 88 and 90 are respectively addressed by addressing units 95 and 96.
• FIG 6C schematically an operation in diagonal direction is illustrated.
• the related addressing unit 85, 86 is operating such that successively the words related to the pixels
• K10, L12, M14, N16 K11 , L13, M15, N17 are supplied to the system 81 then an oblique image operation is obtained in the direction of the arrow 54 in figure 6D.
• a possible pattern operation is illustrated in figure 6E by means of the arrows 55 and 56.
• the pixels are read from the respective image memory 75 or 76 in the order K10, L11, K12, L13, K14, L15, L10, M11, L12, M13, L14, M15, Therewith an operation both in horizontal direction as well as in vertical direction is obtained.
• figure 7 illustrates a generally applicable circuit this circuit has the disadvantage of four relatively large image memories necessary to obtain proper functioning of the circuit. These image memories are not necessary in all cases. Dependent on the desired operation direction it is possible to apply much simpler circuits.
• Figure 8 illustrates a circuit which shows lots of correspondences with the circuit in figure 1.
• the components 10, 11, 12, 13, 15 and 16 are also present in figure 8 and have in principle the same function as in the circuit according to figure 1.
• the difference between figure 1 and figure 8 is found in the register which is present in the coder 12.
• a 1-bit register 14 was used whereas in figure 8 an n-stage shift register 100 is used.
• This shift register 100 is clocked again with a frequency f « being equal to the repetition frequency of the K-bit words in the incoming PCM input signal. If the number of stages n in the shift register 100 is equal to the number of pixels or picture elements in one complete image line then the coding process in the coder 12 will be applied to the K-L least significant bits of a predetermined pixel and the residual value of the pixel positioned vertically above. Said last mentioned residual value is in fact delayed over one line period in the register 100. Instead of a large number of relatively large scale components in the circuit according to figure 7 it is therefor possible with only one n-stage shift register 100 to carry out a coding operation in vertical direction.
• the K-L bits of each word will be combined with the residual value with the word corresponding to the diagonally higher positioned pixel.
• an operation in diagonal direction is carried out.
• An operation in the other diagonal direction can be realized in case the number of stages n in the shift register 100 is selected equal to the number of pixels in a complete image line -1 pixel. If the number of stages n in the shift register 100 is selected to such a value that in the shift register a delay of one complete image can be realized then in fact the operation is carried out on corresponding pixels in successive images. Therewith an averaging of the image information is obtained which especially will lead to a sharpening of the image contours, improving therewith the quality of the image.
• the number of stages n of the shift register 100 is also possible to select the number of stages n of the shift register 100 equal to the number of pixels in a complete image +1 pixel or -1 pixel, in which case a horizontal direction of operation is created on pixels belonging to successive images.
• a vertical direction of operation on pixels of successive images can be obtained in case the number of stages n in the shift register 100 is selected equal to the number of pixels in a complete image plus the number of pixels in an image line.
• a video information is assumed which is structured according to a generally accepted TV-standard, according to which standard the image is built up from frames whereby each frame comprises a number of horizontal lines.
• video information which is structured according to a completely different standard, for instance video information which is configures as in radar systems, display systems etc.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• Multimedia (AREA)
• General Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• Mathematical Physics (AREA)
• Signal Processing (AREA)
• Compression, Expansion, Code Conversion, And Decoders (AREA)
• Analogue/Digital Conversion (AREA)
• Television Systems (AREA)
• Radar Systems Or Details Thereof (AREA)
• Details Of Television Scanning (AREA)
• Compression Or Coding Systems Of Tv Signals (AREA)
• Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

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• 1989
  • 1989-11-07 NL NL8902751A patent/NL8902751A/nl not_active Application Discontinuation
• 1990
  • 1990-09-20 DK DK90914245.7T patent/DK0493466T3/da active
  • 1990-09-20 ES ES90914245T patent/ES2053204T3/es not_active Expired - Lifetime
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  • 1990-09-20 US US07/838,739 patent/US5283577A/en not_active Expired - Fee Related
  • 1990-09-20 DE DE69008731T patent/DE69008731T2/de not_active Expired - Fee Related
  • 1990-09-20 EP EP90914245A patent/EP0493466B1/en not_active Expired - Lifetime
  • 1990-09-20 WO PCT/NL1990/000137 patent/WO1991004611A1/en active IP Right Grant

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