WO1991002395A1 - Indicateur de defaut adaptatif de courant - Google Patents

Indicateur de defaut adaptatif de courant Download PDF

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Publication number
WO1991002395A1
WO1991002395A1 PCT/US1990/004396 US9004396W WO9102395A1 WO 1991002395 A1 WO1991002395 A1 WO 1991002395A1 US 9004396 W US9004396 W US 9004396W WO 9102395 A1 WO9102395 A1 WO 9102395A1
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WO
WIPO (PCT)
Prior art keywords
current
trip
circuit
voltage
capacitor
Prior art date
Application number
PCT/US1990/004396
Other languages
English (en)
Inventor
Thomas Yeh
Original Assignee
Sigma Instruments Division
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/390,541 external-priority patent/US5029039A/en
Priority claimed from US07/505,483 external-priority patent/US5115031A/en
Application filed by Sigma Instruments Division filed Critical Sigma Instruments Division
Publication of WO1991002395A1 publication Critical patent/WO1991002395A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/08—Locating faults in cables, transmission lines, or networks
    • G01R31/081—Locating faults in cables, transmission lines, or networks according to type of conductors
    • G01R31/083—Locating faults in cables, transmission lines, or networks according to type of conductors in cables, e.g. underground
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
    • G01R19/16538—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
    • G01R19/16585—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 for individual pulses, ripple or noise and other applications where timing or duration is of importance
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/02—Details
    • H02H3/04—Details with warning or supervision in addition to disconnection, e.g. for indicating that protective apparatus has functioned
    • H02H3/042—Details with warning or supervision in addition to disconnection, e.g. for indicating that protective apparatus has functioned combined with means for locating the fault
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/44—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to the rate of change of electrical quantities

Definitions

  • This invention relates to faulted current indicators, and particularly to fault indicators which can accommodate themselves to wide variations of load conditions in a distribution network.
  • a conventional fault indicator indicates the passage of power cable current above a predetermined magnitude, i.e. trip current.
  • the fault indicator's trip current is selected to be greater than the expected current at the installation site. Proper selection of the trip current magnitude is very important for the proper application of fault indicators.
  • the trip current is selected about two to three times the maximum load current and less than one half the available fault current. This method of application provides a good trade off between maximum sensitivity while minimizing the un-wanted trips by periodic overloads.
  • Applying conventional fault indicators in a large distribution network often requires many fault indicators with different trip currents to coordinate with loading variations within the network. In addition to the cost of stocking many different fault indicators, the chance of miss- application also increases.
  • An object of the invention is to overcome these difficulties.
  • Another object of the invention is to furnish reliable fault indicators capable of adapting the trip to the load current of a power line to accommodate the wide variations in load condition of a distribution network.
  • such objects are achieved with fault indicating method and means by tripping the fault indicator in response to increases in currents in the cable over time.
  • An example of such an increase is 50 amperes within 3 line cycles of a 60 Hz current, or 50 milliseconds.
  • the trip signal is held and the trip operation is disabled long enough for a fuse or circuit breaker to open in response to a fault, and then the trip operation enabled only if the current then falls to zero.
  • Fig. 1 is a block diagram illustrating an embodiment of the invention.
  • Fig. 2 is a detailed showing of a portion of the circuit in Fig. 1.
  • Fig. 3 is a circuit diagram illustrating details of part of the circuitry in Fig. 1.
  • Fig. 4 are graphs showing the operation of the circuit in Fig. 1.
  • Fig. 5 is a block diagram of another embodiment of the invention.
  • Fig. 6 is a diagram illustrating details of part of the circuitry in Fig. 4.
  • Figs. 7 and 8 are time current diagrams illustrating conditions for tripping the fault indicator.
  • Fig. 9 is a block diagram illustrating another embodiment of the invention.
  • Fig. 10 is a schematic diagram illustrating yet another embodiment of the invention.
  • Fig. 1 illustrates an embodiment of the invention.
  • a power source PS energizes a load LO through a circuit breaker CB and a power cable PC.
  • Fault indicators FIl, FI2, FI3, and FI4 inductively coupled to the cable PC by inductive sensors IS1, IS2, IS3, and IS4 at spaced locations along the cable PC, sense whether a fault exists at positions between any fault indicators.
  • the sensors IS1 to IS5 may be regarded as part of the fault indicators FIl to FI5.
  • a fault between fault indicator FI4 and fault indicator FI5 trips fault indicators FIl to FI4 while leaving fault indicator FI5 reset. This identifies the location of the fault as being between fault indicator FI4 and fault indicator FI5.
  • the length of the cable PC appears shortened for the purposes of illustration.
  • the inductive sensors IS1 to IS5 produce respective alternating voltages corresponding in amplitude to the amplitude of the alternating currents they sense in the cable PC.
  • a capacitor Cl tunes the inductive sensor IS3 to the frequency in the cable PC.
  • a bridge circuit BR rectifies the alternating current in the sensor IS3 to form an output voltage whose peak is proportional to the current flowing in the power cable 16.
  • Three isolating diodes Dl, D2, and D3 furnish the bridge BR output voltage to a reset circuit RC, a trip circuit TC, and a power circuit PO that furnishes a voltage Vcc to the elements of the fault indicator.
  • the diodes Dl, D2, and D3 isolate the various circuits from each other.
  • a capacitor C2 captures the peak of the rectified output of the bridge BR and smoothes ripple.
  • a 12 volt zener diode Zl regulates the voltage across the capacitor C2 so the latter carries a 12 volt potential that serves as the voltage source Vcc for elements of the circuit in the fault indicator FI3.
  • the reset circuit RC responds to a minimum voltage Vmin at the bridge BR to produce a reset signal.
  • the minimum voltage Vmin corresponds to a minimum current Imin in the cable PC.
  • the reset signal energizes a reset winding WR in a fault display actuator DA which then drives a target (or display) TA to a visibly distinguishable reset position.
  • the trip circuit TC operates in response to the voltage at the bridge BR appearing at the diode D2 and representing the operating current in the cable PC.
  • the trip circuit TC produces a trip signal when the rate of change of current in the cable PC causes the rate of change of the voltage at the bridge BR to exceed a predetermined value, and the cable current thereafter drops to 0 within a predetermined time in response to the current opening the circuit breaker CB.
  • the trip signal energizes a winding W2 in the display actuator DA. The latter turns the target to a trip position.
  • a sample preset time is 1/4 to 1/2 cycles. However for particular purposes other delays are useful. According -to one embodiment of the invention the preset time is 60 seconds.
  • Reset circuits such as circuit RC are well known in the art. They include a threshold circuit to establish the reset signal or signals when the voltage at the bridge BR exceeds the minimum value Vmin.
  • a start up delay circuit DE responds to the onset of the voltage Vcc and a reset signal and produces an inhibiting low at one input of AND gates ADl and AD2 for the preset time such as one-quarter or one half cycles or perhaps 60 seconds. Thereafter, the start up delay circuit DE enables the gates ADl and AD2 until three events occur; the current in cable PC drops to 0 to expunge Vcc, the current resumes to re-produce Vcc, and a reset signal appears at the start up delay circuit DE.
  • the start up delay circuit DE is in the form of a timer responsive to a reset signal followed by a latch that resets in the absence of Vcc and is enabled by the presence of Vcc.
  • the other input of the gate AD2 is connected to the output of the reset circuit RC, and the other input of the AND gate AD2 is connected to the trip circuit TC.
  • the AND gate ADl serves to energize the reset winding Wl when the input signal at both inputs are high.
  • the AND gate AD2 serves to energize the trip winding when both inputs are high.
  • the start up delay circuit DE causes the inhibit signal at the inputs of AND gates ADl and AD2 to last for a given time, such as one-quarter or one- half cycle, and then enables the AND gates ADl and AD2 so they can pass reset or trip signals. In this way the inrush restraint circuit prevents resets or trips in response to inrush currents.
  • the trip circuit produces a trip signal in response to the rate of change of current.
  • an integrator INI integrates the rectified voltage at the bridge BR at a first rate and an integrator IN2 integrates the voltage at a second rate much slower than the first rate.
  • a voltage divider composed of resistors Rl and R2 takes a slightly lower proportion of the output of integrator INI than does a voltage divider composed of resistor R3 and R4 take of the integrator IN2.
  • the effective output of the integrator IN2 measured at the voltage divider R3,R4 produces a slightly higher absolute voltage than the effective voltage of integrator INI measured at voltage divider R1,R2.
  • a comparator UI compares the voltages at divider R1,R2 with the voltages at divider R3,R4. When the voltage at capacitor C2 is changing only slowly, the output of the comparator UI is low because the both integrators' effective outputs respond similarly to their inputs and the effective output of integrator INI is lower than that of integrator IN2. When the voltage at the bridge BR rises rapidly, the lower effective output of faster integrator INI climbs above the effective output of integrator IN2. The comparator UI then produces a high.
  • a latch LAI such as a flip-flop latches the high and applies the high to an input of an AND gate AD3.
  • a timer Til responds to the high and resets the latch after a predetermined time such as one minute. The timer TI thus allows the comparator UI to arm the AND gate AD3 and hence the trip winding WT for only the predetermined time, e.g. one minute.
  • An inverter IV1 produces an inhibit signal at the other input of the AND gate AD3 as long as there exists a voltage at the bridge BR. As soon as the voltage at the bridge BR goes to 0 in response to the circuit breaker CB opening the cable PC the inverter applies a high to the AND gate AD3. If this occurs within the predetermined time, e.g. one minute that the timer Til allows the latch LAI to apply a high to the AND gate AD3 the latter goes high. If this high occurs after the inrush restraint period of the start up delay circuit DE, i.e. after the start up delay circuit places highs on AND gates ADl and AD2, the high at AND gate AD3 causes energization of winding W2.
  • Fig. 2 illustrates details of the integrators INI and IN2 and their environments.
  • a capacitor C2 forms the integrator INI.
  • the time constant of the integrator INI is determined mainly by the capacitor C2 and the effective impedance of the resonant circuit composed of the inductive sensor IS3 and the capacitor Cl which tunes the sensor IS3 to the frequency of the current in the cable PC.
  • the values are chosen so that the voltage Vtrip across the capacitor C2 reaches 95% of the voltage of the bridge BR in about 3 line cycles.
  • the capacitor C2 has a value of 4.7 microfarads and the effective impedance a value 3 Kohm although these values are only examples.
  • a capacitor C3 and a resistor R6 form the second integrator IN2.
  • the capacitor C3 has a values such as 1.0 microfarad while the resistor R6 has a value of 15 Kohms. Because the resistor R6 and the capacitor C3 are both connected to the capacitor C2 and the impedance of the tuned circuit C1,IS3, the time constant of the second integrator IN2 includes the effects of the tuned circuit impedance and the capacitor C2. Hence, the time constant of the integrator IN2 is inherently greater than the time constant of integrator INI.
  • the values of the integrator IN2 are chosen to allow the voltage across capacitor C3 to reach 95% of the voltage at the bridge BR 3 cycles later than the time the voltage across capacitor C2 reaches 95% of the voltage across bridge BR.
  • resistors Rl to R4 affect the time constants of the integrators INI and IN2 only slightly. However their voltage dividing ratios are such as to apply a smaller proportion of the signal at the output of integrator INI than that of integrator IN2. This assures that the f ster input from integrator INI to the non- inverting terminal of the comparator UI is less than the slower input from the integrator IN2 to the inverting terminal as long as the currents sensed are varying slowly enough for both integrators INI and IN2 to follow.
  • the capacitor C2 serves two other functions. It serves to reduce the ripple at the bridge BR and to store a voltage Vtrip for energizing the trip winding WT.
  • Fig. 3 illustrates the manner in which the trip signal energizes the trip winding WT.
  • a field effect transistor Ql has a gate which receives the trip signal from the AND gate AD2.
  • a high trip signal causes current flow from along a path from the voltage Vtrip at the capacitor C2 through the trip winding WT, the drain and source of field effect transistor Q, and ground.
  • a similar arrangement energizes the reset winding at the output of AND gate ADl.
  • the integrators INI and IN2 and the comparator UI may be considered as functioning as a differentiator for that responds only to positive di/dt or dv/dt. They may also be regarded as a differentiator followed by a diode that permits only positive flow.
  • the inductively coupled sensor IS3 senses the current in the power cable PC on a continuous basis.
  • the bridge BR rectifies the output of the current sensor IS3 to obtain unidirectional sine pulses with peak values proportional to the current magnitude in the power cable PC.
  • the integrator IN2 with its capacitor C3 and longer time constant than the integrator INI generates the reference for the comparator circuit UI.
  • the time constant of the integrating circuit IN2 is such that the reference of the comparator represents some time average current of the power cable, for example, three line cycles, or 50 milliseconds.
  • the time constant of the integrating circuit INI is less than that of IN2.
  • the effective output of the integrator INI is slightly lower than the integrator IN2 as long as the rate of change in the sensed current is slower than the differences between the charging rates of the capacitors in the integrators INI and IN2. This is so because then both integrating circuits INI, and IN2 keep up with the rate of change at the output of the bridge circuit BR.
  • the integrator INI reacts faster than the integrator IN2 and a voltage differential occurs at the inputs of the comparator UI.
  • comparator UI sets the latch LAI and initiates the timer circuit Til and provides a high at the input of the AND gate ND3.
  • An inverter IV1 disables the AND circuit AD3 as long as the bridge circuit BR indicates that current continues to flow in the cable PC.
  • the timer maintains the high at the output of the latch LAI for a predetermined period. If the current in the line PC drops to zero during that period, the inverter IV enables the AND gate AD3 to pass a trip signal to the winding W2.
  • Figs. 4, 5, and 6 demonstrate conditions that will not cause a trip operation.
  • Figs. 7 and 8 show conditions for tripping the fault indicator.
  • the initial "nominal" current II is the relative reference for the fault determination.
  • the current increase from II to 12 is over a relatively long enough period of time (dt) so that its rate of change is insufficient to cause a trip operation.
  • the fault indicator is referenced to 12 for the fault operation.
  • Fig. 5 shows the increase in the magnitude of the current over time.
  • the current remains at 12 after the increase, thereby indicating that the circuit breaker CB did not interrupt the current in the power cable PC and the entire trip condition was not satisfied.
  • Fig. 7 shows the current dropping to zero after reaching 12, thereby indicating the loss of current in the power cable PC, thereby tripping the fault indicator.
  • Fig. 6, shows a condition where the fault indicator adapts to the variations in the load current. Initially, the power cable PC carries current of the level II. Similar to Fig. 4, the current is increasing in response to an increase in load.
  • the reference against which the fault is judged is also changing.
  • the fault indicator is "adapting" to the changing load current.
  • the fault indicator is referenced to 13.
  • the subsequent current increase of 13 to 12 over the time period dt2 is not sufficiently high relative to 13 to arm the trip circuit.
  • Fig. 8 shows the condition where an increase is sufficiently fast relative to 13 to arm the trip circuit.
  • the trip operation occurs when the breeiker CB interrupts the line current after the arming condition.
  • the loss of current represents this in Fig. 8.
  • the adaptive fault indicator operates to trip when the increase of current in the power cable PC, as referenced to the steady state "nominal" load current is sufficiently high and is over a short enough period of time to generate the necessary di/dt value to arm the trip circuit. If the line voltage or current signal is not available, the arming of the trip circuit will cause the target TA to operate to trip. If line current is available, then the line current must also be interrupted within a period of time such as one minute to enable the trip circuit to operate to trip. If the line current is still present after a given time such as one minute, the latch LAI produces a low and then disables the AND gate AD3 so that the trip circuit is disarmed and ready for the next trip condition.
  • the adaptive fault indicator adapts to the nominal loading current of the power line to accommodate the wide variations of load conditions in a distribution network.
  • the fault indicator according to the invention does not react to absolute magnitude of current but instead responds to increase in current over period of time (di/dt) .
  • the adaptive fault indicator uses the nominal load current as a reference to which a relative increase of current such as 50 amperes within a certain amount of time such as three cycles or 50 milliseconds will cause the indicator to trip. Fault indicators according to the invention thus significantly reduce stocking of fault indicators having different trip setting and thus reduce the chances for misapplication. .
  • two events must occur in sequence to cause the indicator to trip, for example a relative increase in current such as 50 amperes within three cycles "arms" the trip circuit.
  • the second event namely the loss of current within a predetermined time, such as one minute. This will trip the indicator. If after one minute the current in the line still persists, the trip circuit will be "disarmed".
  • the timing is chosen to be longer than the opening time of the circuit breaker CB in the power line PC. If the circuit breaker includes a recloser switch, then the time of timer Til should be chosen to be longer than the final lockout time. The purpose of the timer Til is to prevent the fault indicator from responding to current before the line protection device has a chance to operate.
  • the reset circuit RC responds to a current Imin and initiates the start up delay circuit DE in the inrush restraint IR.
  • the time of the delay is preferably short, for example one quarter to one half cycle. However, delay times of 60 seconds are sometimes used for special purposes.
  • the start up delay circuit DE inhibits the AND gates ADl and AD2 at the initiation or resumption of current and prevents the display actuator DA from changing the reset or trip condition of the target TA for the delay time. Thereafter, the start up delay circuit DE enables the AND gate ADl and AD2 and allows them to pass highs to the windings WR and WT.
  • the capacitor C2 serves three purposes.
  • the invention may also be embodied as shown in Fig. 9.
  • a differentiator Dl substitutes for the integrator INI.
  • the differentiator produces signals proportional to the rate of change of the output of the bridge circuit BR.
  • a large rate of change at the output of the bridge circuit BR produces a large output at the differentiator Dl.
  • a smaller rate of change produces a comparatively smaller output.
  • a comparator UI compares the differentiating circuit Dl output to the nominal current based reference in integrator IN2.
  • the integrator IN2 here has a time constant that depends mainly on the members within it.
  • the threshold of the comparator is such that rate of change in current, say an increase of 50 amperes over three cycles, triggers the comparator output. This output arms the trip circuit and initiates the timer circuit Til.
  • the circuits INI and IN2 may be regarded as energy storage devices with different storage rates. In that sense the circuit IN2 has the faster storage rate.
  • the integrator circuits INI and IN2 may also be considered delay circuits having information storage functions with different write delay times. In that sense the circuit IN2 has the longer delay time.
  • the information storage aspects of circuits INI may be replaced for example with semiconductor memories.
  • Fig. 10 Another embodiment of the invention appears in Fig. 10.
  • the sensor SI3 output after fui L wave rectification, is peak detected by capacitor C2.
  • the DC voltage across capacitor C2 is proportional to the current magnitude being sensed by the sensor SI3.
  • the discharge time constant of capacitor C2, determined by resistance of resistor R6 and capacitance of capacitor C2, is much longer than 60 cycles period to hold the information between 60 Hz period.
  • the rate-of-increase of the DC voltage across capacitor C2 is derived by the differentiator circuit composed of capacitor capacitor C3 and resistor R7.
  • capacitor C3 is 1 microfarad and resistor R7 is approximately 50K ohms.
  • the "differentiator" formed by capacitor C3 and resistor R7 has a time constant of approximately three cycles of the 60 Hz signal or 50 milliseconds. When the sensed 60 Hz current exhibits an increase that occurs within three 60 Hz cycles, the voltage across capacitor C2 also exhibits a corresponding increase.
  • the output of the differentiator, at the cathode of zener diode D14 is proportional to the rate-of-increase of the voltage across capacitor C2.
  • the output of the differentiator will overcome the zener diode voltage D14 and turn ON transistor Ql.
  • the collector of transistor Ql will go low and turn on transistor Q2.
  • the collector of transistor Q2 is tied to the SET input of the SET/RESET Flip Flop and initiates the counter IC U3.
  • the counter IC U3 then counts for a predetermined time period. During this period the trip circuit is enabled at pin 1 of gate U2. If during this time the line current drops to zero as detected by resistor R21, resistor R22, and capacitor C12, pin 3 of gate U2 will go high and turn on the trip driver transistor Q6 to turn the display actuator into FAULT registration.
  • Diodes Dll, D12, and D13 will discharge all of the internal energy storage capacitor to prevent the circuit from reset and re-initiate the circuit into a predictable state. If the sensed current did not decay to zero • before the counter IC U3 times out, the SET/RESET Flip Flop is reset and the trip circuit returns to nominal state.
  • the voltage supply for the trip circuit includes diode D5, resistor R4, capacitor C4, and diode D7.
  • the reset time delay provided by U4 also serves as the inrush restraint timer.
  • the sensor output charges the reset energy storage capacitor capacitor C5.
  • transistor Q4 is turned ON by resistor R24 and capacitor C6 and enables the reset timer IC U4.
  • Another SET/RESET Flip FLop is SET by detecting the presence of line current and disables the adaptive trip circuit by turning transistor Q3 on and clamp the SET terminal of the trip Flip Flop low.
  • the timer IC U4 produces a high at pin 5 of U4 which cause the RESET Flip Flop to release transistor Q3 and enables the adaptive trip circuit.

Abstract

L'indicateur de défaut permet de détecter un courant passant dans un câble, effectue une remise à l'état initial en réponse à un courant minimum et arme un agencement de déconnexion en réponse à une augmentation de courant d'une valeur prédéterminée par rapport au temmps. Si le courant croissant ouvre également un disjoncteur dans un intervalle de temps prédéterminé et coupe le courant allant au câble, l'indicateur déconnecte. Si aucun courant nul ne se produit dans la période de temps, l'agencement de déconnexion est désarmé pour la montée de courant suivante.
PCT/US1990/004396 1989-08-07 1990-08-06 Indicateur de defaut adaptatif de courant WO1991002395A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US07/390,541 US5029039A (en) 1989-08-07 1989-08-07 Current adaptive fault indicator
US390,541 1989-08-07
US07/505,483 US5115031A (en) 1987-08-20 1990-04-06 Process for the manufacture of an impact resistant thermoplastic resin
US505,483 1990-04-06

Publications (1)

Publication Number Publication Date
WO1991002395A1 true WO1991002395A1 (fr) 1991-02-21

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PCT/US1990/004427 WO1991002396A1 (fr) 1989-08-07 1990-08-07 Indicateur adaptatif de defauts de courant

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PCT/US1990/004427 WO1991002396A1 (fr) 1989-08-07 1990-08-07 Indicateur adaptatif de defauts de courant

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AU (2) AU6294590A (fr)
CA (1) CA2064834A1 (fr)
WO (2) WO1991002395A1 (fr)

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GB2253956A (en) * 1991-03-19 1992-09-23 Meco Electronics Ltd A fast acting protection device for use with a power supply
WO1993012436A1 (fr) * 1991-12-09 1993-06-24 Campbell Houston Keenan Indicateur de panne pour lignes d'alimentation
EP0731543A2 (fr) * 1995-03-06 1996-09-11 Dipl.-Ing. H. Horstmann GmbH Indicateur de court-circuit
EP0856929A2 (fr) * 1997-01-30 1998-08-05 Dipl.-Ing. H. Horstmann GmbH Dispositif de location de faute dans un réseau de courant fort
EP2434512A1 (fr) * 2009-05-20 2012-03-28 Inael Electrical Systems, S.A. Procédé d'activation du compteur d'un sectionnaliseur
CN110850234A (zh) * 2019-11-21 2020-02-28 南京能云电力科技有限公司 一种故障指示器自动检测系统及检测方法

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US5159319A (en) * 1990-06-25 1992-10-27 Cooper Industries, Inc. Faulted circuit detector having an isolated indicator for an electrical transformer

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US3673455A (en) * 1970-11-18 1972-06-27 Gen Electric High speed sensor for initiating circuit breaker tripping
US3735248A (en) * 1970-03-31 1973-05-22 R Reese Apparatus having automatic re-set means for detecting a fault current
US4223365A (en) * 1979-03-29 1980-09-16 Mcgraw-Edison Company Auto resetting switchgear trip indicator circuits
EP0095590A1 (fr) * 1982-05-29 1983-12-07 Robert Bosch Gmbh Procédé pour surveiller une grandeur mesurée
EP0244284A1 (fr) * 1986-04-30 1987-11-04 Merlin Gerin Déclencheur statique instantané pour un disjoncteur limiteur

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Publication number Priority date Publication date Assignee Title
US3735248A (en) * 1970-03-31 1973-05-22 R Reese Apparatus having automatic re-set means for detecting a fault current
DE2048695A1 (de) * 1970-10-03 1972-04-06 Licentia Gmbh Mehrseitig gespeistes Hochspannungsnetz
US3673455A (en) * 1970-11-18 1972-06-27 Gen Electric High speed sensor for initiating circuit breaker tripping
US4223365A (en) * 1979-03-29 1980-09-16 Mcgraw-Edison Company Auto resetting switchgear trip indicator circuits
EP0095590A1 (fr) * 1982-05-29 1983-12-07 Robert Bosch Gmbh Procédé pour surveiller une grandeur mesurée
EP0244284A1 (fr) * 1986-04-30 1987-11-04 Merlin Gerin Déclencheur statique instantané pour un disjoncteur limiteur

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2253956A (en) * 1991-03-19 1992-09-23 Meco Electronics Ltd A fast acting protection device for use with a power supply
GB2253956B (en) * 1991-03-19 1994-09-14 Meco Electronics Ltd A fast acting protection device for use with a power supply
WO1993012436A1 (fr) * 1991-12-09 1993-06-24 Campbell Houston Keenan Indicateur de panne pour lignes d'alimentation
EP0731543A2 (fr) * 1995-03-06 1996-09-11 Dipl.-Ing. H. Horstmann GmbH Indicateur de court-circuit
EP0731543A3 (fr) * 1995-03-06 1998-01-14 Dipl.-Ing. H. Horstmann GmbH Indicateur de court-circuit
EP0856929A2 (fr) * 1997-01-30 1998-08-05 Dipl.-Ing. H. Horstmann GmbH Dispositif de location de faute dans un réseau de courant fort
EP0856929A3 (fr) * 1997-01-30 1999-10-06 Dipl.-Ing. H. Horstmann GmbH Dispositif de location de faute dans un réseau de courant fort
EP2434512A1 (fr) * 2009-05-20 2012-03-28 Inael Electrical Systems, S.A. Procédé d'activation du compteur d'un sectionnaliseur
CN110850234A (zh) * 2019-11-21 2020-02-28 南京能云电力科技有限公司 一种故障指示器自动检测系统及检测方法
CN110850234B (zh) * 2019-11-21 2021-12-17 南京能云电力科技有限公司 一种故障指示器自动检测系统及检测方法

Also Published As

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WO1991002396A1 (fr) 1991-02-21
AU6161890A (en) 1991-03-11
CA2064834A1 (fr) 1991-02-08
AU6294590A (en) 1991-03-11

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