WO1990006555A1 - Circuit integre auxiliaire de gestion de microprocesseur - Google Patents

Circuit integre auxiliaire de gestion de microprocesseur Download PDF

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Publication number
WO1990006555A1
WO1990006555A1 PCT/US1989/005456 US8905456W WO9006555A1 WO 1990006555 A1 WO1990006555 A1 WO 1990006555A1 US 8905456 W US8905456 W US 8905456W WO 9006555 A1 WO9006555 A1 WO 9006555A1
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WO
WIPO (PCT)
Prior art keywords
voltage
integrated circuit
power supply
circuit
external power
Prior art date
Application number
PCT/US1989/005456
Other languages
English (en)
Inventor
Don Folkes
Wendell L. Little
Original Assignee
Dallas Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/283,267 external-priority patent/US5754462A/en
Application filed by Dallas Semiconductor Corporation filed Critical Dallas Semiconductor Corporation
Publication of WO1990006555A1 publication Critical patent/WO1990006555A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3209—Monitoring remote activity, e.g. over telephone lines or network connections
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level

Definitions

  • the present invention relates to low-power systems and subsystems employing microprocessors, and to integrated circuit elements which help to manage the low-level operation of a microprocessor.
  • a separate line of technological progress is the increasing use of batteries, in integrated circuit packages or in very small modules, to provide nonvolatile data retention.
  • the driving concern is not the system power budget, but reliability and robustness.
  • the availability of battery backup can be used to ensure that power outages or power-line noise cannot cause loss of data (including configuration data).
  • modern semiconductor technology has provided solid-state memories with such low standby power requirements that a single coin sized battery can power the memory for ten years of lifetime or more. Such memories are already commercially available.
  • Low-power microcontrollers have also been commercially available in recent years.
  • An unusual example of such a microcontroller is the DS5000 Soft MicrocontrollerTM.
  • the DS5000 is a microcontroller which has a small battery packaged with it, to provide nonvolatility.
  • Microprocessors and microcontrollers of this kind are extremely useful, since the internal memory of the microprocessor is always preserved. Therefore, the microprocessor can be programmed to "learn" while in service, or to internally store a parameter set which is adjustable throughout the lifetime of the microprocessor.
  • such microprocessors are typically not the highest-performing microprocessors. Thus, a user who needs nonvolatility may need to make some difficult choices.
  • the present invention provides an auxiliary integrated circuit, which can interface with a microprocessor (or other complex random logic chip) in a way which improves the microprocessor's power management during power-up and power-down transitions.
  • this auxiliary chip provides all necessary functions for power supply monitoring, reset control, and memory back-up in microprocessor based systems.
  • a precise internal voltage reference and comparator circuit monitor power supply status. When an out-of-tolerance condition occurs, the microprocessor reset and power fail outputs are forced active, and static RAM control unconditionally write protects external memory.
  • the auxiliary chip also provides early warning detection by driving a non-maskable interrupt at a user defined voltage threshold.
  • External reset control is provided by a pushbutton reset input which is debounced and activates reset outputs. An internal timer also forces the reset outputs to the active state if the strobe input is not driven low prior to time out.
  • Reset control and wake- up/sleep control inputs also provide necessary signals for orderly shut down and start up in battery backup and battery operate applications.
  • the auxiliary chip provided by the present invention can be used with a very wide variety of different microcontrollers and microprocessors. Two significantly different types must be distinguished:
  • the microprocessor should not be reset when power is failing (because such a reset will wake up the microprocessor, and cause it to draw power).
  • CMOS microprocessors For NMOS microprocessors, and for CMOS microprocessors or microcontrollers which do not have access to a backup power supply, it is desirable to reset the processor as soon as possible when the power supply is failing, and keep it in reset until the power supply begins to recover. (Bringing the microprocessor under control early helps minimize power consumption, and helps to avoid random outputs from the microprocessor.)
  • a battery-backed microprocessor should preferably go into its "stop" mode when power goes down. However, the microprocessor alone does not normally know when it has been switched over to battery backup.
  • auxiliary chip which sends a reset command to an associated microprocessor at a certain voltage level, but only if the direction of voltage change indicates that the power supply is coming up, and not going down. This permits the microprocessor to be reset, and resume operation, as early as possible when power is restored, but prevents a nonvolatized microprocessor from being reset during its low- power state.
  • the microprocessor can access the auxiliary chip to ascertain the power history. That is, the microprocessor can direct an interrupt to the auxiliary chip, which will cause the auxiliary chip to respond with a signal which indicates to the microprocessor whether the power supply voltage is heading up or down.
  • the present invention permits the microprocessor to determine (by querying the auxiliary chip) whether the supply voltage is marginal, so that the microprocessor does not go into full operation until the supply voltage is high enough.
  • Another of the innovative teachings set forth in the present application is a control relationship which permits the auxiliary chip itself to be put to sleep by the microprocessor to minimize power consumption.
  • the sleep mode of the auxiliary chip saves power by shutting down many of the input-sensing circuits. (The sleep mode also gives users a way to turn off the watchdog functions of the auxiliary chip.)
  • the present invention imposes a timing relationship where the sleep command is not accepted unless it stands in the proper timing relationship to a signal on the strobe pin. This permits the power savings of the sleep mode to be realized, without any risk of the system being placed in the sleep mode due to an out-of-control system condition.
  • This auxiliary chip, and systems or subsystems which use this auxiliary chip provide at least the following advantages: Holds microprocessor in check during power transients; Halts and restarts an out-of-control microprocessor; Monitors pushbutton for external override; Warns microprocessor of an impending power failure; Converts CMOS SRAM into nonvolatile memory; Unconditionally write protects memory when power supply is out of tolerance; Consumes less than 100 nA of battery current; Can control an external power switch for high current applications; Provides orderly shutdown in nonvolatile microprocessor applications; Supplies necessary control for low power "stop mode' in battery operate hand held applications.
  • this auxiliary chip provides designers with a greatly increased range of options.
  • This auxiliary chip permits system designers to obtain many of the advantages of a specialized low- power microprocessor (such as the DS5000), while using a different microprocessor which has higher-speed, or more versatility, or compatibility with some existing software base, or special adaptation for some special purpose.
  • systems which include the combination of an auxiliary chip as described with a general-purpose microprocessor can have advantages including robustness in the face of power-supply crashes or glitches, and program resumption which appears (to the user) to be continuous with the program's operation at the moment when the machine was turned off (depending on how state-save operations are interwoven with software execution).
  • microprocessor architectures have reset lines running to every gate on the chip, so that a reset command will instantly reset every logical element to the known state.
  • some architectures do not. For example, in the Intel 8051 architecture, several cycles are necessary after the reset command, to clock all of the logical elements on the chip into the known state. (This architecture is used not only in Intel's 80C51 microprocessor, but also in any other microprocessor which is to be compatible with this widely-used architecture.)
  • a simple example of a logic block which would require multiple cycles to reset would be a shift register, with a reset only at the input of the shift register.
  • a "shadow” memory or register can be used to track the status of various on-chip registers, etc.
  • portions of on-chip memory can even be used as "shadow” scratch pad, to preserve some state information during such power-down operations.
  • Figure 1 shows a typical example of the power monitor, watchdog timer, and pushbutton reset
  • Figure 2 shows how the high impedance input at the IN pin allows for a user to define a sense point, using a simple resistor voltage divider network to interface with high voltage signals.
  • FIG. 3 shows a typical nonvolatile SRAM application.
  • Figure 4 depicts the three negative pulses on the IN pin which are used to invoke the freshness seal.
  • Figure 5 shows how the external supply voltage is switched by discrete transistors, controlled by power-fail signal PF and its complement PF*.
  • Figure 6 shows the power-down timing relations which result, in the presently preferred embodiment, when the reset control input (RC) has been tied to V CCO .
  • Figure 7 shows the power-down timing relations which result, in the presently preferred embodiment, when the reset control input (RC) has been tied to ground.
  • Figure 8 shows the power-up timing relations which result, in the presently preferred embodiment, when the reset control input (RC) has been tied to ground.
  • Figure 9 shows the power-up timing relations which result, in the presently preferred embodiment, when the reset control input (RC) has been tied to V CCO .
  • Figure 10 shows the signal timing relations which permit sleep mode to be entered
  • Figure 11 shows the signal timing relations which permit the chip to awaken from sleep mode.
  • Figure 12 shows the timing relation between the NMI* and ST* signals.
  • Figure 13 shows the overall organization of the auxiliary chip of the presently preferred embodiment.
  • Figure 14 shows the critical points on the curve of power supply voltage, when the power supply voltage is falling. DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • the auxiliary chip employs a bandgap voltage reference and a precision comparator to monitor the 5 volt supply (V CC ) in microprocessor based systems.
  • V CC 5 volt supply
  • the V CC trip point (V CCTP ) is set, for 10% operation, so that the RST and RST* outputs will become active as V CC falls below 4.5 volts (4.37 typical).
  • the V CCTP for the 5% operation option is set for 4.75 volts (4.62 typical).
  • the RST and RST* signals are excellent for microprocessor control, as processing is stopped at the last possible moment of within- tolerance V CC .
  • the RST and RST* signals are held active for a minimum of 40 ms (60 ms typical) after V CCTP is reached to allow the power supply and microprocessor to stabilize.
  • the mode of operation just described is achieved if the reset control pin (RC) is connected to GND.
  • the reset control pin RC is connected to GND.
  • V CCO voltage
  • a different mode of operation can be achieved. This different mode is shown in Figures 6 and 9, and is described below.
  • the auxiliary chip also provides a watchdog timer function by forcing the RST and RST* signals to the active state when the strobe input (ST*) is not stimulated for a predetermined time period. This time period is set for 220 ms typically with a maximum time- out of 300 ms.
  • the watchdog timer begins timing out from the set time period as soon as RST and RST* are inactive. If a high-to-low transition occurs at the ST* input prior to time-out, the watchdog timer is reset and begins to time out again.
  • the ST* input can be derived from microprocessor address, data, and/or control signals. Under normal operating conditions, these signals would routinely reset the watchdog timer prior to time out. If the watchdog timer is not required, it may be disabled by permanently grounding the IN input pin which also disables the NMI* output (described below). If the NMI* signal is required, the watchdog may also be disabled by leaving the ST* input open.
  • the watchdog timer is also disabled as soon as the IN input fells to V TP or, if IN is not used and grounded, as soon as V CC fells to V CCTP .
  • the watchdog will then become active as V CC rises above V CCTP and the IN pin rises above V TP .
  • PUSH-BUTTON RESET An input pin is provided on the auxiliary chip for direct connection to a push-button.
  • the push-button reset input requires an active low signal. Internally, this input is debounced and timed such that the RST and RST* outputs are driven to the active state for 40 ms maximum. This 40 ms delay begins as the push-button is released from low level.
  • NONMASKABLE INTERRUPT The auxiliary chip generates a non- maskable interrupt NMI* for early warning of power failure to a microprocessor.
  • a precision comparator 110 monitors the voltage level at the input pin IN relative to a reference generated by the internal bandgap.
  • the IN pin is a high impedance input allowing for a user defined sense point using a simple resistor voltage divider network ( Figure 3) to interface with high voltage signals. This sense point may be derived from the regulated 5 volt supply, or from a higher DC voltage level closer to the AC power input. Since the IN trip point V TP is 2.54 volts, the proper values for R 1 and R 2 can easily be determined. Proper operation of the auxiliary chip requires that the voltage at the IN pin be limited to 5 volts maximum. Therefore, the maximum allowable voltage at the supply being monitored (V MAX ) can also be derived as shown.
  • a simple approach to solving this equation is to select a value for R 2 of high enough impedance to keep power consumption low, and solve for R 1 .
  • the flexibility of the IN input pin allows for detection of power loss at the earliest point in a power supply system, maximizing the amount of time for microprocessor shut-down between NMI* and RST or RST*.
  • the auxiliary chip drives the NMI* output to the active state for a minimum of 200 microseconds, but does not hold it active. If the pin is connected to V CC , the NMI* output will pulse low as V CC decays to V CCTP if RC pin at ground (see reset control section).
  • the NMI* power fail detection circuitry also has built in time domain hysteresis. That is, the monitored supply is sampled periodically at a rate determined by an internal ring oscillator running at approximately 47 kHz (20 ms/cycle). Three consecutive samplings of out-of tolerance supply (below V SENSE ) must occur at the IN pin to active NMI. Therefore, the supply must be below the voltage sense point for approximately 60 ms or the comparator will reset.
  • the NMI* signal has been defined, in the presently preferred embodiment, as a pulse, rather than a level, because a constant output would keep some microprocessors from going into their lowest-power mode. Thus, the microprocessor cannot simply scan the NMI* signal to see where the power supply voltage level is.
  • the microprocessor can query the auxiliary chip to see where the power suppfy level is. Whenever the auxiliary chip receives a pulse from the microprocessor on the ST* line, it will return a pulse to the microprocessor on the NMI* line, but only if the system supply voltage is less than that required to trip the NMI* interrupt
  • FIG 14 is a simplified version of Figure 7, which shows this relationship more clearly.
  • V 1 refers to the voltage at which the auxiliary chip generates an interrupt (on line NMI*, in the presently preferred embodiment);
  • voltage V 2 is the voltage at which the auxiliary chip generates a reset (this is equal to voltage V CCTP , in the presently preferred embodiment);
  • voltage V 3 is the voltage at which comparator 130 connects the internal VCC to V BAT rather than to V CCI (which is the externally supplied power voltage, as opposed to the on- chip supply V CC ).
  • V CCI which is the externally supplied power voltage, as opposed to the on- chip supply V CC
  • the microprocessor can send a query to the auxiliary chip by pulsing the strobe pin ST*. When this occurs, the auxiliary chip will reply with a pulse on line NMI* if the supply level is then in zone 2, but not If the power supply level is in zone 1. Thus, the microprocessor can use this exchange to recognize whether it is in zone 2. This is important because the watchdog operation is turned off in zone 2, so that otherwise it might be possible for a stuck condition to occur.
  • MEMORY BACKUP The auxiliary chip provides all necessary functions required to battery back up a static RAM.
  • a switch is provided to direct power from the incoming 5 volt supply (V CC ) or from a battery (V BAT ) whichever is greater.
  • This switched supply (V CCO ) can also be used to battery back CMOS microprocessors.
  • the reset control and wake control sections provide further discussion regarding nonvolatile microprocessor applications.
  • the same power fail detection described in the power monitor section is used to inhibit the chip enable input (CEI*) and hold the chip enable ou ⁇ ut (CEO*) to within 0.3 volts of V CC or battery supply. This write protection mechanism occurs as V CC falls below V CCTP as specified previously.
  • CEO* is held in its present state until CEI* is returned high, or if CEI* is held low, CEO* is held active for t CE maximum. This delay of write protection until the current memory cycle is completed prevents the corruption of data. If CEO* is in an inactive state at the time of V CC fail detection, CEO* will be unconditionally disabled within t CF . During nominal supply conditions CEO* will follow CEI* with a maximum propagation delay of 20 ns.
  • FIG. 4 shows a typical nonvolatile SRAM application. If nonvolatile operation is not required, the battery input pin V BAT must be grounded. In order to conserve battery capacity during storage and/or shipment of a system, the auxiliary chip provides a freshness seal to electronically disconnect the battery.
  • Figure 5 depicts the three pulses below ground on the IN pin required to invoke the freshness seal. The freshness seal will be disconnected and normal operation will begin when V CC is next applied to a level above
  • the 5 volt supply and battery supply switches internal to the auxiliary chip may not be large enough to support the given load within significant voltage drop.
  • the PF and PF* outputs are provided to gate external switching devices to switch supply from V CC to battery on power down and from battery to V CC on power up.
  • the transition threshold for PF and PF* is set to the external battery voltage V BAT (see Figure 6).
  • the load applied to the PF pin from the external switch will be supplied by the battery. Therefore, this load should be taken into consideration when sizing the battery.
  • RESET CONTROL Two modes of operation on power down and power up are available, depending upon the level of the reset control
  • RC RC input pin.
  • the level of this pin distinguishes timing and level control on RST, RST*, and NMI* outputs for volatile processor operation versus non-volatile battery backed (or battery operated) processor applications.
  • V CC collapses to V CCTP , and RST* is held at a high level by the battery as V CC falls below battery potential.
  • the NMI* output pin will pulse low for t N MI following a low voltage detect at the pin of V TP .
  • NMI* will also be held at a high level following t NMI by the battery as V CC decays below V BAT .
  • RST and RST* are held inactive until V CC reaches power valid V CCTP , then RST and RST* are driven active for t RST .
  • NMI* will pulse low for 500 microseconds maximum then will follow V CC during the power up sequence.
  • the processor may power down into a "stop" mode and subsequently be restarted by any of several different signals. If V CC does not fall below V CCTP , the processor will be restarted by the reset derived from the watchdog timer as the IN input rises above V tp . If V CC falls below V CCTP but not below V BAT , the processor will be restarted as V CC rises above V CCTP . If V CC fells below V BAT , the reset outputs will be forced active the next time V CC rises above V CCTP as shown in the power up timing diagram.
  • the pushbutton input PBRST* may be used, whenever V CC is above V BAT , to drive the reset outputs and thus restart the processor.
  • the Wake/Sleep Control input WK/SC* allows the processor to disable all comparators on the auxiliary chip, processor, and nonvolatile static RAM to maintain nonvolatility in the lowest power mode possible.
  • the processor may invoke the sleep mode in battery operate applications to conserve capacity when an absence of activity is detected.
  • the auxiliary chip may subsequently be restarted by a high to low transition on the PBRST* input via human interface by a keyboard, touch pad, etc. The processor will then be restarted as the watchdog timer times out and drives RST and RST* active.
  • the auxiliary chip can also be woken up by forcing the WK/SC* pin high from an external source.
  • the auxiliary chip will wake up the next time V CC rises above V CCTP . That is, the auxiliary chip leaves the sleep mode as the power is falling below V BAT .
  • the processor invokes the sleep mode during normal power valid operation, all operation on the auxiliary chip is disabled, thus leaving the NMI*, RST and RST* outputs disabled as well as the ST* and IN inputs.
  • the PBRST* input will also become inactive when the main battery supply falls below the IN input at V TP or the backup 3 volt supply at V BAT .
  • Figure 13 shows the overall electrical organization of the auxiliary chip of the presently preferred embodiment.
  • a first comparator 110 compares the input voltage at the IN pin with the reference voltage provided by bandgap voltage reference generator 200. The output of this comparator is connected through rime delay stage 112 to one-shot 114. Thus one- shot 114 will provide a pulse on the NMI* output pin when comparator 110 sees that the voltage at pin IN has fallen below limits. (As noted, a resistive divider network would commonly be used to scale the supply voltage appropriately for this comparison.)
  • a second comparator 120 compares a fraction of the supply voltage input V CCI (scaled by resistors 121) with the reference voltage provided by bandgap voltage reference generator 200.
  • the output of this comparator 120 is connected, through time delay stage 122 and OR gate
  • comparator 120 is also connected (through the time delay block 122) to control a chip-enable-control gate 139, so that incoming chip-enable signals CEI* will n ot be passed through to signal CEO* when V CCI has fallen below V CCTP .
  • a third comparator 130 compares the external VCC supply voltage input (V CCI ) against the battery voltage V BAT , and switches large transistors 132, 134, and 136 (via NAND gate 135) appropriately, to connect the external power supply output VCCO and the internal power supply lines VCC to V BAT if V CCI falls significantly below V BAT .
  • the NAND gate 135 also receives an input from freshness seal logic 131, so that, if the input from freshness seal logic 131 is low, transistor 136 will never turn on. In this case, if the external power supply V CCI fails, comparator 130 will drive its output PF positive, turning off transistors 132 and 134, and pin V CCO will be floated. This avoids any loss of battery lifetime due to drain from external devices.
  • the freshness seal logic 131 decodes signals received on the SLP* pin, as described above, to enter or leave the freshness-seal mode.
  • the output of the bandgap voltage reference 200 is also used by a current source (not separately shown), which provides a temperature- independent current to the ring oscillator.
  • This current source also provides a temperature-independent current to the voltage reference 200.
  • the voltage reference 200 uses this current to define charging relationships, and also makes use of the output of the ring-oscillator (to chipper-stabilize the comparators).
  • the ring oscillator 310 provides a constant-frequency output to watchdog timer 300.
  • the watchdog timer 300 provides timing and alarm functions, such as those performed by commercially available part DS1286.
  • the watchdog timer will provide an input to OR gate 410, to generate a reset, if it counts down through its time-out limit without having received a pulse on pin ST*.
  • the sleep-control logic 500 receives inputs from the SLP* pin and also from the ST* pin.
  • the outputs of this logic can disable not only watchdog timer 300, but also are connected to disable bandgap voltage reference 200, oscillator 310, and comparators 110 and 120.
  • Comparator 130 is not disabled, but is switched into a low-power mode. In comparator 130's low-power mode, its bias current is reduced, so that it can still detect when V CCI falls below V BAT , it reacts more slowly.
  • the third input to the OR gate 410 is from the pushbutton input PBRST*, which is cleaned up by debounce logic 420.
  • the reset control logic 400 can be conditionally commanded to initiate a reset by any of the three inputs just described. However, the reset control logic 400 also receives external control input RC, and also is connected to see the outputs of comparators 110 and 120, to implement the logical relations described above.
  • I CCO1 is the maximum average load which the DS1236 can supply at V CC - 3V through the V CCO pin during normal 5 volt operation.
  • 4I CCO2 is the maximum average load which the DS1236 can supply through the V CCO pin during data retention battery supply operation.
  • V CCO is approximately V BAT -0.5V at 1 ⁇ A load.
  • 9 t REC is the minimum time required before memory access to allow for deactivation of RST and RST*.
  • the microprocessor's programming can use the power- down warning interrupt to trigger a state-save operation.
  • the disclosed auxiliary chip can be used with a wide variety of microprocessors, microcontrollers, or microcomputers, including ones which do and ones which do not have their own battery back-up supplies; 8-bit, 16-bit, 32-bit, or other architectures; general- purpose processors, DSPs (digital signal processors), or ASICs (application-specific integrated circuits); numeric or symbolic processors; and others.
  • a wide range of system contexts are enabled by the disclosed inventions, including (for example) portable computers, device controllers, desk-top computers, sub-processors which perform management functions in minicomputer, mainframe, or even supercomputer systems.

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
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Abstract

Système comprenant un microprocesseur (ou microcontrôleur) ainsi qu'une puce auxiliaire contrôlant la tension d'alimentation du système, exécutant des fonctions associées pour le microprocesseur, et assurant une fonction de surveillance. Le microprocesseur peut mettre ladit puce auxiliaire en veilleuse afin de réduire au minimum la consommation. Ledit microprocesseur peut envoyer à ladite puce auxiliaire un signal d'interruption, laquelle répond par un signal indiquant au microprocesseur si la tension d'alimentation monte ou baisse. Dans un mode, ladite puce auxiliaire envoie un signal d'interruption au microprocesseur lorsque l'alimentation tombe à un premier niveau, et rerègle également le microprocesseur lorsque la tension d'alimentation atteint un second niveau prédéterminé lors de la montée (c'est-à-dire lorsque l'alimentation est rétablie). Dans un second mode sélectionnable, la puce auxiliaire rerègle le processeur lorsque l'alimentation chute.
PCT/US1989/005456 1988-12-09 1989-11-30 Circuit integre auxiliaire de gestion de microprocesseur WO1990006555A1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US28279388A 1988-12-09 1988-12-09
US28326888A 1988-12-09 1988-12-09
US282,793 1988-12-09
US283,267 1988-12-09
US07/283,267 US5754462A (en) 1988-12-09 1988-12-09 Microprocessor auxiliary with ability to be queried re power history
US283,268 1988-12-09

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WO1990006555A1 true WO1990006555A1 (fr) 1990-06-14

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PCT/US1989/005544 WO1990006552A1 (fr) 1988-12-09 1989-11-30 Mise en circuit a effleurement declenchee par batterie
PCT/US1989/005456 WO1990006555A1 (fr) 1988-12-09 1989-11-30 Circuit integre auxiliaire de gestion de microprocesseur

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EP0496536A2 (fr) * 1991-01-25 1992-07-29 International Business Machines Corporation Système de gestion d'alimentation pour ordinateur à piles
EP0504007A2 (fr) * 1991-03-08 1992-09-16 Fujitsu Limited Unité alimentée par batterie
EP0563924A1 (fr) * 1992-04-01 1993-10-06 Nec Corporation Dispositif de contrôle d'une unité centrale (CPU) lors d'une baisse instantanée de la tension
EP0602264A1 (fr) * 1992-12-15 1994-06-22 Siemens Aktiengesellschaft Procédé et dispositif pour surveiller l'opération d'un circuit numérique
US6252823B1 (en) 1994-12-16 2001-06-26 Vu-Data Limited Recorder device, reading device and regulating device
DE102016107801B3 (de) 2016-04-27 2017-03-30 Zippy Technology Corp. Verfahren zum Vermeiden eines zu häufigen Neubootens einer Stromversorgungs-Vorrichtung

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JP3684590B2 (ja) * 1994-04-25 2005-08-17 カシオ計算機株式会社 リセット制御装置及びリセット制御方法
DE69609530T2 (de) * 1995-12-29 2001-03-29 Advanced Micro Devices Inc Rücksetzschaltung für eine batterie-getriebene integrierte schaltung und verfahren zum rücksetzen dieser integrierten schaltung
US5790873A (en) * 1996-07-23 1998-08-04 Standard Microsystems Corporation Method and apparatus for power supply switching with logic integrity protection
AUPQ088699A0 (en) * 1999-06-10 1999-07-01 Tentas Telehealth Pty Ltd Power saving leads status monitoring
US7589568B2 (en) * 2007-05-04 2009-09-15 Microchip Technology Incorporated Variable power and response time brown-out-reset circuit
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EP0496536A2 (fr) * 1991-01-25 1992-07-29 International Business Machines Corporation Système de gestion d'alimentation pour ordinateur à piles
EP0496536A3 (en) * 1991-01-25 1993-02-24 International Business Machines Corporation Battery operated computer power management system
EP0504007A2 (fr) * 1991-03-08 1992-09-16 Fujitsu Limited Unité alimentée par batterie
EP0504007A3 (fr) * 1991-03-08 1994-02-23 Fujitsu Ltd
EP0563924A1 (fr) * 1992-04-01 1993-10-06 Nec Corporation Dispositif de contrôle d'une unité centrale (CPU) lors d'une baisse instantanée de la tension
US5400341A (en) * 1992-04-01 1995-03-21 Nec Corporation Control device for controlling a central processing unit on instantaneous voltage drop
AU664734B2 (en) * 1992-04-01 1995-11-30 Nec Corporation Control device for controlling a central processing unit on instantaneous voltage drop
EP0602264A1 (fr) * 1992-12-15 1994-06-22 Siemens Aktiengesellschaft Procédé et dispositif pour surveiller l'opération d'un circuit numérique
US6252823B1 (en) 1994-12-16 2001-06-26 Vu-Data Limited Recorder device, reading device and regulating device
DE102016107801B3 (de) 2016-04-27 2017-03-30 Zippy Technology Corp. Verfahren zum Vermeiden eines zu häufigen Neubootens einer Stromversorgungs-Vorrichtung

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