WO1990001826A1

WO1990001826A1 - Pwm inverter control method and circuit

Info

Publication number: WO1990001826A1
Application number: PCT/US1989/003164
Authority: WO
Inventors: Sampat S. Shekhawat; John Dhyanchand
Original assignee: Sundstrand Corporation
Priority date: 1988-08-08
Filing date: 1989-07-21
Publication date: 1990-02-22
Also published as: IL91092A0

Abstract

Prior types of neutral point clamped PWM inverters pulses in a PWM waveform having reference points which are evenly spaced. Such a control technique, however, accomplishes a significant reduction in output harmonics only for relatively low inverter output magnitudes. In order to overcome this problem, a control for a PWM inverter defines a series of reference points (alpha) spaced in time in accordance with an inverse trigonometric function of the number of pulses (9) to be produced in a portion (180°) of the inverter output wherein each reference point is associated with a pulse to be produced in the PWM waveform and determines rising (R1, R2...) and falling (F1, F2...) edges of each pulse of the AC output relative to the reference point associated with such pulse in dependence upon an output parameter of the inverter. Switch control signals are developed for each switch from the defined rising and falling edges. The control of the present invention accomplishes a significant reduction in the harmonics produced by the inverter at higher inverter output magnitudes.

Description

PWM INVERTER CONTROL METHOD AND CIRCUIT

Technical Field

The present invention relates generally to inverter controls, and more particularly to a control circuit for operating switches in a pulse width modulated (PWM) inverter to minimize harmonics in the output thereof.

Background Art

Prior conventional inverters typically include one or more legs, each of which includes a pair of switches connected in series across a DC power source providing voltages of opposite polarity on first and second rails, respectively. The switches are alternately operated so that a phase output is developed at a junction between the switches which alternately assumes the first and second voltages developed by the DC power source. This wide swing in output voltage results in an undesirably high harmonic content in the output. This results in the need for an output filter coupled to the inverter output which must be undesirably large and heavy.

In an attempt to reduce this harmonic content, neutral point clamped inverters have been developed which limit the output voltage swing. Such inverters include a pair of clamping switches coupled between each phase output and a neutral voltage whereby the clamping switches are operated by logic in interlocking fashion with the main phase switches in the inverter leg so that the output voltage swing is limited to half the voltage produced by the DC power source.

A prior control for a neutral point clamped PWM inverter is disclosed in Shekhawat et al. U.S. Patent No. 4,635,177, assigned to the assignee of the instant application and the disclosure which is hereby incorporated by reference. This patent discloses a control which develops a PWM control signal by defining the rising and falling edges of each of a series of PWM pulses relative to each of an associated series of equally spaced reference points in dependence upon the displacement of the pulse reference point from a zero crossing point of a sine wave. More particularly, a series of integral equations defining the rising and falling edges of the pulses relative to the pulse reference points are solved by a processor while the inverter is operating based upon the required "depth of modulation", wherein this parameter is proportional to the deviation of the voltage at a point of regulation from a desired voltage. The PWM control signal is in turn used to derive switch control signals for switches in the inverter. This control is capable of on-line regulation of the output of the inverter and can thus accomplish continuous regulation over the inverter output.

Other patents disclosing methods and apparatus for controlling PWM inverters include Geppert et al. U.S. Patent No. 4,458,194, Muto et al. U.S. Patent No. 4,562,524 and Sato U.S. Patent No. 4,729,082.

Disclosure of the Invention

In accordance with the present invention, a control for a neutral point clamped PWM inverter comprises an improvement over the control disclosed in the Shekhawat '177 patent described above whereby higher harmonics are reduced or eliminated for higher values of depth of modulation, thereby minimizing output filter size and weight.

The control implements a method including the steps of generating a magnitude signal representing a desired magnitude of a parameter of the AC output waveform to be produced by the inverter, defining a series of reference points spaced in time in accordance with an inverse trigonometric function of the number of pulses to be produced in a portion of the AC output wherein each reference point is associated with a PWM pulse to be produced and determining rising and falling edges of each pulse of the AC output of the inverter relative to the reference point associated with such pulse in dependence upon the magnitude signal. Switch control signals for each switch are developed from the defined rising and falling edges.

Preferably, the reference points are spaced according to an inverse sine function. The positions of the rising and falling edges relative to each reference point are dependent upon the solution of integral equations having trigonometric limits and are further dependent upon the magnitude signal, which is preferably the depth of modulation required to cause the inverter output voltage to be equal to a desired level.

The leading and falling edges of each pulse may be spaced from the associated reference point by amounts which are equal or unequal, as desired. In the former case, the control operates on a symmetric basis whereas in the latter case the control operates on a symmetric basis.

The control and method of the present invention results in the elimination of up to the seventeenth harmonic and results in a significant reduction in the nineteenth harmonic in the inverter output as compared with the system disclosed and claimed in the '177 patent when the control is used in a four-wire, three-phase system at higher values of depth of modulation. Brief Description of the Drawings

Fig. 1 is a combined simplified schematic and block diagram of a neutral point clamped inverter in conjunction with the control of the present invention;

Fig. 2 is a simplified schematic diagram of a different type of neutral point clamped inverter with which the control of the present invention may be used;

Fig. 3 is a series of waveform diagrams illustrating the operation of the control shown in Fig. 1;

Fig. 4 is a block diagram of the control shown in Fig. 1;

Fig. 5 is a block diagram of one of the programmable timer modules (PTM) shown in Fig. 4;

Fig. 6 is a flow chart illustrating the operation of the control shown in Fig. 1; and

Fig. 7 is a schematic diagram of a circuit for developing a switch control signal for the switch Q13 shown in Fig. 2.

Best Mode for Carrying Out the Invention

Referring now to Fig. 1, there is illustrated one type of neutral point clamped inverter 10 in conjunction with a PWM inverter switch control 12 according to the present invention. The inverter 10 includes first and second rails 14, 16 which receive DC voltages V _DC+ and V_DC- developed by one or a pair of DC voltage sources E₁ and E₂. Coupled across the rails 14, 16 are three inverter legs 20, 22, and 24, each including a pair of series connected phase output switches Q1, Q2 and Q3, Q4 and Q5, Q6, respectively. Connected across the collector and emitter electrodes of each of the switches Q1-Q6 is a flyback diode D1-D6, respectively. These diodes prevent reverse breakdown of the switches Q1-Q6 and permit regenerative currents to flow. Also coupled across the rails 14, 16 is a pair of capacitors C1 and C2 which minimize disturbances caused by regenerative currents.

The switches Q1-Q6 are operated so that phase outputs V_A, V_B, V_C are developed at junctions 30, 32, 34 between switches of each leg 20, 22, 24, respectively.

Each of the junctions 30, 32 and 34 is coupled by a pair of clamping switches to a neutral line N connected to the junction between the voltage sources E₁ and E₂. For example, referring specifically to the inverter leg 20, the junction 30 is coupled by means of diodes D7 and D8 and switches Q7 and Q8 to the neutral line N. Similarly, the junction 32 is connected to the neutral line N by means of diodes D9 and D10 and switches Q9 and Q10 as is the junction 34 by diodes D11 and D12 and switches Q11 and Q12.

While the switches Q1-Q12 are illustrated as bipolar transistors, it should be understood that these switches may be other types of devices, if desired.

As noted more specifically below, the phase output switches Q1-Q6 of each leg are operated in interlocking fashion with the clamping switches Q7-Q12 associated with that leg to limit the voltage swing at the respective phase output to one-half the voltage difference between the rails 14, 16.

Each of the phase outputs V_A, V_B, and V_C is coupled through an output filter 36, 38, 40, respectively, to individual phases of a load 41 represented by phase impedances Z_L. While each output filter is represented in Fig. 1 by lumped impedances, such as L_A and C_A in filter 36, it should be understood that these lumped impedances may represent the combined effect of several inductors and capacitors. Also, the phase impedances of the load 41 may be unequal, causing an unbalanced load condition. Each of the phases of the load 41 is connected to the neutral line by a conductor 42. This type of inverter, therefore, comprises a three phase, four wire system.

The switches Q1-Q12 in the inverter 10 are operated by the switch control 12 which senses the voltage at a point of regulation, or POR, near the load. The switch control 12 also receives a signal representing the current in one of the rails 14, 16 from a current transformer CT. This signal is utilized to limit the destructive effects of shoot-through or cross conduction of transistors in the inverter legs.

The neutral point clamped topology shown in Fig. 1 can alternatively be replaced by that shown in Fig. 2, in which like reference numbers or letters designate elements in common with Fig. 1. Several of the elements which would normally be present in Fig. 2, such as the flyback diodes and load and associated circuits are not shown for purposes of clarity.

Each of the junctions 30, 32, 34 is coupled by means of a bilateral switch 50, 52, 54, respectively, to the neutral line N. Each bilateral switch, such as the switch 50, includes four diodes D13-D16 which are connected in a bridge configuration. One pair of diagonally opposite vertices of the bridge is connected between the phase output and the neutral line N while the collector and emitter electrodes of a switch Q13 are connected across the other pair of vertices.

The operation of the inverter of Fig. 2 differs from that shown in Fig. 1 in that each switch Q13-Q15 is operated when both of the transistors of the associated inverter leg are in an off state. This function is described with more particularity below. A more specific description of the bilateral switch is contained in Glennon, U.S. Patent No. 4,564,895, entitled, "Improved Waveform Inverter", and assigned to the assignee of the instant application, the disclosure of which is hereby incorporated by reference.

Referring again to Fig. 1, the control of the present invention is a microprocessor-based system which develops PWM waveform patterns on-line, i.e. the PWM patterns are generated as the inverter is operating based upon one or more operating parameters of the inverter, such as the output voltage at a point of regulation (POR) and/or the DC link current in the rails 14, 16. The microprocessor in the switch control 12 utilizes a pair of equations to calculate a series of switching points for the PWM patterns as follows:

( 1 ) α_RN = α_REFN - β _1N

( 2 ) α_FN = α_REFN + β _2N

The above terms α _RN and α_FN represent the rising and falling edges, respectively, of pulses in a pulse width modulation pattern. Fig. 3 illustrates the case where the number of pulses P to be produced per half cycle is equal to nine. The switching points for each pulse in the PWM pattern are determined by finding a reference point for the pulse represented by the term α_REFN, and subtracting from this term the value β _1N to derive αRN and adding to this term the value β_2N to derive α _FN. For example, as seen in the waveform of Fig. 3 representing the base drive for the switch Q1, the fourth pulse (i.e. N = 4) in the inverter output for phase A is defined by switching points found by subtracting a value 8 from the term αREF4 and adding a value β24 to the term αREF4.

In first and second embodiments described hereinafter, the reference points are defined according to the following function:

(3) α_REFN = arcsin(2N-1)/P where P is predetermined and is the number of pulses developed at each phase output during a half-cycle and N is the number of a pulse in a quarter-cycle, where N assumes integer values between 1 and (P+1)/2.

In a first embodiment of the invention, the terms β_1N and β_2N are equal in magnitude, and hence the rising and falling edges of each pulse are spaced equally in time from the reference point of such pulse. In this embodiment, the control operates on a "symmetric" basis and the values β_1N and β₂N ^are defined as follows:

(4)

where :

(5) k₁ = 180(DM)/πF

The term DM is a magnitude signal representing the desired magnitude of a parameter of the inverter

SUBSTITUTE SHEET output. More particularly, DM represents the required depth of modulation and is proportional to the deviation of a POR phase voltage from a desired level. The term DM may instead represent the deviation of any other output parameter from a desired magnitude, if desired.

In further embodiments of the invention, the rising and falling edges of each pulse may be spaced unequally from the pulse reference point. In these embodiments, the terms β_1N and β_2N are unequal and the control is said to operate on an "asymmetric" basis. In a first of the asymmetric embodiments, the values β_1N and β_2N are defined as follows:

(6)

(7)

where k₁ is defined as noted above. The values β_1N and β_2N are subtracted from and added to the reference points, respectively, as defined above.

In a second of the asymmetric embodiments, the reference points are defined differently than the symmetric embodiment and the first of the asymmetric embodiments. In this case, the reference points and the values β_1N and β_2N are defined as follows: (8)

(9)

(10)

where k₁, α_RN and α_FN are defined as before.

In yet another asymmetric embodiment, the terms α_REFN, β_1N and β_2N are defined as follows:

(11) α_REFN = arcsin R_N

where: R_N = 2N/P when 2N/P < 1; or

R_N = 1 when 2N/P > 1

(12) β_1N = k₁[cos (arcsin A_N) - cos(arcsin R_N)]

(13) β_2N = k₁[cos] (arcsin R_N) - cos(arcsin B_N)]

where: A_N = 0 when N=1

A_N = (2N-1)/P when (2N-1)/P < 1

A_N = ((2N-1)/P+1)/2 when (2N-1)/P = 1

B_N = (2N+1)/P when (2N+1)/P < 1

B_N = ((2N/P)+1)/2 when (2N+1)/P = 1

The only variables in the above equations (4)-(13) are the terms F, i.e. the desired output frequency, and DM which is a function of the output voltage of the inverter. Of course, when the inverter is to be operated as a constant frequency power supply, F is a known quantity and hence the only variable is DM. Hence, the equations (1) and (2) defining the rising and falling edges of the pulses in the PWM pattern can be solved by simply inserting the current value of the variable DM in the equations along with the constant or predetermined values and solving the equations (1) and (2) for each value of N.

The integrals of equations (4), (6), (7), (9) and (10) define the area under a portion of an imaginary sine curve at a frequency and amplitude equal to the frequency and amplitude of the desired inverter output fundamental. Thus, the rising and falling edges of each PWM pulse, and hence the width of each pulse, is dependent not only upon the parameter DM, but also the area under one (if symmetric) or two (if asymmetric) portions of the imaginary sine wave.

Referring now to Fig. 4, there is illustrated in greater detail the switch control 12 shown in Fig. 1. The switch control 12 includes means for generating the magnitude signal DM including a full-wave rectifier 60 which receives a POR voltage, such as V_PORA, and a summer 62 which subtracts a signal V_REF representing the desired output voltage from the output of the rectifier 60 to develop an error signal V_e which is proportional to the variable DM.

While not illustrated in Fig. 4, each of the POR voltages V_PORB and V_PORC may be rectified and compared to reference signals by circuits similar to circuits 60, 62 to develop additional error signals which are proportional to the variable DM for each of these phases. These signals may be used to calculate switching points for the switches of these phases so that individual phase regulation can be accomplished, if desired.

The error signal V_e is coupled to an interface unit 64 which converts the signal into data signals which are then coupled to a microprocessor 66.

The interface unit 64 also receives a current error signal I_e which is developed by coupling a signal I_DC representing the current in one of the rails 14, 16 to a summer 67 which subtracts from this signal a reference I_Ref. A frequency command signal may also be coupled to the interface unit 64 in the event that the inverter is to be used as a variable frequency power supply.

The interface unit 64 is coupled to a CPU 68 within the microprocessor 66 over a data bus 70. The CPU is in turn coupled to a pair of memory units consisting of a random access memory, (RAM) 70 and a programmable read only memory (PROM) 72. These memory units may be a part of the microprocessor 66 or may be external units, as desired.

The microprocessor data bus 70 is also coupled to a pair of programmable timer modules 76, 78 each of which in turn develops signals for controlling the conduction of one-half of the switches Q1-Q12 through base drive circuits 80, 82, respectively. Each of the programmable timer modules 76, 78 receives clock signals from a clock 84. As seen in Fig. 5, and with reference to the PTM 76 specifically, the clock signal developed by the clock 84 is coupled to each of three counters 90, 92 and 94 which receive data signals on the bus 70 through latch circuits 96, 98 and 100, respectively. The outputs of the counters 90, 94 are coupled to the base drive circuit 80 and to an interrupt generator 102, which is in turn coupled to the CPU 68.

Referring also to Fig. 6, the control 12 according to the present invention is prepared for use by first determining the number of pulses P to be produced during each half cycle of the inverter output. While the example shown in Fig. 3 is for the case P = 9 a lesser or greater number of pulses may alternatively be produced, as desired. In general, considerations of harmonic content in the output dictate that the number of pulses P to be produced during each half cycle be an odd multiple of three, i.e. 3, 9, 15, etc.

As previously mentioned, once P has been determined, the only variables remaining in equations (4)-(1() are the desired output frequency F and the variable DM. It should be noted that the integral terms of equations (4), (6), (7), (9) and (10) are not solved directly, instead, the corresponding trigonometric equations are reduced to a constant times DM (and F, if variable) for each value of N once P is determined and these resulting values, as well as the remaining constants, are stored in memory locations in the PROM 72.

Referring now to Fig. 6, once the PROM 72 has been loaded with the control program for the microprocessor 66 and the terms and constants described above, and following start up of the inverter, a block 110 senses the frequency command and the signal V_e representing the variable DM coupled to the bus 70 via the interface 64. A pair of blocks 112 and 114, to be described in greater detail below, then calculate the switching points for the required PWM pattern and operate the switches to generate the pattern.

Following the block 114, a block 116 again senses the frequency command and a block 118 then determines whether the frequency command has changed from the previous value. If this is not the case, control passes to a block 119 which senses the variable DM. If this variable has not changed since it was last sensed, control returns to the block 116, since the inverter output voltage is such that corrective action need not be taken.

Control remains in the loop consisting of the blocks 116-120 until a change in frequency command or a change in the variable DM occurs.

If either of the blocks 118 or 120 determines that there is a change in the frequency command or in the variable DM, control returns to the block 112 which calculates the switching points for the PWM pattern required to maintain the inverter output at the desired voltage and/or frequency. This is accomplished by solving the equations (1) and (2) described above for each value of N using the present values of the variables F and DM and the resulting values stand in the PROM 72. The CPU 68 calculates the switching points for the PWM pattern for one quadrant of the desired output and stores values in the RAM 70 representing the duration between the switching points for the PWM pattern for one quadrant of the desired output. For example, with particular reference to Fig. 3, the CPU 68 stores values in the RAM 70 representing the duration between 0° and α_R1, the duration between the switching points α_R1 and α_F1, the duration between the switching points α_F1 and α_R2, etc...

The CPU 68 also stores a value in the RAM 70 representing the duration between the switching point α_R5 and the 90º point multiplied by two. This value is used to determine the falling edge α_F5 of the center pulse in each half-cycle.

Once these values have been stored in the RAM 70, the block 114, Fig. 6, loads the PTM's with the information representing the PWM pattern. This is accomplished by loading each of the latches in the" PTM's with the required values, and enabling the counters by coupling an enable signal to an enable input E at appropriate times so that the proper phase sequence is produced. Taking the waveform of Fig. 3 as an example, the value representing the duration between the 0º point of the output waveform and the switching point α_R1 is loaded into the latch 96 at a point prior to time to. At time to the counter 90 is enabled by a signal from the CPU 68 to begin decrementing the value stored in the latch 96 as pulses are received from the clock 84. Also at this time, the latch input receives a next value representing the duration between the switching points α_R1 and α_F1.

At time t₁ the counter 90 has decremented the present value representing the duration between the 0º point and the switching point α_R1 to zero. The output of the counter 90 then switches to a high state. This high state signal is coupled through the base drive circuit 80 to the control input of the switch Q₁ so that this switch is closed. The high state signal from the counter 90 is also coupled to the interrupt circuit 102 which in turn causes the CPU to load the next value representing the duration between switching points α_F1 and α_R2 into the latch 96. Also at time t₁, the counter 90 is enabled to decrement the value representing the duration between the switching points α_R1 and α_F1.

Once the counter 90 has decremented this value to zero at time t₂, the counter output switches to a low state, in turn opening the switch Q₁. An interrupt is again generated to cause loading of a new value into the latch 96 and decrementing of the value representing the next duration by the counter 90.

The above process continues until the rising edge of the (P + 1)/2th (or half-cycle) pulse is generated, following which the data stored in the memory representing the duration between the rising edge α _R5 and the falling edge α_F5 is decremented by the counter 90 so that the center pulse is developed. Thereafter, the data representing the first quadrant of the PWM output (except the data relative to the (P + 1)/2th pulse) is loaded in reverse sequence in the PTM 76. The counter and latches are operated as noted before to produce the proper pulse widths.

Of course, values representing the durations between switching points for an entire half-cycle can be stored in the RAM 70, if desired, in which case the values would be loaded into the latches in proper sequence to produce the required pattern.

As seen in Fig. 4, the switch control signal for the switch Q₁ is inverted by an inverter 130 in a switch control circuit 131A and the resulting signal is coupled to one input of an AND gate 132. A second input of the AND gate 132 receives a signal from a half-wave rectifier 134 coupled to V_PORA and a pulse shaper 135. The circuits 134, 135 together generate a signal which is in a high state for the first half-cycle of the voltage V_PORA and in a low state for the balance of the cycle. The AND gate 132 combines the signals at the first and second inputs to generate a switch control signal for the switch Q7, Fig. 3, so that the phase output V_A is clamped by Q7 to the neutral voltage during off periods of the switch Q1 in the first half-cycle of the phase output. This operation limits the swing in output voltage, as previously mentioned.

During the first 180º of the output waveform, the switches Q2 and Q8 are maintained in an off state. At some point prior to the 180º point, the appropriate latch in the PTM 78 is loaded with the information representing the duration between the 180º point and the first switching point of the PWM waveform for this half cycle. The operation of the latch and counter in the PTM 78 to control the switch Q2 is identical to that described with reference to the PTM 76 and the switch Q1, the only difference being the timing of enable signals for the counters in the PTM 78.

The switch Q8 is controlled by signals which are generated by a switch control circuit 136A comprising inverters 137, 138 which receive the output of the pulse shaper 135 and the switch control signals for the switch Q2, respectively, and an AND gate 140 which combines the inverter outputs to produce the control signal shown in Fig. 3. The switch Q8 is thereby controlled to clamp the phase output V_A to neutral during the second 180º of each cycle during off periods of the switch Q2.

The net effect of the above operation is to produce the waveform V_AN illustrated in Fig. 3 representing the phase output with respect to neutral. This phase output is filtered by the output filter 36 to produce the sine wave output V_PORA shown in dotted lines in Fig. 3.

The control of the remaining switches Q3-Q6 in the inverter is identical to that described above, it being understood that these switches are controlled in accordance with the variables F and DM so that the phase outputs V_B and V_C are displaced 120º with respect to one another and with respect to the phase output V_A. This displacement is accomplished by suitable timing of the enable signals coupled to the counters in the PTM's 76, 78.

The control of switches Q9-Q12 is accomplished by switch control circuits 131B, 131C and 136B, 136C, which are identical to the circuits 131A and 136A, with the exception that the circuits 13IB and 131C are coupled to the voltages V_PORB and V_PORC, respectively.

It should be noted that the internal timing of the CPU 68 is controlled by a high-speed clock signal of approximately 16 megahertz so that a change in the PWM pattern can be effected within a single output cycle. The response time can be minimized by use of a 16-bit microprocessor, such as a Motorola 68000. This ensures that the output is maintained within closely prescribed values with a minimum of control delay.

In the event the control 12 is to be utilized with the inverter shown in Fig. 2, the switches Q13, Q14, and Q15 would be controlled by the circuitry shown in Fig. 7. With specific reference to the control for the switch Q13, the switch control signals for the switches Q1 and Q2 are inverted by a pair of inverters 140, 142, respectively, and are coupled to an AND gate 144. The resulting signal is utilized to control the switch Q13 to cause it to conduct when both of the switches Q1 and Q2 are off. Control of the switches Q14 and Q15 is similar to that described with respect to switch Q13 , with the switch control signals for the switches Q1 and Q2 being replaced by those for the switches Q3 and Q4 or the switches Q5 and Q6, respectively.

As previously noted, each phase output may be individually controlled, i.e. the PWM pattern for each phase may be calculated according to the variable DM as derived for each phase. In practice, this generally results in different PWM patterns for each phase during an unbalanced load condition.

The current error signal shown in Fig. 4 may be utilized to disable the counters in the PTM's 76, 78 to deactivate the inverter in the event of a shoot-through or a cross conduction condition.

When the inverter is to be utilized as a constant frequency power supply, the frequency command shown in Fig. 4 may be dispensed with, as would be the blocks 110 and 112 shown in Fig. 6. In this case, the only variable in the equations (1)-(5) solved by the microcomputer 66 is the variable DM, thereby further simplifying the task of producing the necessary required PWM waveforms.

The control disclosed in the '177 patent identified above accomplishes a large reduction of harmonic content in the inverter output at relatively low values of DM. When DM exceeds such levels, however, the control of the present invention is preferable inasmuch as it eliminates up to the seventeenth harmonic and accomplishes a significant reduction in the nineteenth harmonic as compared with the control in the '177 patent. For a four-wire, three-phase system, the variable DM is typically at a high level, and hence this control is preferred under such circumstances over that disclosed in the '177 patent. Further, the asymmetric embodiments disclosed herein are preferred over the symmetric embodiment, inasmuch as the former eliminate the third harmonic and multiples thereof whereas the symmetric embodiment does not.

Furthermore, the last two asymmetric embodiments represented by the equations (7)-(12) achieve a still more favorable reduction in harmonic content in the inverter output for certain values of DM. Thus, if the expected values of DM are known in advance, the appropriate control technique can be selected to minimize harmonics in the output.

It should be noted that the control of the present invention can be utilized to reduce the DC content in the inverter output. In this case, a phase voltage at the point of regulation is coupled to separate positive and negative half-wave rectifiers so that DC signals representing the positive and negative portions of the output waveform are produced. The DC signals are individually compared to reference signals and the resulting signals are utilized to calculate first and second required PWM patterns to minimize the variation in the positive and the negative cycles from the reference signals. The results of these calculations may then be averaged to bring the positive and negative portions of the output waveform into balance and thereby minimize the DC content.

Of course, the DC content in the output of the inverter can be sensed in other ways. Also, the result of these calculations can be combined in another way to reduce DC content, if desired.

The above scheme can therefore take into account DC levels in the output generated by mismatch in component values or other factors.

Claims

1. A method of controlling a pulse width modulated (PWM) inverter having a pair of switches which are alternately operated to produce a series of pulses approximating a sinusoidal AC output waveform at a junction therebetween, the method comprising the steps of:

generating a magnitude signal representing a desired magnitude of a parameter of the AC output waveform;

defining a series of reference points spaced in time in accordance with an inverse trigonometric function of the number of pulses to be produced in a portion of the AC output wherein each reference point is associated with a pulse to be produced;

determining rising and falling edges of each pulse of the AC output relative to the reference point associated with such pulse in dependence upon the magnitude signal; and developing switch control signals for each switch from the determined rising and falling edges.

2. The method of claim 1, wherein the method is effected by a processor which accomplishes the defining and determining steps by calculating the positions of N pairs of rising and falling edges α_RN and α_FN, respectively, relative to N reference points according to the equations: αRN = α_REFN - β_IN; and

where α_REFN defines the positions of the N reference points and is equal to arcsin (2N-1)/P, P is the number of pulses to be produced in a half-cycle of the AC output, N is the number of a pulse in a quarter-cycle of the AC output such that N assumes integer values between 1 and (P+1)/2 and β_1N and β_2N are values which depend upon the magnitude signal.

3. The method of claim 2, wherein the processor effects the further step of calculating the values β_1N and β_2N according to the equations:

k₁ = 180(DM)/πF where DM is a value defined by the magnitude signal and F is the desired frequency of the inverter output.

4. The method of claim 2, wherein the processor effects the further step of calculating the values β_1N and β_2N according to the equations: β _1N = k₁[cos(arcsin (2N-2)/P) - cos(arcsin (2N-1)/P)]; β_2N - k₁[cos(arcsin (2N-1)/P) - cos(arcsin 2N/P)]; and k₁ = 180 (DM)/πF where DM is a value defined by the magnitude signal and F is the desired frequency of the inverter output.

5. The method of claim 1, wherein the method is effected by a processor which accomplishes the defining and determining steps by calculating the positions of N pairs of rising and falling edges α_RN and α_FN, respectively, relative to N reference points according to the equations: α_RN = α_REFN - β_1N; and

α_FN = α_REFN + β_2N where α_REFN defines the positions of the N reference points and is equal to arcsin P is the number

of pulses to be produced in a half-cycle of the AC output, N is the number of a pulse in a quarter-cycle of the AC output such that N assumes integer values between 1 and (P+1)/2 and β_1N and β_2N are values which depend upon the depth of modulation.

6. The method of claim 5, wherein the processor effects the further step of calculating the values β_1N and β_2N according to the equations:

k₁ = 180(DM)/πFF where DM is a value defined by the magnitude signal and F is the desired frequency of the inverter output.

7. The method of claim 1, wherein the method is effected by a processor which accomplishes the defining and determining steps by calculating the positions of N pairs of rising' and falling edges α_RN and α_FN, respectively, relative to N reference points according to the equations: α_RN = α_REFN - β_1N; and

α_FN = α_REFN + β_2N where α_REFN defines the positions of the N reference points and is equal to arcsin R_N, where R_N equals 2N/P when 2N/P is less than one and where R_N. equals one when 2N/P is greater than one, P is the number of pulses to be produced in a half-cycle of the AC output, N is the number of a pulse in a quarter-cycle of the AC output such that N assumes integer values between 1 and (P+1)/2 and β _1N and β_2N are values which depend upon the magnitude signal.

8. The method of claim 7, wherein the processor effects the further step of calculating the values slN and β_2N according to the equations: β_1N=k₁[cos(arcsin A_N)-cos(arcsin %R_N)];

B_2N=k₁[cos(arcsin R_N)-cos(arcsin B_N)]; and

k₁ = 180(DM)/πF where:

A_N=0 when N=1

and where DM is a value defined by the magnitude signal and F is the desired frequency of the inverter output.

9. The method of claim 1, wherein the developing step includes the steps of storing values representing the time duration between rising and falling edges in a memory and counting the stored values in a predetermined sequence to produce switch control signals for each switch to reduce the deviation of the AC output from the desired magnitude.

10. A control circuit for controlling a pulse width modulated (PWM) inverter having three switches per phase wherein the switches of each phase are alternately operated to produce a series of pulses approximating a sinusoidal AC phase output waveform at a common junction of the switches, comprising:

means for generating a depth of modulation signal representing the deviation of the amplitude of a phase output waveform from a reference level;

a memory for having a series of values which, when multiplied by a value, based upon the depth of modulation by signal, define rising and falling edges of each pulse in the phase output waveform relative to an associated reference point for such pulse wherein the reference points are spaced in time in accordance with an inverse trigonometric function of the number of pulses to be produced in a portion of an AC phase output waveform; and

means coupled to the memory for developing switch control signals for each switch from the defined rising and falling edges.

11. The control circuit of claim 10, further including a processor which calculates N pairs of rising and falling edges α_RN and α_FN, respectively, relative to N reference points α_REFN according to the equations: α_RN = α_REFN - β_1N; and

α_FN = α_REFN + β_2N where β_1N and β_2N are values which depend upon the depth of modulation signal.

12. The control circuit of claim 11, wherein the processor calculates the valves α_REFN, β_1N and β_2N according to the equations:

k₁=180(DM)/πF where P is the number of pulses to be produced in a half-cycle of an AC phase output waveform, N is the number of a pulse in a quarter-cycle of the AC phase output waveform such that N assumes integer values between 1 and (P+1)/2, DM is a value defined by the depth of modulation signal and F is the desired frequency of each AC phase output waveforms.

13. The control circuit of claim 11, wherein the prcocessor calculates the valves α_REFN ^, β_1N and β_2N according to the equations:

k₁=180(DM)/πF where P is the number of pulses to be produced in a half-cycle of an AC phase output waveform, N is the number of a pulse in a quarter-cycle of the AC phase output waveform such than N assumes integer values between 1 and (P+1)/2, DM is a value defined by the depth of modulation signal and F is the desired frequency of each AC phase output waveform.s.

14. The control circuit of claim 11, wherein the processor calculates the valves α_REFN, β_1N and β_2N according to the equations:

k₁ =180 ( DM) / πF where P is the number of pulses to be produced in a half-cycle of an AC phase output waveform, N is the number of a pulse in a quarter-cycle of the AC phase output waveform such than N assumes integer values between 1 and (P+1)/2, Dm iks a value defined by the depth of modulation signal and F is the desired frequency of each AC phase output waveforms.

15. The control circuit of claim 11, wherein the processor calculates the valves α_REFN, β_1N and β_2N according to the equations. β_1N=k₁[cos(arcsin A_N) -COS(arcsin R_N)]'

β_2N=k₁[cos(arcsin R_N)-cos(arcsin B_N)]; and

k₁=180(DM)/πF; and where:

where P is the number .of pulses to be produced in a half-cycle of an AC phase output waveform, N is the number of a pulse in a quarter-cycle of the AC phase output waveform such that N assumes integer values between 1 and (P+1)/2, DM is a value defined by the depth of modulation signal and F is the desired frequency of each AC phase output waveforms.

t '

16. The control circuit of claim 10, wherein the memory stores duration values representing the duration between adjacent rising and falling edges in a quarter-cycle of an AC phase output and further including a programmable timer which is sequentially loaded with the duration values and which decrements the values to zero, at which time a rising or falling edge is produced.

17. The control circuit of claim 16, which the duration values are loaded into the programmable timer in a particular sequence to produce a first quarter-cycle of the AC phase output and wherein the duration values are loaded in a sequence which is the reverse of the particular sequence to produce a second quarter-cycle subsequent to the first to thereby produce a half-cycle of an AC phase output.