WO1989012273A1

WO1989012273A1 - Testing method

Info

Publication number: WO1989012273A1
Application number: PCT/JP1989/000505
Authority: WO
Inventors: Masaki Seki; Takashi Takegahara; Shuji Sato
Original assignee: Fanuc Ltd
Priority date: 1988-05-30
Filing date: 1989-05-22
Publication date: 1989-12-14
Also published as: JPH01300348A

Abstract

A machine (1) being tested decodes an instruction sent from a tester (2), performs an operation or I/O control based on the instruction, and sends the result to the tester. The tester compares the result with a predetermined, expected value for coincidence and the result of processing or the I/O control is input to the testing machine which determines whether a memory (11) and an I/O unit (8) in the machine (1) being tested are acceptable or not.

Description

Specification

Test method

Technical field

The present invention relates to a test method, and more particularly, to a test method for checking the quality of hardware such as a CADZCAM system and a CNC device to be tested.

Conventionally, when checking a device under test such as a CNC device, a software for self-diagnosis is installed in the device under test, and a test is performed based on the software. The test results were displayed on the output device on the EUT. In addition, a dedicated test machine for the device under test was created, and electrical tests such as continuity chips were performed using the dedicated test machine.

However, there is a problem in that the conventional technology requires the production of a dedicated test machine and software, which requires too much time and cost for production.

Further, in the conventional technology, there is also a problem that if the output device of the EUT has no output device or if the output device of the EUT has failed, the test result cannot be confirmed even if the self-diagnosis is performed.

As described above, an object of the present invention is to provide a test method capable of performing a test using a general-purpose tester. Another object of the present invention is to provide a test method capable of lowering the cost of test-related equipment and confirming the test results using an output device of the tester.

Disclosure of the invention

The EUT decodes the command input from the testing machine, and Command or I / O control based on the instruction, and input the test result, which is the result of the process or I / O control, to the testing machine, and the testing machine matches the test result with the predetermined expected value Judge the quality of the hardware X of the EUT.

Brief description of drawings

FIG. 1 is a system configuration diagram for realizing the test method of the present invention, FIG. 2 is a configuration diagram of command data,

FIG. 3 is a flowchart for testing the memory of the EUT, and FIG. 4 is a flowchart of a process for testing the IZO section of the EUT.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a system configuration diagram for realizing the test method of the present invention.

In the figure, reference numeral 1 denotes a device under test, which corresponds to, for example, a CADZCAM system, a CNC device, a PC device, or the like. 2 is a general-purpose tester that can be used in common for various EUTs, 3 is a ROM that stores software used as decoding means and command execution means, and 4 and 5 are CPUs of the EUT and test equipment. is there. The CPU 5 decodes command data from the test machine 2 based on the software, and executes processing or I / O control based on the command. Reference numerals 6 and 7 denote serial ports for connecting the EUT 1 and the EUT 2 to transfer command data from the EUT 2 or serial data that is a test result from the EUT 1. Reference numeral 8 denotes an IZO port. For example, a light emitting die 8a indicating an operation state of the EUT 1 An output terminal for the light emission signal is provided. Reference numeral 9 denotes a check terminal, which is connected to the I / O port 8 of the device under test 1, and the CPU 4 receives the control result of the device under test from the check terminal 9. The flash state can be captured. 10 and 11 are memory (RAM), and the memory 10 of test machine 2 stores the processing result or I / O control result (normally called the expected value) of the EUT in response to the command during normal operation of the EUT. ) Is stored. Numeral 1 2 denotes a display device, which displays the quality of the hardware of the EUT 1.

The CPU 4 of the test machine 2 determines in advance the processing of the machine under test with respect to the command data input from the serial port 6 or the check terminal 9 or 1 〇 control results (called test results). The quality of the hardware under test 1 is judged based on the identity with the expected value. That is, when the test result and the expected value are the same, the EUT 1 is judged to be normal, and when the test result and the expected value are different, the EUT 1 is judged to be defective.

FIG. 2 is a diagram for explaining the configuration of command data. In the figure, (0), (1), (2), (3), (9), and (15) represent the digit positions of each command data, and CMD is a one-digit command part. There are a read instruction R (READ) for a specified address in the memory space or IZ〇 space, and a write instruction W (WRITE) for a physical address in the memory space.

MZI is a one-digit address space indicator, which is used for memory space. When specifying an address, the address space is specified by M, and when specifying the address of the I / O space, the address space is specified by I.

B / W is a 1-digit access unit designator. When it is accessed in units of 8 bits (1 knot), it is indicated by 、. When it is accessed in units of 16 bits (1 word), Indicates the access unit by W.

ADR is a 6 珩 input / output address indicator that indicates the start address of the memory space or IΖ space to be accessed 0 0 0 0 0 0 to FFFFFFF (hexadecimal notation). LEN is a 7 珩 input / output data number indicator, and indicates the number N of input / output data. DATA is a data part, and is N input / output data composed of 16 hexadecimal numbers.

In the following, the operation of the present invention will be described separately for a memory space test and an I / O space test.-Memory space test (see Fig. 3)

Command data shown below from test machine 2

r MB 0 12345 000003 5 A3C1j is transferred to the EUT 1 via the serial board 6 and the transfer data {5}, 3C, 21J is the expected value. It is stored in the memory 10 (steps 101, 102).

The EUT 1 decodes the above command data by the decoding means (R〇M3 software), and the EUT 1 executes the command according to the decoding result (steps 103 and 100). Four ) . In other words, the EUT 1 is a physical address 0 1 2 3 4 5 1-byte data “5Aj (hexadecimal)” in the memory of the memory, and 1-byte data “3C” in the memory of the physical address 0 1 2 3 4 6 (1 hexadecimal number) and 1-byte data Γ2 1 (16 hexadecimal number) are stored in the memory at the physical address 0 1 2 3 4 7. '' Then, test machine 2

`` RMB 0 1 2 3 4 5 0 0 0 0 0 3 ''

Then, the data stored in each address of the memory 11 (that is, “5A, 3C, 21”) is read (steps 105, 106).

The test machine 2 receives the data (“5A, 3C, 21j”) input from the device under test 1 via the serial ports 7 and 6 and the expected value stored in the memory 10. ("5A, 3C, 21j") is compared with (Step 107). If they match, the EUT 1 is judged to be normal and the display 12 is displayed normally. (Step 108).

On the other hand, if the data input via serial ports 7 and 6 is different from the expected value “5A, 3C,” like “5A, 3C, 22j” Displays the failure of the EUT 1 (step 109). In this case, I “Defective memory (address = 0 1 2 3 4 7)” is displayed on the display device 12 to clearly indicate the failure location.

1 〇 Space test (See Fig. 4)

Command data shown below from test machine 2

`` WIW 0 0 F 0 0 0 0 0 0 0 0 1 0 0 0 1 '' Is transferred to the device under test 1 via the serial port 6, and the transfer data “00001” is stored in the memory 10 as an expected value (steps 201, 202). . Address 0 0 F 0 00 in the I / O space (0 0 F 0 0 0 terminal of I / O port 8) corresponds to the terminal of light emitting diode 8a, and data Γ 0 0 0 1 J corresponds to the light emitting signal of the light emitting diode 8a.

The EUT 1 decodes the command data by the decoding means (software of the ROM 3), and outputs the light emission signal “0 0 1” to the 0 0 F 0 0 0 terminal of the 1 port 8 according to the decoding result. Is output, and the light emitting diode 8a is lit (steps 203, 204).

Thereafter, the test machine 2 detects the light emission state from the chip terminal 9 connected to the I / O terminal of the device under test 1 at address 0 0 F 0 00 (step 205). If a current is flowing, the data indicating the light emission state is “1”, and if the light is turned off and no current is flowing, the data is “0”). Then, the tester 2 checks whether the test result in the light emitting state and the expected value “00001” stored in the memory 10 are the same (step 206), and If so, the light emitting diode 8a of the EUT 1 is determined to be normal, and that fact is displayed on the display device (step 207).

On the other hand, if the data read through the check terminal 9 is different from the expected value Γ 0 Q 0 1 j, such as Γ 0 J, a defect of the light emitting diode 8 a is displayed (Step 2). 0 8). In this case, “LED failure (address = 0 0 F 0 0 0)” is displayed on the display device 12 to clearly indicate the failure location.

When the EUT 1 is normal, for example, a display such as “Memory 0 KJ” or “LEDOKJ” may be displayed. According to the present invention, a means for decoding a command from the test machine to the EUT is provided. The test equipment is connected to the test equipment via a serial port, and the 1〇 port of the test equipment is connected to the check terminal of the test equipment. The command input from the testing machine is decoded via the port and the test result based on the command is input from the serial port or the I and II ports to the testing machine. Since the quality of the hardware of the EUT is determined based on the identity with the predetermined expected value, a general method that can be used in common for each type of EUT Test equipment can be provided and test results can be output to the test equipment. It is a call to make sure Ri good, more can and child to reduce the co-be sampled of test related equipment.

Claims

The scope of the claims

1. In the test method in which the hardware of the EUT is checked by the testing machine,

Connect a small serial port, a memory, and a check terminal to the test machine, connect the UUT and the test machine with the serial port, and connect the IZO port of the UUT and the check terminal of the test machine. And

The test equipment transmits the command data to the EUT via the serial port, and stores the operation result when the EUT operates normally as the expected value in the memory.

The device under test decodes command data input from the test device via the serial port and executes processing or I〇 control operation based on the command data,

Thereafter, the test result based on the directive is input to the testing machine from the serial port or from the IZO board,

A test method, wherein the tester judges the quality of the hardware of the device under test based on the identity of the test result and the expected value stored in the memory.

When testing the memory of the EUT, the tester transmits a command to write data to the specified memory address of the EUT as command data, and the data is used as the expected value. Remember,

2. The test method according to claim 1, wherein data read from said memory address after writing processing of the device under test is used as a test result.

3. When testing the I / O part of the EUT, the tester transfers to the EUT a command to operate the specified 1〇 element as command data, and expects the operation result of the IZO element. Memorize it as a value,

2. The apparatus according to claim 1, wherein after executing the IZO control of the device under test, an operation state is read from a chip terminal corresponding to the IZO element, and the operation state data is used as a test result. Test method.