WO1989001702A1 - Procede d'oxydation locale de silicium - Google Patents

Procede d'oxydation locale de silicium Download PDF

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Publication number
WO1989001702A1
WO1989001702A1 PCT/GB1987/000575 GB8700575W WO8901702A1 WO 1989001702 A1 WO1989001702 A1 WO 1989001702A1 GB 8700575 W GB8700575 W GB 8700575W WO 8901702 A1 WO8901702 A1 WO 8901702A1
Authority
WO
WIPO (PCT)
Prior art keywords
oxide
layer
silicon
mesa
bird
Prior art date
Application number
PCT/GB1987/000575
Other languages
English (en)
Inventor
Shane Duncan
Original Assignee
Plessey Overseas Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to GB8614667A priority Critical patent/GB2192093B/en
Application filed by Plessey Overseas Limited filed Critical Plessey Overseas Limited
Priority to PCT/GB1987/000575 priority patent/WO1989001702A1/fr
Priority to JP50477887A priority patent/JPH02500872A/ja
Priority to EP19870905246 priority patent/EP0326549A1/fr
Publication of WO1989001702A1 publication Critical patent/WO1989001702A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape

Definitions

  • the present invention concerns improvements in or relating to processes which use local oxidation of silicon (LOCOS) to provide oxide isolation for silicon integrated circuit components.
  • LOCS local oxidation of silicon
  • the invention is intended to have application to processes for both bipolar and MOS device isolation.
  • LOC Local oxidation of silicon
  • LSI large-scale integration
  • VLSI very large-scale integration
  • the standard LOCOS isolation technique currently employed involves recessing a silicon surface to form a mesa, and thermally oxidising the exposed silicon surface in steam.
  • the top of the mesa is typically protected from oxidation by a nitride cap which is deposited on a thin stress relief oxide, to ensure minimal defect generation during oxidation.
  • the topography presented by the isolation oxide can cause problems with photolithography prior to metal deposition, where multiple angle reflections from the bird's beak produces a 'necking' effect in subsequent metal depositions.
  • the profile of the bird's head does not provide a suitable surface for metal coverage primarily due to a re-entrancy of the oxide at the bottom of the bird's head/field oxide region.
  • the coupled effect of a large bird's head and a re-entrant step could present severe problems for metal continuity, where cracking or 'mouse-holing' may be evident.
  • the present invention is intended to provide an alternative to the foregoing remedial processes, one that does not involve difficult processing operations.
  • the aim of the inventive process, as disclosed below, is to provide a more ideal planar surface for subsequent metal coverage, this by reducing the step height of the bird's head/field oxide.
  • a further aim of the inventive process herein is to suppress, or at least reduce, bird's beak encroachment, allowing thus more optimal use of the active areas enclosed within the boundaries of the field oxide isolation structure.
  • a local oxidation of silicon process a process of the type wherein a capped single crystal silicon mesa is defined in a silicon substrate and thereafter an isolating structure of local field oxide is grown by thermal oxidation of the silicon; characterised in that:- a layer of passive oxide is deposited upon the surfaces of the mesa cap, the mesa sidewall, and the silicon substrate prior to said thermal oxidation; thermal oxidation is performed in the presence of this layer; and, excess oxide removed thereafter by etching.
  • the inventive process disclosed here addresses the problem of surface re-entrancy and bird's head height from two standpoints. Firstly, the deposited layer of oxide relies on being non-conformal to the silicon surface, and thus exaggerates the corners at the bottom and top of the mesa. Secondly, an oxide thickness 0. Sex- will put oxidation kinetics in the parabolic regi ⁇ e thus effectively reducing any differential oxidation rate between the (100) and (111) crystal planes. The height of the bird's head is significantly reduced primarily due to visco-elastic flow of the oxide around the nitride edge. The presence of an oxide layer on the nitride allows a diffusion path for the expanding surface of oxidising silicon. BRIEF INTRODUCTION OF THE DRAWINGS
  • a mesa 1 is defined in a single crystal silicon substrate 3. As shown in figures 1 and 2 this is performed by growing a thin first layer 5, a layer of thermal oxide, at the surface of the substrate 3. In a typical process this layer 5 would be approx. 250A thick. This then is followed by the deposition of a second layer 7, a layer of an oxide-etch resistant material, typically nitride. Th c is preferably somewhat thicker, typically approx. 1000A.
  • nitride this may be performed by a low-pressure chemical vapour deposition technique, the details of which are well known and not therefore detailed here.
  • a layer 9 of resist is then spun onto the surface of the second layer 7. This then is selectively exposed and developed and the exposed part of the second layer 7 removed by an anisotropic etch - for example, by a plasma.
  • An illustrative cross-section of the substrate-and-structure at this stage of the process is
  • the layer 9 of resist is now stripped off eg. by ashing and the remanent part of the second .
  • layer 7 is used as a mask during etch removal of the exposed oxide part of the first layer 5. This may be performed using a selective wet etchant - eg. hydrofluoric acid (HF). Exposed silicon material is then
  • SUBSTITUTESHEET removed using an anisotropic wet etchant, for example, potassium hydroxide etchant isopropyl alcohol (KOH/IPA).
  • KOH/IPA potassium hydroxide etchant isopropyl alcohol
  • This step of the process thus defines a mesa 1 with sloping walls.
  • this etching step is continued until a depth of approx. 0.6 ⁇ o ⁇ of silicon is removed, which depth corresponds to the desired height of the mesa 1.
  • This capped mesa 1 is shown in figure 2.
  • a passive oxide deposition is performed.
  • a layer 11 of low-pressure chemical vapour depositon (LP CVD) oxide is blanket deposited over the recessed mesa 1 and substrate 3. This deposited layer 11 typically can be approx. 0.5pm thick and is undope .
  • the labels D Q ⁇ and H M are used to denote, respectively, the thickness (depth) of the deposited oxide layer 11, and, the height of the mesa 1 above the surrounding surface of the silicon substrate 3.
  • the silicon is oxidised by exposing the oxide covered structure to steam at a raised temperature.
  • Tn can be conducted at a temperature of 1050°C for a period of 8 hours, this allowing oxidation
  • oxide-etch resistant material eg. nitride 7, and of oxide material 5.
  • the bird's head/beak structure 13 is depicted in figure 4.
  • an approximation to a profile produced by this process is shown in bold outline.
  • an approximate profile produced by conventional processing is also shown, but in broken outline.
  • the thicknes-s of the oxide, and, the penetration length of the "bird's beak"- are depicted respectively by symbols T and B.
  • the slope angle 0 B of the "bird's head”, as measured relative to the normal to the plane silicon surface, is also labelled.
  • the inventive process is not restricted to the
  • SUBSTITUTESHEET Micrograph examination also shows there to be considerable etch-back smoothing of the profile at the base of the bird's head.
  • the angle 0 B is found to be approx. 45° compared to an angle of 15° subtended by the bird's head after conventional processing.
  • the step height of the bird's head is also found to be 0.5pm, respresenting a 50% reduction compared with that found conventionally, typically 1 height.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

Un procédé LOCOS (oxydation locale de silicium), un procédé du type dans lequel une structure (1, 3) mésa évidée recouverte, est définie dans du silicium monocristal, de qualité semiconductrice, après quoi, et en présence des couches (5, 7) de couverture, on fait gonfler thermiquement de l'oxyde local (13) afin de ménager une structure d'isolation. Ce procédé est modifié par l'introduction d'une couche (11) de dépôt d'oxyde passif destinée à couvrir le substrat (3), la mésa (1) et la couche (67) supérieure de couverture, avant le gonflement thermique de davantage d'oxyde (13). L'oxyde (13) ainsi obtenu est gravé en retrait afin de retirer la matière excédentaire. Cette modification a pour résultat une réduction de la hauteur de tête d'oiseau non planétaire, ainsi que la réduction de l'empiètement du bec d'oiseau dans la partie active du dispositif (3) au silicium. La rentrée à la base la tête d'oiseau (13) est également éliminée.
PCT/GB1987/000575 1986-06-17 1987-08-17 Procede d'oxydation locale de silicium WO1989001702A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB8614667A GB2192093B (en) 1986-06-17 1986-06-17 A local oxidation of silicon process
PCT/GB1987/000575 WO1989001702A1 (fr) 1987-08-17 1987-08-17 Procede d'oxydation locale de silicium
JP50477887A JPH02500872A (ja) 1987-08-17 1987-08-17 珪素の局部的酸化法
EP19870905246 EP0326549A1 (fr) 1987-08-17 1987-08-17 Procede d'oxydation locale de silicium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/GB1987/000575 WO1989001702A1 (fr) 1987-08-17 1987-08-17 Procede d'oxydation locale de silicium

Publications (1)

Publication Number Publication Date
WO1989001702A1 true WO1989001702A1 (fr) 1989-02-23

Family

ID=10610553

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1987/000575 WO1989001702A1 (fr) 1986-06-17 1987-08-17 Procede d'oxydation locale de silicium

Country Status (3)

Country Link
EP (1) EP0326549A1 (fr)
JP (1) JPH02500872A (fr)
WO (1) WO1989001702A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0095328A2 (fr) * 1982-05-21 1983-11-30 Kabushiki Kaisha Toshiba Procédé de réalisation d'un dispositif semi-conducteur par le contrôle de l'épaisseur de la couche isolante sur la partie périphérique de l'élement
GB2123605A (en) * 1982-06-22 1984-02-01 Standard Microsyst Smc MOS integrated circuit structure and method for its fabrication
GB2192093A (en) * 1986-06-17 1987-12-31 Plessey Co Plc A local oxidation of silicon process

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61111559A (ja) * 1984-11-05 1986-05-29 Sanyo Electric Co Ltd 半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0095328A2 (fr) * 1982-05-21 1983-11-30 Kabushiki Kaisha Toshiba Procédé de réalisation d'un dispositif semi-conducteur par le contrôle de l'épaisseur de la couche isolante sur la partie périphérique de l'élement
GB2123605A (en) * 1982-06-22 1984-02-01 Standard Microsyst Smc MOS integrated circuit structure and method for its fabrication
GB2192093A (en) * 1986-06-17 1987-12-31 Plessey Co Plc A local oxidation of silicon process

Also Published As

Publication number Publication date
EP0326549A1 (fr) 1989-08-09
JPH02500872A (ja) 1990-03-22

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