Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
  • G06N3/00—Computing arrangements based on biological models
  • G06N3/02—Neural networks
  • G06N3/10—Interfaces, programming languages or software development kits, e.g. for simulating neural networks

Definitions

• TITLE A COGNISANT SYSTEM
• THIS INVENTION relates to a cognisant system particularly adapted for managing and controlling a multitude of complex tasks using parallel processing. Moreover, the architecture of the system is of a form which can embody high level artificial intelligence to manage and' control the parallel processing of multiple and simultaneous events.
• Incumbent on any Artificial Intelligence system hardware engineer is the need to provide more efficient methods of dealing with the rapid growth of programme ranges and complexity. This requirement is addressed through so-called parallelism of processing which ideally will be accompanied by enhanced disc operating speeds such as 'head placement times' etc. Search techniques, relational data bases, content addressibility are among other techniques emerging in the pursuit of improved overall computer performance.
• Artificial Intelligence systems may be broadly divided into the two areas of deductive or inductive reasoning with: a_n overriding obligation for such systems to have the means t ⁇ learn.
• Some systems have been able to achieve low level intelligent status through the incorporation of stored logic adaptive microcircuits, neural networks, multi- layering, feed back mechanisms and short term memory, but as yet the progenitors of artificial intelligence have not developed machines that can learn by themselves. It would appear that a principal factor contributing to this inability is that designers still utilise basic constructs embedded in Von Neumann architecture and that in order to achieve a high level of artificial intelligence in a computer it is necessary to look towards other architectures which provide a more conducive environment to nurture cognisance within a machine structure.
• a cognisant system for managing and controlling a multitude of complex tasks using parallel processing comprising:-
• memory means adapted for receiving and presenting information for scrutiny by a said intelligent processor to determine storage of said information, said memory means having a series of memory elements arranged into prescribed locations to store said information;
• interface means to input and output information to or from the system
• said intelligent processors include a management means dedicated to organising and directing said information to said memory means received from said interface means to said memory means having regard to a cognisance of the system, and to organising and directing communications between said processors and said interface means.
• the discrete intelligent processors interact with each other and are also capable of performing tasks additional to said specific tasks.
• said information is relationally stored within said prescribed locations of said memory means.
• said memory means is partitioned into discrete memory partitions related to the tasks of said intelligent processors, whereby in ormation relevant to one task or another is stored in an appropriate memory partition to facilitate the relational ordering of information stored within said memory means.
• access of at least some of said intelligent processors is restricted to prescribed memory partitions.
• the particular intelligent processors for which access is restricted can be selectively chosen.
• said memory elements are addressed by content rather than by location.
• said memory means is capable of being accessed substantially simultaneously by at least some of said intelligent processors including said management means and being supplemented with information therefrom.
• the particular intelligent processors which are to have access to the memory means can be selectively chosen.
• said memory means comprises a main memory for storing enduring information and an active memory for storing transient information.
• said main memory is capable of being accessed substantially simultaneously by said management means and selected other said intelligent processors and is capable of being supplemented with information therefrom and from said active memory.
• said active memory is capable of being accessed substantially simultaneously with accesses to said main memory by said management means and being supplemented with information therefrom.
• said main memory comprises a matrix of said memory elements which are interconnected to permit independent and simultaneous access thereto by a plurality of intelligent processors operating in parallel.
• said management means comprises an administrator means to monitor and administer the basic operation of said system having regard to some of said information related to its tasks stored within said memory means, and an executive controller means to monitor and administer the overall operation of the system having regard to all of the information stored within the memory means.
• said administrator means is capable of monitoring said intelligent processors and interface means for contingencies and for maintaining cognisance of the operational state of the system, and directing communication of selected information between said intelligent processes and interface means.
• said administrator means is also capable of interacting with said intelligent processors, memory means and executive controller means to resolve said contingencies.
• said administrator means is capable of hierarchically ordering the performance • of its tasks according to urgency of operation.
• executive controller means is capable of selectively interacting with said intelligent processors, memory means and said administrator means to resolve contingencies requiring the cognisance of said executive controller means as provided by its ability to access all of the information within said memory means, and overseeing the operation of the system.
• said interface means includes a channeller to channel certain types of information input to the system directly to said administrator means and other types of information directly to other said intelligent processors in a manner whereby said other types of information can still be scrutinised by said administrator means.
• said active memory comprises a short term memory and an iconic memory, whereby said short term memory is dedicated to:
• any one or more of said intelligent processors include means for performing the following tasks:
• identity recognition processing for decoding an encoded input for the purposes of identity recognition
• the intelligent processors may be capable of performing tasks additional to tasks (i) to (v) above.
• the cognisant system 11 generally comprises a plurality of intelligent processors including processors A involved with specific tasks and management means B, a memory means C, an interface means D, and areas of association (not shown) between the intelligent processors A.
• the interface means D connects the system to a series of external devices E
• the intelligent processors A and B each comprise a microprocessor and local resident memory to house firmware and application software, which control the operation of the processor, and to perform its requisite processing functions in accordance with the firmware and application software directions.
• the processors A are arranged functionally into means for graphics processing 13, means for identity recognition 15, output processing means 17, input processing means 19, speech synthesis processing means 21, speech recognition processing means 23, and image recognition processing means 25.
• the processors A which provide means for graphics processing 13 have the primary assignment of processing, generating and displaying graphics information for output to appropriate graphics output devices at E. This is performed in accordance with a computer program containing appropriate algorithms for the processor and is stored in the firmware 47 of the system dedicated thereto. When necessary, the processor 13 can instantaneously access an allowed portion of the memory means C for stored information necessary for the processor to perform its task.
• the processors A which provide means for identity recognition 15 have the primary assignment of decoding an encoded input such as a security card, fingerprint, identikit, etc., for the purposes of identity recognition. Again these processors have a computer program containing appropriate algorithms stored in firmware 47 dedicated thereto and has instantaneous access to an allowed portion of the memory means C when required.
• the output processor ' 17 is committed to performing intelligent processing of information for output purposes which is to be transmitted through the interface means D to an external device E. As in the previous processes, this processor has a computer program containing algorithms stored in firmware 47 dedicated thereto and has instantaneous access to allowed portions of the memory means C when required.
• the input processor 19 is committed to performing intelligent processing of information for input purposes received through the interface means from an external device E.
• the input processor has a computer program containing algorithms stored in firmware 47 dedicated thereto and has instantaneous access to allowed portions of the memory means C when necessary.
• processors 21, 23 and 25 are self-explanatory and as in the previous processors each have a computer program containing their algorithms stored in firmware 47 dedicated thereto and each have instantaneous access to allowed portions of the memory means C when required.
• a special telecommunications processor 45 also constitues an intelligent processor and is located externally of the system as one of the external devices E. The basic function of this processor is to control bidirectional communications between the system and some external device which is intelligent. Accordingly the processor handles protocol operation and communicates with other processors and the memory means via the management means.
• the memory means comprises a series of memory elements arranged into prescribed locations to store information therein.
• the prescribed locations of the memory means are partitioned into discrete memory partitions which are generally related to the tasks performed by the intelligent processors A.
• information relevant to one task or another to be performed by an intelligent processor is stored in an appropriate memory partition to facilitate relational ordering of information within the memory means.
• the memory means includes a main memory and an active memory.
• the main memory comprises a long term memory 27 for storing enduring information and the active memory comprises a short term memory 29 and an iconic memory 31 both adapted for storing transient information for different periods of time.
• a resident memory is provided by firmware 47.
• the long term memory 27 is of a design which is particularly characterised to facilitate parallel processing.
• the memory is a high density, read/write memory having memory elements interconnected in a matrix.
• the memory elements are interconnected in such a manner as to permit simultaneous addressing by a number of different processors A and B.
• Information is stored within the prescribed locations of the memory elements in a relational manner so that each prescribed location contains information relationally ordered therein. Consequently, addressing of a memory element by an intelligent processor is made according to content rather than location.
• the long term memory 27 permits the retention of information so as to form a knowledge base which is conditionally accessible by the various processors A and is selectively accessible by the management means B.
• the memory means C can be embodied in appropriate media which is capable of acting as a storage element.
• memory elements may comprise magnetic media which can be read or written to by a sensor head, or alternatively the elements may comprise solid state electrical charge storing devices which can be addressed by electronic means.
• the memory elements may be embodied in new forms of memory technology such as laser memories or the like. It should be appreciated, however, that the memory elements need to be interconnected in such a manner as to allow the simultaneous addressing of two or more memory elements by a plurality of processors. Thus, memory structures enabling parallel memory access are utilised rather than structures which only permit serial memory access.
• the interface means D essentially comprises an information channeller.33, and input/output ports 39 for porting information externally to and from the system. Accordingly, the ports 39 are connected to external devices E such as output devices 41, input devices 43 and the special telecommunications processor 45.
• Output devices 41 may comprise displays, printers, digital control outputs, local status indicators and the like.
• Input devices may comprise local interactive inputs, analogue inputs, digital inputs and the like, and the telecommunications processor 45 may comprise receiving and transmitting circuits for connection to various communication protocols including both asynchronous and synchronous protocols such as RS232, 20mA current interface, RS422, BYSYNC, DDCMP, HDLC and the like.
• asynchronous and synchronous protocols such as RS232, 20mA current interface, RS422, BYSYNC, DDCMP, HDLC and the like.
• the channeller 33 is in the form of an interactive interface which channels selected information received by the interface means D directly to appropriate intelligent processors A and B.
• the management means B comprises two executive members: an administrator means or administrator 35, and an executive controller means or intellect 37.
• the administrator 35 and intellect 37 are special intelligent processors which enable the management means to manage the entire operation of the system by dividing the management task amongst its subordinate members in a hierarchical fashion.
• the administrator 35 performs a relatively higher level of processing than the processors A and is essentially in the form of a reticular activating system which co-ordinates all input and output occurrences in a hierarchical manner. Moreover, the administrator essentially monitors and administers the basic communicating operations within the system.
• the intellect 37 constitutes the highest order intelligence of the system and has the power to oversee operation of the system and resolve contingencies therein having regard to information stored within the entire memory means C.
• the functions of both the administrator and intellect are determined by the resident firmware of each respectively and can be achieved using conventional software development techniques.
• the areas of association between the intelligent processors comprise any suitable means along or through which communications can be conveyed.
• the means may comprise buses along which data can be transferred from one processor to another so as to allow instantaneous communication between processors associated in this manner.
• one processor can have a plurality of areas of association to enable a plurality of processors to share resources in performing a task.
• the intelligent processors A and B are arranged so that any processor has instant direct access to any relevant memory element thereto in the long term memory 27. As graphically shown in the diagram, this access is directed by the firmware of the processors being permanently integrated, as symbolically represented at 47. Additionally, each task related processor A can interact with the administrator 35 and intellect via a reticular communications network 49 represented by the stippled arrows in the drawing. Furthermore, interaction can be provided between any processor A and the intellect 37 via the firmware 47 and areas of association of the system.
• the long term memory 27 as previously described is capable of being accessed by any of the processors A and the intellect 37 via the firmware 47. Additionally, the long term memory is capable of being accessed by the intellect 37 and administrator 35 via the reticular communications network which has a direct route of access through the short term and iconic memories 29 and 31 to the long term memory via paths 50 and 51, respectively. Selected memory elements of the long term memory are supplemented with information from the short term memory 29 as determined by the intellect 37, the task related processors A, and the administrator 35.
• the short term memory 29 is capable of direct interaction with the intellect 37 alone and conditional interaction with the administrator and processors A.
• the short term memory 29 essentially comprises an erasable memory which is dedicated to temporarily storing short term transient information from the iconic memory 31. This information is only stored within the memory unit for relatively short time periods for the purposes of monitoring and selective use by the intellect at the discretion of the latter. Accordingly, transient information which is stored within the short term memory 29 eventually decays after a short time period whereby if the intellect 37 has decided not to supplement the long term memory 27 with this information, it is discarded from the short term memory .
• the iconic memory 31 again is capable of direct interaction with the intellect 37 alone and conditional interaction with the administrator and processors A but is served by information transmitted thereto by the system administrator 35.
• the iconic memory 31 is dedicated to temporarily storing transient information for an extremely short time period for selection by the intellect 37 at the discretion of the latter.
• the iconic memory comprises a first in first out status register which holds information for a transitory time period, being much less than the short time period of the short term memory 29, before such information decays and is discarded from the memory via the path represented by the arrow 53.
• the intellect 37 accordingly monitors the iconic memory 31 at its discretion and determines an item of information therein to be of relevance to the system. It supplements the short term memory 29 at its discretion with information for further consideration.
• the interface means D interacts with the administrator 35 or with the processors A. Direct interaction with the administrator is only provided through the ports 39 in respect of certain types of information transmitted or received via the path 55. Indirect interaction with the administrator 35 is provided via the channeller 33 in respect of certain types of information received from the ports 39 via the path 57, which is destined for input to a processor. This indirect interaction is provided by the path 59 connected between the channeller and administrator 35 along which selected information chosen by the administrator can be received. Moreover, all output information from the system is transmitted to the input/ output ports 39 via the path 55, and selected input information to the system is received either via paths 55 or 57, depending upon the predetermined nature and significance of the information type.
• the channeller 33 acts as a means for channelling input information from the interface means D to administrator 35 and/or appropriate processors A.
• the system administrator 35 performs the bulk of the basic administrator tasks of the system and interacts with most of the components of the system. Accordingly, its administration tasks are largely dedicated, whereby it performs four major functions:
• the system administrator 35 When the system administrator 35 recognises a contingency, it may order the processing of the contingency in a hierarchical manner with respect to other tasks to be performed by it, and can resolve the contingency, if necessary, by access to the appropriate processor(s) , memory, and/or the intellect 37 via the reticular communication network 49. Additionally, the administrator 35 can convey certain information it acquires from its monitoring and administrator tasks at its discretion for scrutiny by the intellect, by conveying the same directly to the iconic memory unit 31.
• the intellect 37 is the master of intelligence in the system and is capable of selective interaction with all of the processors A, all of the memory means C, and the administrator 35. This permits the intellect to resolve contingencies which require cognisance of the entire operation of the system and to provide information for subordinate management decisions. Accordingly, the intellect 37 is in a superior position to resolve such contingencies than is the administrator 35.
• the principal advantage of the invention as provided by the present embodiment is that the system defines an architecture which permits a level of complex deductive reasoning to be provided by artificial means for interpreting and responding to a multitudinous and complex set of events.
• the system achieves this by employing a . very high . speed group of integrated and parallel processors having rapid parallel .access to a vast array of stored information, logic algorithms and managing tasks according to a highly ordered executive task allocation and delegation structure.
• High processing speeds are attained by arranging the processing means in a structure which permits parallel processing to be performed whereby each processor can be assigned a specific task to be performed concurrently or in parallel with the other processors.
• addressing of the memory is effected by association to the content of the information and by having information storage within the main memory organised according to content rather than by chronological ordering or the like.
• a processor may move directly to the memory element containing the information sought, by association to the content of the information, rather than by serially stepping through a large amount of unrelated information until the desired information is located.
• a further consideration to high speed is the fact that any processor should be able to get to the sought information immediately rather than having to wait in a queue. Accordingly, by adopting the present long term memory structure, concurrent access to memory elements is permitted so as to avoid contesting access with other processors.
• memory means and management means use of a symbolic language is preferably employed. Moreover the various functions and tasks of the system are coded symbolically to facilitate reference thereto during communications. Consequently, memory requirements by using a high level symbolic language are small but execution speeds are high.
• the various algorithms of the processing means are written as symbolic programs dedicated to operating the processors according to the function or task they are to perform. Accordingly, these programs are stored in the appropriate firmware 4 .

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• 1988
  • 1988-06-30 BR BR888807601A patent/BR8807601A/pt unknown
  • 1988-06-30 WO PCT/AU1988/000227 patent/WO1989000735A1/en not_active Application Discontinuation
  • 1988-06-30 EP EP19880905614 patent/EP0371979A4/en not_active Withdrawn
  • 1988-06-30 DE DE883891254T patent/DE3891254T1/de not_active Ceased
  • 1988-06-30 AU AU19910/88A patent/AU613062B2/en not_active Ceased
  • 1988-06-30 HU HU884170A patent/HUT52263A/hu unknown
  • 1988-06-30 JP JP63505677A patent/JPH03501069A/ja active Pending
  • 1988-06-30 NL NL8820470A patent/NL8820470A/nl not_active Application Discontinuation
  • 1988-07-04 NZ NZ225276A patent/NZ225276A/xx unknown
  • 1988-07-06 IL IL87009A patent/IL87009A0/xx unknown
  • 1988-07-07 ZA ZA884888A patent/ZA884888B/xx unknown
  • 1988-07-08 IE IE211188A patent/IE61262B1/en not_active IP Right Cessation
  • 1988-07-08 ES ES8802149A patent/ES2009964A6/es not_active Expired
  • 1988-07-08 MY MYPI88000756A patent/MY103116A/en unknown
  • 1988-07-09 CN CN88106022A patent/CN1013071B/zh not_active Expired
  • 1988-07-11 PL PL27367088A patent/PL273670A1/xx unknown
  • 1988-07-11 DD DD31781488A patent/DD272718A5/de not_active IP Right Cessation
• 1989
  • 1989-03-10 KR KR1019890700439A patent/KR0136877B1/ko not_active IP Right Cessation
• 1990
  • 1990-01-09 DK DK005590A patent/DK5590A/da not_active Application Discontinuation
  • 1990-01-09 GB GB9000409A patent/GB2228808A/en not_active Withdrawn
  • 1990-01-09 SE SE9000064A patent/SE464943B/sv not_active IP Right Cessation

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