WO1988008564A1 - Procede pour transmettre des donnees entre l'unite centrale d'un systeme informatique serveur et l'unite centrale d'un systeme informatique a coprocesseur - Google Patents

Procede pour transmettre des donnees entre l'unite centrale d'un systeme informatique serveur et l'unite centrale d'un systeme informatique a coprocesseur Download PDF

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Publication number
WO1988008564A1
WO1988008564A1 PCT/US1988/001166 US8801166W WO8808564A1 WO 1988008564 A1 WO1988008564 A1 WO 1988008564A1 US 8801166 W US8801166 W US 8801166W WO 8808564 A1 WO8808564 A1 WO 8808564A1
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WO
WIPO (PCT)
Prior art keywords
data
computer system
dual port
port memory
computer
Prior art date
Application number
PCT/US1988/001166
Other languages
English (en)
Inventor
Dieter Preiss
Frank-Thomas Ullmann
Original Assignee
Commodore-Amiga, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commodore-Amiga, Inc. filed Critical Commodore-Amiga, Inc.
Publication of WO1988008564A1 publication Critical patent/WO1988008564A1/fr
Priority to NO885742A priority Critical patent/NO885742L/no

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Definitions

  • the present invention relates, in general, to microprocessor controlled video games and personal computers and, more particularly, to the communication between the cen ⁇ tral processing unit ("CPU") of a host computer system and that of a co-processor computer system to provide application software compatibility.
  • CPU cen ⁇ tral processing unit
  • a large number of personal computers are available on the market today. Typically, each of the personal computers is restricted in its operation to application software designed specifically for the particular computer system. Also typi ⁇ cally, the library of available application software for one particular computer system does not contain all of the programs found in the libraries of application software of other com ⁇ puter systems. When application software is not available for a specific computer system, it would be most beneficial to be able to utilize the different but noncompatible application of another computer system.
  • a specific computer system may have su ⁇ perlative processing speed, enhanced graphics, enhanced sound, and/or other high performance capabilities not available in the computer system which enjoys a large or different library of application software.
  • the noncompatible application software could be used within the computer system having the high performance capabilities so that the better processing enhancements provided by the high performance capabilities could be used with the noncompatible software.
  • the Amiga system is a low-cost, high performance computer with advanced graphics features, sound features, and high speed per ⁇ formance.
  • the Amiga system is not IBM-PC/XT ("PC") compatible and, thus, cannot use the library of PC application software which is readily available on the market.
  • the Amiga personal computer has a low-cost, high per ⁇ formance graphics and sound system for state of the art video game and personal computer applications.
  • the system includes three custom integrated circuits controlled by a Motorola 68000 16-32/-bit microprocessor as the CPU. These custom chips, des ⁇ ignated Agnus, Denise, and Paula, provide extraordinary color graphics on a standard TV or on a color video minotor with arcade quality resolution and depth to display video games, cartoons, low.resolution photographs and up to 80 characters of text on the .screen.
  • the sound circuits can duplicate complex wave forms on each of four channels, matching commercial synthesizers in quality.
  • the Amiga computer system has multitasking capability, that is, it can perform more than one program at a time and is interrupt driven.
  • the Amiga computer system is available as the Amiga 1000 computer and the Amiga 2000 computer. .
  • the differences between the two Amiga computer systems are not relevant, and reference will be made to the Amiga 2000 computer system for simplicity.
  • the hardware of an Amiga 2000 is shown in block diagrammatic form in Fig. 1.
  • Fig. 2 shows in simplified block diagrammatic form the similarities and differences between the hardware of the Amiga 1000 computer system designated element 8 and the Amiga 2000 computer system designated element 10, with respect to data traffic.
  • Fig. 1 is the Amiga computer system's hardware and buses, collectively desig ⁇ nated as element 10.
  • the hardware includes the Motorola 68000 CPU 12, the three custom chips (that is, Angus 14, Denise 16, and Paula 18), and the 100 pin expansion Amiga bus slots 20. Also shown are the ports for the peripherals of computer system 10 such as keyboard port 22, parallel port 24, serial port 26, and video port 28. Additionally, an 86 pin local expansion CPU bus slot 30 and associated data, address, and control buses are illustrated.
  • the entire interrupt driven Amiga computer system 34 with its software is shown diagrammatically in Fig. 3.
  • the software includes the Kickstart and Workbench operation system 36 and various available Amiga application software packages 38, 40, 42, ' 44 to run on the multi-tasking system 34. Also shown are keyboard 46, printer 48 and video monitor 50 connected to the appropriate ports 22, 24, and 28.
  • FIG. 4 Diagrammatically presented in Fig. 4 is a PC compati ⁇ ble computer system 52 including PC hardware 53 with an Intel 8088 CPU 54, PC operating system 56 (that is, BIOS and MS-DOS), and a selected PC application software package 58, such as IBM's "Flight Simulator" program. Since the PC system itself is not multi-tasking, only one application program can be run on that system at one time. Like the Amiga system, the PC system is interrupt driven. Also shown are various periph ⁇ erals for PC compatible system 52 such as keyboard 60, printer 62, and video monitor 64.
  • the Amiga computer system While the Amiga computer system has high performance capabilities, including superlative graphics and high pro ⁇ cessing speeds, it cannot, standing alone, run PC application software. By extending the Amiga computer system to be compat ⁇ ible with PC application software, not only can additional pro ⁇ grams be run on the Amiga computer sytsem, but also the high performance processing capability of the Amiga computer system can enhance the PC application software.
  • an object of the invention to provide a method for allowing normally noncompatible application software to be utilized by a host computer system
  • Another object of the invention is to provide a meth ⁇ od for high speed communication of data between the central CPU of a host computer system and the CPU of a co-processor com ⁇ puter system which processes application software which is not compatible with the host computer system.
  • Still another object of the invention is to provide a method for providing data communication between a host computer system and a co-processor computer " system in such a manner that the communication process is transparent to the host computer system user and to the co-processor computer system.
  • Still another object of the invention is to provide a method of creating a PC environment in a co-processor computer system to run PC application software for use in a host com ⁇ puter system which is normally not PC compatible.
  • a method of communicating data between the central processing unit (CPU) of a host computer system and the CPU of a co-processor computer system the method using a dual port memory connected to the data and address buses of the CPUs, is provided.
  • CPU central processing unit
  • the method includes requesting in one of the two computer system one of a plurality of functions to be performed; generating, using the requesting computer system-, parameter data representing the requested function; trans ⁇ ferring, using the requesting computer system, the parameter data to the dual port memory; storing the parameter data in the dual port memory, issuing, using the requesting computer sys ⁇ tem,, an interrupt to the other one of the two computer systems, the interrupt indicating to the other one of the two computer systems the type of function requested, the parameter data in the dual port memory based on the interrupt received to perform the requested function.
  • the method also includes the steps of issuing to the requesting computer system at the completion of the requested function, using the other one of the two computer systems, an acknowledgement of the completed requested function and erasing the stored data from the dual port memory using the other one of the two computer systems.
  • the method further includes the step of processing requests for access to the dual port memory made by the CPUs one at a time on a first-come, first-serve basis.
  • the method includes the step of translating the transfer data issued by one of the two computer systems into a data format usuable by the other of the two computer systems before the transfer data is stored ' in the dual port memory.
  • Fig. 1 is a block diagram of the hardware of the Amiga 2000 computer
  • Fig. 4 is a system diagram of a PC compatible com ⁇ puter including software
  • Fig. 5 is a system diagram helpful in explaining the method of the invention.
  • Fig. 6 is another system diagram helpful in explaining the method of the invention.
  • Fig. 7 is the block diagram of Fig. 2 showing the PC compatibility system in place;
  • Fig. 8 is a diagram showing the various portions of a dual port RAM used in a preferred embodiment of the invention.
  • Fig. 9 is a block diagram of the details of the interface hardware shown in Fig. 5.
  • Fig. 5 aft overview of the sytem for enhancing a host computer system to allow the host system to be compatible with PC application software.
  • the host computer system 66 includes the basic Amiga computer sys ⁇ tem illustrated in Fig. 3, that is system 34.
  • the enhancement includes Amiga operating system extension 68, co-processor com ⁇ puter system 70, and interface hardware 72 which provides interprocessor communication between CPU 12 of the host system (Motorola 68000) and CPU 54 of the co-processor system (Intel 8088) .
  • Co-processor computer system 70 in Fig. 5 includes hardware and software necessary to create a PC environment and also includes PC application software to run in that environ ⁇ ment.
  • co-processor computer system 70 is a PC- type interrupt driven computer system with an 8088 CPU 54, RAM, ROM, and support chips less peripherals and includes a PC oper ⁇ ating system extension 74 discussed below.
  • Monochrome and color graphics adapters are also included in the co-processor computer system.
  • the remainder of the co-processor system is emulated on the host system side of the interface hardware.
  • the Amiga system reconfigures the data being generated by input on keyboard 46 to appear as PC keyboard data for use by the PC system.
  • the Amiga system also emulates a PC printer port on its own paral ⁇ lel port so that the PC system can use printer 48, and displays the PC video output in both monochrome and color on video monitor 50.
  • interface hardware 72 is used between the host computer system and the co-processor computer system.
  • the operating system extensions 68 and 74 manage and use interface hardware 72 to allow rapid interprocesor communi ⁇ cation between CPU 12 of the host computer system 66 and CPU 54 of co-processor computer system 70.
  • the main component of interface hardware 72 is' a dual port random access memory 76 (DPRAM) connected to the data and address buses of the two CPUs 12, 54. This memory is shared by both CPUs to accomplish communication between the CPUs. Other memories, of course, could be used as long as access can be made from more than one port. Such a memory, for the purposes of this disclosure, is called a dual port memory.
  • DPRAM dual port random access memory
  • SUBSHTOT ⁇ E SHEET systems 66, 70 can, of course, communicate directly with its respective operating systems 36, 56. Additionally, however, any task requested in one operating system can communicate to the operating- system of the other computer system and request that the processing system perform the requested task. For example, if a specific task is requested in the host computer's operating system 36 requesting that PC operating system 56 exe ⁇ cute a specific function, the operating system can communicate with interface hardware 72 via operating system extension 68 and set up parameter data in a specified are of the DPRAM of the interface hardware to perform the requested function. Operating system 36 causes an interrupt to be transmitted to co-processor system 70 which interrupt indicates to the co ⁇ processor system the type of function requested.
  • the interrupt driven co-processor computer system accepts the function re ⁇ quest and performs the necessary program based on the interrupt received to execute the function, including accessing the parameter data in the DPRAM which is included in the interface hardware 72.
  • co ⁇ processor computer system 70 Upon the completion of the execution, co ⁇ processor computer system 70 returns an acknowledgment through its operating system extension 74 and interface hardware 72 to provide an interrupt to operating system 36. This -acknowl ⁇ edgement notifies operating system 36 that the requested func ⁇ tion has been completed.
  • a PC application program can run, for example, output data to be displayed on a video monitor. As discussed later, that data is then placed into the appropriate DPRAM location, particularly into the video RAM portion fo the DPRAM.
  • That action bf the co-processor system causes an inter ⁇ rupt to issue to the host computer system 66 which recognizes it as a video memory interrupt.
  • the host system accesses the appropriate loca- tion in DPRAM 76 and processes the video memory into the host computer system's video monitor 50.
  • interface hardware 72 The interface between host computer system 66 and co ⁇ processor computer, system 70 provided by interface hardware 72 is interrupt driven. All functions in the computer systems are requested by interrupts. Hardware in interface hardware 72 automatically issues hardware interrupts to host CPU 12 or co ⁇ processor computer' system 70 or host computer system 66, re ⁇ spectively. Furthermore, software applications can define new classes of events which allow either of the computer systems to use the facilities of the other, thereby creating an extended multiprocessor environment.
  • predefined events occur ⁇ ring in co-processor computer system 70 which generate hardware interrupts to be acted upon by the host computer system can in ⁇ clude requests by the co-processor computer system to access the color video memory of DPRAM 76, access the mono-chrome video portion of the DPRAM, access the mono CRT register, accessor the color CRT register, access the line printer regis ⁇ ter, access the serial data register, and read the keyboard register.
  • Predefined events from the host computer system which force interrupts on the co-processor computer system in the preferred embodiment, can include accessing the keyboard register, accessing the serial data register, and accessing the line printer register.
  • Inter ⁇ face hardware 72 can be added to allow the programs on both sides of inter ⁇ face hardware 72 to communicate in any way desired. This could include, for example, code execution by one of the CPU's, including full access to all system functions of each operating system.
  • the CPU of the co-processor computer system could, for example, create a task in the host computer system's multi ⁇ tasking environment and then instruct the task to execute host computer system library calls.
  • the host computer system in turn, can request software interrupts on the co-processor com ⁇ puter system.
  • SUBSTITUTESHEET must be informed with information on the appropriate function to undertake. These non-predefined events or logical events require the use of parameter blocks as discussed below.
  • DPRAM 76 in the preferred embodiment, is a 128K byte memory into which data is transferred from one of the computer systems for use by the other of the computer systems.
  • General purpose RAM area 88 is a 64K byte area used as a general purpose buffer
  • color video RAM 90 is a 32K byte area used for PC color video memory
  • monochrome video RAM 92 is an 8K byte area for PC monochrome video memory.
  • a 16K byte area is designated as a parameter RAM 94.
  • Parameter RAM 94 provides two functions. First, both the host computer 66 and the co-processor computer 70 use one byte of parameter RAM 94 to assist the two systems in successfully sharing the DPRAM. Specifically, the byte is a "lock byte" used by either of the computer systems to signal that a new portion of general purpose RAM 88 is being alocated or freed. A check of this lock byte by one of the computer systems indicates whether the other of the computer systems is allocating data to a portion of the memory or is freeing a portion of the memory. If that is the case, the com ⁇ puter attempting to allocate or free a portion of the memory will wait until the other system is completed in its allocating or freeing and has so indicated that completion by configuring the lock byte to the "unused" status.
  • parameter RAM 94 The second function of parameter RAM 94 is to hold blocks of parameters set by one computer which the other com ⁇ puter reads. For example, when host computer system 66 desires, an action which is not one of the preferred events discussed above which automatically generates the appropriate hardware interrupt, for example, the transfer of a block of data to co ⁇ processor system 70, the transferring data is read into. and- held by general purpose RAM 88 of DPRAM 76 until that data is read out of that address by co-processor system 70.
  • Parameter RAM 94 holds information necessary to perform the transfer, for example, the length and location of the data to be transferred and the desired destination of that data in the co-processor system, which information has been set by the computer re ⁇ questing the transfer, in this instance, host computer 66.
  • I/O page RAM 96 Also included in DPRAM 76 is a final 8K byte area designated the I/O page RAM 96. It is used to perform various services such as mapping certain address ranges on the host computer system side of the interface hardware. On the co ⁇ processor system side of the hardware the I/O page RAM area contains a standard set of I/O register locations for the co ⁇ processor system that are used to control the serial and paral ⁇ lel ports and the PC monochrome and color CRT controller.
  • SUBSTITUTE SHEET In the preferred system described herein concerning an Amiga computer system as host, computer system 66 and the co ⁇ processor system 70 which creates a PC.environment for runing PC application software, two support chips are provided to assist in the interprocessor communication achieved through the sharing of DPRAM 76. The details of those chips in interface hardware 72 are shown in Fig. 9. The two chips, called data bus translator (“DBT”) 98 and address bus translator (“ABT”) 100, are shown in block diagrammatic form connected to the CPU buses and control buses of both host computer system 66 and PC compatible co-processor computer system 70.
  • DBT data bus translator
  • ABT address bus translator
  • DBT 98 functions as a data bus transceiver for 68000 data bus 82 and for the 8088 data bus 86 to interface those data buses with DPRAM 76. More specifically, DBT 98 contains data translato-r 102 which functions to interface the 68000 CPU 12 of the host computer system to the DPRAM. Specifically, data translator 102 provides three transfer mechanisms. First, a word transfer operation is provided to realign bytes in . accordance with individual processor requirements of the host and co-processor systems. Host CPU 12 stores the most signifi ⁇ cant byte at the low-order address while co-processor CPU 54 stores the most signficant byte at the high-order address. Data translator 102 provides this word transfer mechanism to make realignment ' automatic whenever data is written across interface hardware 72. Thus, this realignment places data in one of the computer systems into a format usable by the other system.
  • data translator 102 provides byte transfer operations which transfer data straight across the interface hardware without the byte swap which occurs in the word trans ⁇ fer operation described above.
  • data translator 102 also provides a graphics transfer mechanism which is used to sepa ⁇ rate PC graphics data into discrete bit planes required by the host computer system. The graphics transfer mechanism substan ⁇ tially reduces the amount of software overhead necessary to display PC graphics on video monitor 50.
  • a specific example of the graphics transfer mechanism is illustrated and discused in an article titled "The Commodore A2000" found at pages 84-98 of the March 1987 issue of BY E magazine.
  • Transceiver 104 of DBT 98 functions as a high-speed data-transceiver.
  • Auto config 108 of DBT 98 provides an autoconfiguration protocol which is used to insure that periph ⁇ eral boards are installed into the system at boot-up. Auto config 108 automatically configures the co-processor system 70 into the host computer system 66 memory map during system boot.
  • control 110 of DBT 98 functions to provide control signals for driving the various functions performed in DBT 98. Control 110 contains the base address comparator, address, decoders, and other circuits which support the interface hard ⁇ ware operation.
  • the second chip in interface hardware 72 is ABT 100. It provides PC address translation, DPRAM arbitration, inter ⁇ rupt control- logic, and keyboard emulation. Concerning address translation, ABT 100 translates co-processor system memory and I/O addresses into appropriate locations in the memory map of DPRAM 76 shown in Fig. 8. Any I/O request recognized by the ABT 100 as being I/O device emulated by the host computer system 66 triggers the translation function. For example, if host computer system 66 on the parallel port emulation and co ⁇ processor system 70 attempts to write to the printer data port, ABT 100 will generate the address for the printer data port's location in DPRAM 76. ABT 100 also maps various co-processor system memory requests into DPRAM 76, for example, video memory accesses to monochrome video RAM 92 or color video RAM 90 of the DPRAM show in Fig . 8.
  • ABT 100 arbitrates access requests to DPRAM 76 between host computer system 66 and co-processor system 70.
  • the two computer systems utilize inde ⁇ pendently generated clocks, thus requiring DPRAM requests to be synchronized to prevent conflict.
  • the requests are serviced on a first-come, first-serve basis as discussed above.
  • ABT 100 also provides DPRAM timing signals and DPRAM refresh signals as necessary.
  • ABT 100 With respect to the interrupt control logical func ⁇ tion of ABT 100, when either one of the computer systems places information in DPRAM 76 as a predefined event, ABT 100 gener ⁇ ates an interrupt to the other one of the computer systems as necessary. In the printer port example described above, an in ⁇ terrupt to host comp ' uter system 66 will occur to inform that system, by its reading of a register in ABT 100, that the printer data has been updated so that the host computer system 66 will take appropriate action on that data.
  • ABT 100 The last function of ABT 100 concerns keyboard emula ⁇ tion. Since the system described, here uses keyboard 46 of the host system for data input to the co-processor system 70, the keyboard input from keyboard 46 must be translated into a key ⁇ board equivalent for loading DPRAM 76 so that co-processor system 70 can utilize the information. Thus, another function of ABT 100 is to serialize the keyboard data received from host computer system 66 for use in co-processor system 70. Specifi ⁇ cally, the Amiga host system loads an ABT register with a byte of keyboard data from keyboard 46. Thus, the. ABT encodes the data serially for use by the co-processor system.
  • PC compatibility system 78 has been described in association with Fig. 9 for the host computer system 34.
  • the system is connected to the CPU bus of the host computer system and allows true PC displays to be intermixed with all the dis ⁇ plays available on the host computer system itself.
  • the PC video information can be displayed in standard windows of the multi-tasking host computer system. Additionally, all PC video modes are supported, that is monochrome and color text and color graphics, which can be displayed simultaneously in dif ⁇ ferent windows on host video monitor 50.
  • the video portion of the co-processor system memory is mapped directly into mono ⁇ chrome video RAM 92 or color video RAM 90 of DPRAM 76. That writing is a predetermined event and is performed by the co ⁇ processor system BIOS screen I/O routines.
  • the co ⁇ processor system action causes the transmission of a hardware generated interrupt signal to the host computer system which informs that computer system that there has been activity in the video memory portion, that is, portion 90 or 92 of DPRAM 76, and the host system acts accordingly on that data. Since this mapping is transparent to co-processor system 70, the video display is -completely compatible both to applications that use the ROM BIOS in the co-processor system and to appli ⁇ cations that word directly with the with the video memory in that system.
  • the host system's keyboard 46 and serial and parallel ports 24," 26 can be used by the PC co-processor system as dis ⁇ cussed above.
  • the method of communicating a monochrome or color video display from co-processor system 70 to video monitor 50 on the Amiga host system 66 is discussed.
  • a PC "Flight Simulator" program is running on the co-processor system which is to be displayed in the video monitor on the host system.
  • the co ⁇ processor system using its BIOS screen I/O routines as dis ⁇ cussed above writes the information into the monochrome video memory 92 or into color video memory 90 of DPRAM 76 as deter ⁇ mined by the specific output data.
  • the computer system requesting the operation that is co-processor system 70, has therefore requested a function to be performed and has transferred the data to the DPRAM. Since the function desired by the requesting computer is one of the predefined events a hardware interrupt issues' to the other one
  • the interrupt indicates to the host computer system the type of function requested, that is, a video memory request.
  • the host computer system acting on the informative interrupt accesses he data in the appropriate video RAM portion of DPRAM 76 and acts on the data contained therein.
  • the host system updates the PC video display shown on host computer system video monitor 50.
  • the host system upon completion of the requested function, informs the requesting computer system (in this instance, co-processor system 70) by way of acknowledgment that the requested function has been completed. That acknowledgment initates the erasing of the data temporarily stored on the DPRAM.
  • the requesting computer system is the host computer system which wishes to write a block of data into the specific portion • of the memory in co-processor system 70.
  • the specific function is a "peek/poke" memory function.
  • the host computer system When the peek/poke function is requested in host computer system 66, the host computer system generates data representing the requested function and, in this instance, would request allocation of memory in parameter RAM 94 and in general purpose RAM 88 of DPRAM 76. Then, the host system provides the data on how the function is to be performed to DPRAM 76.
  • the data would include the address in the co-processor system to be written, how many bytes of data are to be transferred, and where in the general purpose RAM the actual data is stored.
  • the actual data is then transferred from the host system into the designated portion of general purpose RAM 88. That data is temporarily stored in the DPRAM.
  • the host system calls the peek/poke memory function and issues an interrupt to the interrupt driven co-processor system 70.
  • the interrupt is received by the co-processor system, that system will be informed that the host system desires the transfer of data .to the co-processor system; and, therefore, the co-processor system takes action to examine parameter RAM 94 for data on the specific function requested.
  • the co-processor system locates in and trans ⁇ fers the data from general purpose RAM 88 to the designated final location within the co-processor system.
  • the co-processor After that data has been transferred, the co-processor generates and transfers an acknowledgment of completion to the host system.
  • the memory in DPRAM 76 allocated for the specific func- tion is cleared so that the memory will be available for other tasks.
  • a method is provided to allow the high performance host computer system to utilize PC application software as desired.
  • the user of the host system can enjoy the available library of PC application pro ⁇ grams which otherwise would be unavailable.
  • the user can process the PC programs in a multi-tasking environment using enhanced graphics made capable by the host system.

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  • Theoretical Computer Science (AREA)
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Abstract

Un procédé pour transmettre des données entre l'unité centrale (''UC'') (12) d'un système informatique serveur (66) et l'unité centrale (54) d'un système informatique à coprocesseur (70) permet l'utilisation par le système serveur de logiciel d'application non compatible. Ce procédé consiste à utiliser une mémoire à accès sélectif à double accès (76) partagée entre les UC (12, 54) des deux systèmes informatiques pour la communication interprocesseur.
PCT/US1988/001166 1987-04-23 1988-04-12 Procede pour transmettre des donnees entre l'unite centrale d'un systeme informatique serveur et l'unite centrale d'un systeme informatique a coprocesseur WO1988008564A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
NO885742A NO885742L (no) 1987-04-23 1988-12-23 Fremgangsmaate til aa utveksle data mellom sentralprosessoren i et vertsdatamaskinsystem og sentralprosessoren i et datamaskinsystem med koprosessor.

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US4153387A 1987-04-23 1987-04-23
US041,533 1987-04-23

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WO1988008564A1 true WO1988008564A1 (fr) 1988-11-03

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EP0426412A2 (fr) * 1989-10-31 1991-05-08 Canon Kabushiki Kaisha Appareil électronique composite
EP0843254A2 (fr) * 1990-01-18 1998-05-20 National Semiconductor Corporation Processeur de traitement de signaux numériques et processeur universal intégré avec mémoire interne partagée
CN1097919C (zh) * 1996-12-27 2003-01-01 三星电子株式会社 用于个人数字助理的打印机和打印方法
EP1271307A1 (fr) * 2000-03-03 2003-01-02 Sony Computer Entertainment Inc. Dispositif de divertissement compatible et systeme informatique

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US5313614A (en) * 1988-12-06 1994-05-17 At&T Bell Laboratories Method and apparatus for direct conversion of programs in object code form between different hardware architecture computer systems
CA2002201C (fr) * 1988-12-06 1999-04-27 John Charles Goettelmann Methode de traduction

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