WO1988007242A3 - Modificateur de calcul arithmetique se fondant sur des operations dependantes de donnees - Google Patents

Modificateur de calcul arithmetique se fondant sur des operations dependantes de donnees Download PDF

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Publication number
WO1988007242A3
WO1988007242A3 PCT/US1988/000670 US8800670W WO8807242A3 WO 1988007242 A3 WO1988007242 A3 WO 1988007242A3 US 8800670 W US8800670 W US 8800670W WO 8807242 A3 WO8807242 A3 WO 8807242A3
Authority
WO
WIPO (PCT)
Prior art keywords
status
conditions
arithmetic units
shift register
bits
Prior art date
Application number
PCT/US1988/000670
Other languages
English (en)
Other versions
WO1988007242A2 (fr
Inventor
Ray E Artz
Richard J Martin
Vincent E Splett
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Publication of WO1988007242A2 publication Critical patent/WO1988007242A2/fr
Publication of WO1988007242A3 publication Critical patent/WO1988007242A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/264—Microinstruction selection based on results of processing
    • G06F9/265—Microinstruction selection based on results of processing by address selection on input of storage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Complex Calculations (AREA)

Abstract

Des unités arithmétiques (12-14) se trouvant dans un processeur SIMD sont configurées de sorte que l'état est calculé sur la base de conditions arithmétiques. Cette étape peut refléter des conditions telles que ''A > B'', ''A = 0'' ou ''dépassement de capacité''. L'état mis en place dans un processeur SIMD dépend de l'application spécifique du processeur. Les valeurs 0 ou 1, qui représentent des conditions d'état vrai ou faux, sont généralement maintenues dans une bascule d'état (41). L'un des bits (42) de la bascule d'état peut ensuite être sélectionné au moyen d'un multiplexeur (43) (la sélection s'effectuant au moyen d'une instruction provenant de l'unité de commande), ledit bit étant appelé la condition sélectionnée (44). Cette condition sélectionnée est introduite par décalage sériel dans un registre à décalage d'état (45). Les bits d'état accumulatifs provenant de différents calculs de données peuvent être accumulés dans le registre à décalage d'état, où le nouveau bit de condition sélectionné est introduit par décalage, et tous les bits d'origine se trouvant dans le registre à décalage d'état sont décalés d'une position vers la gauche. Ces conditions d'état accumulées peuvent être ensuite être ajoutées à l'adresse commune dont sont pourvues toutes les unités arithmétiques. On obtient la capacité de modifier les adresses de mémoire à l'intérieur des unités arithmétiques sur la base de calculs de données, ainsi que la possibilité d'exécuter des algorithmes dépendant de données à l'intérieur du processeur SIMD, sans la perte d'efficacité qu'on trouve dans les procédures d'activation/désactivation conditionnelles, étant donné que les unités arithmétiques sont actives en permanence.
PCT/US1988/000670 1987-03-17 1988-03-07 Modificateur de calcul arithmetique se fondant sur des operations dependantes de donnees WO1988007242A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US026,913 1987-03-17
US07/026,913 US4792894A (en) 1987-03-17 1987-03-17 Arithmetic computation modifier based upon data dependent operations for SIMD architectures

Publications (2)

Publication Number Publication Date
WO1988007242A2 WO1988007242A2 (fr) 1988-09-22
WO1988007242A3 true WO1988007242A3 (fr) 1988-10-20

Family

ID=21834512

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1988/000670 WO1988007242A2 (fr) 1987-03-17 1988-03-07 Modificateur de calcul arithmetique se fondant sur des operations dependantes de donnees

Country Status (2)

Country Link
US (1) US4792894A (fr)
WO (1) WO1988007242A2 (fr)

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Publication number Priority date Publication date Assignee Title
US5212777A (en) * 1989-11-17 1993-05-18 Texas Instruments Incorporated Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation
US5471593A (en) * 1989-12-11 1995-11-28 Branigin; Michael H. Computer processor with an efficient means of executing many instructions simultaneously
EP0485594A4 (en) * 1990-05-30 1995-02-01 Adaptive Solutions Inc Mechanism providing concurrent computational/communications in simd architecture
US5175858A (en) * 1991-03-04 1992-12-29 Adaptive Solutions, Inc. Mechanism providing concurrent computational/communications in SIMD architecture
JPH07500437A (ja) * 1991-10-24 1995-01-12 インテル　コーポレイシヨン データ処理システム
US5361370A (en) * 1991-10-24 1994-11-01 Intel Corporation Single-instruction multiple-data processor having dual-ported local memory architecture for simultaneous data transmission on local memory ports and global port
US5440702A (en) * 1992-10-16 1995-08-08 Delco Electronics Corporation Data processing system with condition code architecture for executing single instruction range checking and limiting operations
US5322108A (en) * 1993-10-04 1994-06-21 Hoffman Robert E Two section slat for roll-type shutters
DE19532527C2 (de) * 1995-09-02 2000-06-15 Winfried Gehrke Verfahren zur dynamischen assoziativen Steuerung von Parallelprozessoren
GB2352536A (en) 1999-07-21 2001-01-31 Element 14 Ltd Conditional instruction execution
US6842811B2 (en) * 2000-02-24 2005-01-11 Pts Corporation Methods and apparatus for scalable array processor interrupt detection and response
HUP0102356A2 (hu) * 2001-06-06 2003-02-28 Afca-System Kft. Eljárás és kapcsolási elrendezés előnyösen ciklikusan ismétlődő adatfeldolgozási feladatok párhuzamos üzemű végrehajtására, továbbá az eljárás végrehajtásához szükséges műveleti kódok előállítására és szimulálására szolgáló programrendszer
US7127593B2 (en) * 2001-06-11 2006-10-24 Broadcom Corporation Conditional execution with multiple destination stores
US7802076B2 (en) * 2004-06-24 2010-09-21 Intel Corporation Method and apparatus to vectorize multiple input instructions
US7725691B2 (en) * 2005-01-28 2010-05-25 Analog Devices, Inc. Method and apparatus for accelerating processing of a non-sequential instruction stream on a processor with multiple compute units

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1036644A (en) * 1964-05-14 1966-07-20 Ibm Improvements in or relating to data processing machines
EP0121763A2 (fr) * 1983-03-08 1984-10-17 Alcatel N.V. Processeur associatif en réseau
US4521858A (en) * 1980-05-20 1985-06-04 Technology Marketing, Inc. Flexible addressing and sequencing system for operand memory and control store using dedicated micro-address registers loaded solely from alu
US4574348A (en) * 1983-06-01 1986-03-04 The Boeing Company High speed digital signal processor architecture

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US4101960A (en) * 1977-03-29 1978-07-18 Burroughs Corporation Scientific processor
US4380046A (en) * 1979-05-21 1983-04-12 Nasa Massively parallel processor computer
US4287566A (en) * 1979-09-28 1981-09-01 Culler-Harrison Inc. Array processor with parallel operations per instruction
US4539635A (en) * 1980-02-11 1985-09-03 At&T Bell Laboratories Pipelined digital processor arranged for conditional operation
US4435758A (en) * 1980-03-10 1984-03-06 International Business Machines Corporation Method for conditional branch execution in SIMD vector processors
JPS57155666A (en) * 1981-03-20 1982-09-25 Fujitsu Ltd Instruction controlling system of vector processor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1036644A (en) * 1964-05-14 1966-07-20 Ibm Improvements in or relating to data processing machines
US4521858A (en) * 1980-05-20 1985-06-04 Technology Marketing, Inc. Flexible addressing and sequencing system for operand memory and control store using dedicated micro-address registers loaded solely from alu
EP0121763A2 (fr) * 1983-03-08 1984-10-17 Alcatel N.V. Processeur associatif en réseau
US4574348A (en) * 1983-06-01 1986-03-04 The Boeing Company High speed digital signal processor architecture

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
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Association for Computing Machinery, Proceedings of 1971 Annual Conference, 3-5 August 1971, Chicago, Illinois (New York, US), pages 508-519 *
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Also Published As

Publication number Publication date
US4792894A (en) 1988-12-20
WO1988007242A2 (fr) 1988-09-22

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