WO1988000774A1

WO1988000774A1 - Audio amplifier

Info

Publication number: WO1988000774A1
Application number: PCT/US1987/000680
Authority: WO
Inventors: Robert Ponto
Original assignee: Robert Ponto
Priority date: 1986-07-17
Filing date: 1987-03-30
Publication date: 1988-01-28
Also published as: WO1988000773A1

Abstract

A power supply and audio amplifier system including an audio amplifier system adapted to receive an audio signal (AD) which is supplied to an attenuator (70) which receives the signal and selectively attenuates the signal which is then supplied to a buffer (80) and filter circuit (90) to condition the signal. The attenuated, filtered, signal (99) is then supplied to a modulator (100) where it is converted to a square wave signal having a pulse width a function of the level of the audio signal. The square wave pulse signal is then supplied to a push-pull converter (110) to generate an alternating current signal which is supplied to the primary coil (P3, P4) of a transformer (T3, T4) an amplified output signal is supplied to a load (L) from the secondary (53A, 53B, 54A, 54B) of the transformer. The load characteristics are analyzed and a loading signal is supplied to a clipper circuit (220) which prevents the output from exceeding selected load limits.

Description

DESCRIPTION

AUDIO AMPLIFIER

TECHNICAL FIELD

The present invention relates to signal amplification systems and power supply systems and more particularly to low signal distortion amplifiers and power supply systems particularly useful in connection with such amplifier systems, as well as other purposes. Various amplifier and power supply systems are known and have been used in the art for many years in connection with audio systems and for other pur-poses.

In general power supply arrangements for audio systems, and particularly for audio amplifier systems, must be operable over a wide range of audio frequencies with least signal distortion possible in response to frequency change.

BACKGROUND ART

Various prior art amplifier arrangments are known to provide acceptable audio frequency response but, in general, the cost of such systems has been found to increase directly in proportion to efficiency. Also amplifier systems for providing quality audio can be quite expensive.

Further no prior art system is known to provide an inexpensive power supply arrangement and an inexpensive amplifier arrang eπt to receive an audio signal and provide substantially distortion free response over a wide range of audio frequencies and at high loading with very high efficiency.

Moreover, no prior art arrangement is known where the amplifier operating characteristics are responsive to the instantaneous load on the output of the system in order to avoid overloading the system and where signal distortion which inherently occurs in the event of changing load in prior art amplification systems is substantical ly reduced by limiting the input to the device.

Moreover, no prior art audio smplifier system is known which provides "push-pull" mode of operation of the type provided by devices within the scope of the present invention. Numerous prior art systems are known which utilize pulse width modulation techniques to attempt to accomplish the objectives of the present invention.

Also, no prior art power supply is known which anticipates devices in accordance with the present invention which utilize MOSFET (metal oxide si licon field effect transistors) to provide a high efficiency power supply based on generation of a square wave signal of selected frequency where the square wave signal is then used to convert a direct current supply to alternating current in a transformer where the secondary voltage is closely controlled over a. wide range of current range.

In one known instance, as disclosed in U.S. Patent

No. 4,554,512 driver means utilizing Mosfet devices to operate an RF frequency amplifier system.

In general, no prior art amplifier or power supply system is known which yields the efficiencies and the characteristics of devices within the scope of the present invention utilizing. DISCLOSURE OF THE INVENTION

The present invention provides new, useful, and particularly inexpensive, but effective, arrangements for power supply and audio amplifier systems.

More particularly, the present invention provides audio systems which can accommodate change in loading of the system yet maintain quality of response and avoid the adverse characteristics of various prior art arrangements under similar changes by providing a system which limits the power which can be supplied by the unit but is substantially unaffected by overdriving the input of the system so long as the permitted power levels are not exceeded.

Additionally, a power supply can be provided for use with audio systems of the present invention which is economical to fabricate and which utilizes dual transistor switches which allows enhanced speed of operation yet minimize power loss through destructive heat generation and leads to improved overall efficiency of the power supply.

Additionally, multiple voltage outputs can be provided from secondary windings of a transformer associated with the power supply where a change in power consumption at one of the outputs does not neces_.sarily cause a change in the power available at other outputs. More particularly the present invention provides a power supply and audio amplifier system including an audio amplifier system adapted to receive an audio signal which is supplied to an attenuator which receives the signal and selectively attenuates the signal which is then supplied to a buffer and filter circuit to condition the signal. The attenuated, filtered, signal is then supplied to a modulator where it is converted to a square wave signal having a pulse width a function of the level of the audio signal. The square wave pulse signal is then supplied to push-pull converter to generate an alternating current s'ignal which is supplied to the primary coil of a transformer and amplified output signal is supplied to a transformer. The load characteristics are analyzed and a loading signal is supplied to an clipper circuit at the input to the device which prevents the output from exceeding selected load limits.

A power supply system is provided including a pulse signal generator to operate transistor devices to supply square wave current pulse through an inductive coil at a rate determined by a clock where such current is supplied as a square wave and where, the square wave pulses drive first transformer which operate first and second switches for example field effect transistors to gate supply power to the primary coil of second 6 transformer in push-pull relation in response to the pulsed output signal from the pulse signal generator arrangement to improve efficiency and reduce losses in the conversion. Amplifier devices within the scope of the present invention further provide filter arrangements to allow wide variation in output loading without substantially affecting audio characteristics of an associated audio amplifier.

Examples of arrangements within the scope of the present invention are illustrated in the accompanying

Figures which will be understood are by way of illustration and not by way ^"of limitations and that various other arrangements also within the scope of the present invention will occur to those skilled in the art upon reading the disclosure set forth hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

Examples within the scope of the present invention are il lustrated in the accompanying drawings wherein:

Figure 1 is a schematic illustration of an example of a power supply within the scope of the present invention;

Figure 2 is a flow illustration of an audio ampl ifier system also within the scope of the present invention;

Figure 3A-3C present a more detailed schematic of the amplifier system shown in Figure 2;

Figure 4 is a graphic illustration of a signal generated in accordance with one feature of the present invention;

Figers 5 is a simplified flow diagram of a driver arrangement within the scope of the present invention; and

Figers 6A-6N illustrate signal characteristics at selected locations in the schematic of Figure 5 as well as the signal components. BEST MODE FOR CARRYING OUT THE INVENTION

Figure 1 illustrates a power supply useful in devices within the scope of the present invention as well as other applications. A direct current voltage source VDC for example a 120 VAC rectified supply is provided across input terminals 41, 42. A current sensing fuse 21 and a temperature sensitive fuse 22 are provided in terminals 41 and 42 along with a filtering capacitor CH. Terminals 41, 42 are connected through transistors^'Q41, Q42 gated by windings L2A, L2B of transformer 44 so that as the transistors Q41, Q42 are gated current flows through the transistors tό^; the primary coil PI of a transformer Tl. Windings L2A, L2B are operated directly in response to operation of pulse width modulator 40, for example part number 3524 which utilizes transistors Q40A, Q40B to supply a pulsed outputs 43-43A to drive the bases of transistors Q43, Q44 and supply current to winding Ll, the primary coil for secondary coils L2A, L2B by means of core 44. Pulsing current to coil Ll is supplied through a coupling capacitors C2A and C2B and transistors Q43, Q44 are provided to amplify signal 43 to the primary coi 1 Ll.

The resistor capacitor network R1,-C1, provides a damping network while the capacitor C4 provides a current blocking arrangement. Diodes D-, , D_? are clamping diodes and capacitor C- acts as a bypass capaci tor .

Clamping diodes 03, D4 are provided, as shown, across the base emitters of transistors Q43, Q44 to allow internal transistors Q40A, Q40B in modulator 40 to drive the rising edge of a pulse and transistors Q43 and Q44 to drive the falling edge of the pulse which is inherently slow in a modulator at a relatively low switching rate. It has been found that such an arrangement avoids the inefficiencies commonly encountered in the operation of, similar prior art devices. A control circuit 46 is provided to be operated through transistor 31 to pulse regulator 40 which is unique in that it provides three things not available with a pulse width modulator: 1. It provides voltage regulation to pulse regulator 40 in response to characteristics set by zener diode Zl.

2.) It provides a soft start by controlling pulse regulator 40 during turn on at a rate fixed by capacitor C53.

3.) It provides under voltage protection by shutting off modulator 40 ti ll the input voltage reaches the characteristic voltage of zener diode Zl.

The particular configuration shown includes diodes D31-D33 capacitor C50, C51 and resistors R50-R53 arranged as shown to permit low speed operation and enhance operating efficiency. Further, is known that the normal filtering requirements of prior art devices intended to accomplish the objectives of devices in accordance with the present invention reduce in direct proportion to frequency but it has been unexpectedly found that with a square wave output of the type supplied to coil Ll in devices accordance with the present invention practically no filtering is needed at the low frequency operating point.

Since modulator 40 operates in a push-pull mode current flow is generated through the primary PI of transformer Tl at the rate set by the pulse width modulator 40 which provides an inexpensive means of setting dead time between the on-off cycles of transistors Q41, Q42 to enable generation of a square wave output of desired characteristics through the primary PI of transformer Tl as opposed to, for example an inverter transformer used in the prior art which drives with no dead time.

It has been further found that a square wave function with ve ry small (less than 1% ) dead time generated in the supply to the primary unexpectedly greatly increases the efficiency of the system and reduces losses. The pulse width modulator 40 is driven in response to clock pulses provided by means of input 68 from a clock (described hereinafter) to an opto- coupler 0P41 provided to isolate pulse width modulator 40 where the isolated clock pulses are provided at to modulator 40 input 48. Output 47 i s a 5 volt REF voltage. The Pot P2 is the primary frequency determing element of pulse width modulator 40, and the pulses from input 68 to modulator 40 syncronize.

Referring now to the power supply output characteristics which illustrate another feature in accordance with the present invention, a higher voltage output from the secondary SI, is provided through a rectifier circu t RCT1 which includes dio^'des D2T1-C5T1 and capacitor C2T1 -to terminals 51, 52 and is also supplied through a zener diode D6, which limits the overall voltage from the device by way of an opto isolator 0P42 by means of output 52 from collector of the transistor of isolator 0P42 which is connected to a control input of pulse width modulator 40 to control the output pulse width in response to the output voltage from secondary SI. Whi le other control system typically use similar means as a way of regulating the power supply designs within the scope of the present invention do not use it except for over voltage protection, not regulation. This is significant because: 1.) Because using such arrangement for regulations causes unacceptable levels of^" audio noise which degrade the performance of the amplifier; and,

2.) Use of such an arrangement for regulation causes the modulator 40 to generate a pulse width modulated signal which is not a square wave which has been found to be important in devices in accordance with the present invention.

The logic output of the AND gate of isolator 0P41 is connected through lead 48 through capacitor C48 to the pulse width modulator 40 as previously described. The outpu^'t drives the modulator 40 to sychroniz^'e operation of modulator 40 with the clock input 68 from the clock system described hereinafter. A resistor R48 is provided in the output 55 to act as a pullup while capacitor C48 is provided as a differentiating capacitor to generate small spikes.

In accordance with another feature of the present invention it has been found that precise output voltage control with varying load can be achieved principally because the drive to the primary of the transformer 44 is a square wave. It has further been unexpectedly found that the output voltages at terminals 53-54 generated by secondary S2 and supplied through a standard rectifier circuit RCT2 including capacitors C2T2-C4T2, Diodes D2T2, D3T2 and voltage regulators VR1, VR2 are regulated, with ve ry little loss in the regulators because of the close control of the input vo 1 tage 56 , 57.

Figure 2 is a flow chart illustration of an example of an amplifier device within the scope of the present invention to provide a general understanding of one example of a device within the scope of the present invention. A more detailed description of one example of a device within the scope of the present invention is shown in Figures 3A-3C.

In Figure 2 an audio signal AD is provided to an amplifier circuit 60 which provides an ampl ified- audio signal 69. Signal 69 is supplied to a digital attenuator 70 which attenuates the signal, for example, in a binary mode, that is ldB, 2dB, 4, 8, 16, 32. etc. up to 63dB in ldB steps. The attenuated output signal 79 is supplied to a buffer 80 which then supplies a buffered signal 89 to a high pass, low pass filter combination 90, (which can be a multiple order filter) to supply a fi ltered attenuated signal 99 of selected ch aracteri sties.

Signal 99 is supplied to modulator 100 which converts the alternating signal to a pulse width modulated signal M which is reflective of the characteristics of the output signal 226 and AD from the device as described hereinafter. An output M from modulator 100 is then supplied to a gating system 110 which generates a 4 phase output Ql, Q2, Q3, Q4, where 02 is the inverse of 01 and 04 is the inverse of 03 then to drivers 120, 121, 130, 131 to generate signals 129, 139 which are utilized to drive the primary coils P3, P4 of transformers T3 and T4 . The secondary coils 53A, 53B, 54A, 54B are connected in a 4 phase mode operated at a rate determined by the characteristics of output drivers 140, 160, 180, 200 to supply alternating power to a load L. A feedback signal 226 is supplied from filter circuit 210 to modulator 100 to indicate loading on the circuit. Signal 226 is also supplied to a clipper circuit 220 which supplies an output signal 225 to the filter output 99 to override or clip the audio signal in the event the signal indicates a load at L exceeding a selected load limit as well as an input signal exceeding a selected input level, as described hereinafter.

Referring now to Figure 3A which illustrates in more detail an example of an attenuator and amplifier system useful within the scope of the present invention an amplifier A60 is connected in a differential mode to receive input AD through coupling capacitors C21, C22 and adjusting resistors R21, R22 to supply a signal 23 to a signal attenuation switch network 24. The switch network consists of a number of solid state switches SW1-SW6, SW1B-SW6B cooperatively connected to switches SW1A-SW6A which in the example are manual switches to operate the solid state switches SW1-SW6 by means of inverting buffers B1-B6 but it will be understood that other means such as programmable controllers can also be used.

Resistor ladders (R1A-R6A), (R1B-R6B) (R1C-R6C) are provided and sized to achieve binary attenuation by appropriate adjustment of the switches SW1A-SW6A to attenuate the signal in a binary format. That is, switch SW1A introduces a one dB change in characteristics wh'ile switch SW2A introduces a change of 2 dB, switch SW3A introduces a change of 4 dB and so on until switch SW6A introduce a change of 32 dB so that by proper selection of the switches any decibel (dB) attenuation between 0 and 63 can be provided to supply a selectively attenuated signal 31 at the output.

Attenuated signal 31 is supplied through a network terminating resistor R31 to signal buffer ci cuit including an operational amplifier A2 with negative feedback loop having a resistor R32. The buffered signal 32 is then supplied through a series of high-pass low-pass amplifier systems as shown where RC pairs R3(A-D); R4(A-D) and R6(A-D); C3(A-D, C4(A-D) and C6(A-D), A3, A4, A6, A5, R5 (A-B) C5(A-B) are provided along with operational amplifiers A3, A4, A6 each with a feedback loops respectively to define three high pass-low pass filter networks. The signal is supplied to a single low pass filter including an amplifier A5 and resistors R5(A-B) and capacitors C5 (A-B) in feedback loops provided so that overall an eight order low pass filter and a seventh order high pass filter is provided .

It has been found that by the use of only four operational amplifiers a multistage filter arrangement can be provided which would require the use of many more operational amplifiers in conventional practice.

Thus, a filtered attenuated audio signal J is provided from the filter network.

Figure 3A-3C also illustrates another feature of the present invention namely a clipping circuit operated by signal 225 from an LC filter 210 in the load output as shown in Figure 2 and 3C which operates the clipping circuit 220 to supply the signal 225 in direct response to the load. As shown in Figure 3C clipping circuit power is supplied from a power tap S4 where an input voltage, for example plus 150 volts is supplied from the output of a terminal of the power supply previously described. A voltage regulator RF3 is provided to supply an output signal 226 which is filtered by means of a RC filter R15-C15 to the base of a transistor Q221 which drives an opto isolator 0P220 in response to signal 221 from fi lter 210 where opto isolator 220 includes a transistor Q0P220 having its collector supplied by voltage source S4. The emitter 72 of opto isolator 0P220 is then supplied to an adjusting circuit including an op-amp A7 to operate as a DC bias eliminator to adjust the signal to keep the transistor of opto coupler 0P220 at "0" volts, while still passing audio in a linear manner.

The emitter 72 of the opto coupler 0P220 provides an adjusted AC signal 225 directly proportional to the current through the load L and in response to the signal 227 received from filter 210.

It has been found that the cost of the circuit of an equivalent type described above would be greatly in excess of the cost of the arrangment shown.

The signal 225 is directly proportional to the current through the load and is supplied through adjusting potentiometer P3 to op-amps A8, A9, of Figure 3A connected as a full wave rectifier to generate rectified signal 74 indicative of the loading which is supplied op -amp All which supplies a signal F which is indicative of loading on the unit.

A signal present indicator is also provided by means of amplifier A10 which gates transi stor Qll in the presence of a load signal to turn on light emitting diode LED 11.

The signal F from the output of the amplifier All is supplied to an amplifier A15 having an output AF to be supplied to the emitter of a transistor Q20.

A potentiometer P223 is provided to adjust a voltage reference VR 220 to adjust the operational amplifier All which determines the level at which the current to load L is to be clipped as described hereinafter where the signal 74, 75 is provided to one input of operational amplifier All connected as differential amplifier having its second input from voltage reference VR 220 for example a part NQ. LN317 adjusted by means of a potentiometer P223 to adjust the reference signal to adjust output F from the operational amplifier All. Potentiometer P223 sets the voltage clipping level and the signal F is supplied to an amplifier A13 to supply an inverted signal -F to an amplifier A14 and the signal F is supplied to amplifier A15. The op-amps A14 , A15 are operated in voltage bias mode across the audio signal J where the reference for the inverting amplifiers is supplied from audio signal J through resistors R71, R72 with clamping diodes D5-D8, provided as shown. The adjusted reference voltage -AF is supplied to adjust the signal J while the signal AF is supplied to the emitter of a transistor Q3 having its collector supplied from a voltage source S6 through a light emitting diode LED 2 and the transistor base operated by the audio signal J. Output signal -AF is then connected to the audio channel signal to provide signal which is the combined effect of the audio signal and reference signal F. If the combined signal is in excess of the voltage necessary to gate, the signal J is then increased to clip power as described hereinafter. Diodes D5, D7 block the reference signals F, -F from the audio signal unless the audio exceeds the value of F or -F then they ^• conduct the output of op-amps A15, A13 to clip^' the audio at the value of reference F or -F. The transistor Q20 is in series with diode D7 and is turned on any time D7 is conducting.

Under all normal operating conditions signal F is fixed at a setting which will clip the audio at a selected input level . If the maximum load current is exceeded the signal 74 will exceed this reference F and only then will it cause signal F to reduce and in turn reduce the input clipping level .

In the arrangement shown if the audio channel voltage exceeds J selected limits the appropriate diode clamps the audio channel voltage at the reference before it can exceed the permissible band and limits the load current as described hereinafter as shown in Figure 3B. The signal J is supplied to the inputs of op-amps A16 and A17 which supply inverted and balanced outputs K and L as inputs to op-amps A18, A19 connected as integrators. The integrators are clocked by means of a pair of exclusive "OR" gates ORl, OR so signals M and N are provided at the outputs. The input to the integrators A18, A19 is further modified by negative feedback 274, 276 from load L as shown in Figure 2.

The feedback loops for op-amps A18, A19 including resistors R48, R47 and capacitors C25, C27 assist in converting the audio signal to a pulse width modified signal shown in Figure 4. It has been found that the arrangment shown creates generally flat audio .response signals M, N to supply the input of comparator A20 to generate a signal "0".

The signal 0 is applied to "OR" gates 0R3, 0R4 where the second input of "OR" gate 0R3 is grounded and the second input of "OR" gates 0R4, 0R5 is from a voltage reference S8. The second input to "OR" gates -

0R5, 0R6 is from a clock CL110 which includes OR gates

0R7, or 0R8 driven by a clock with appropriate adjustment. The outputs from the "OR" gate, starting with "OR" gate 0R110 are as follows where "OR" means exclusive "OR" Gates:

ORGATE OUTPUT 0R6 Clock 0R5 .Not Clock 0R4 Not Data 0R3 Data

This arrangement of using exclusive "OR" gates to invert a signal provides an output signal that is the exact compliment of the inverted signal, without any time delay or phase shift between outputs, as there would be if an inverter were used.

Thus it can be seen that the outputs are sequenced directly with each other. Each of the outputs is connected to a corresponding Nand Gate N1-N4. A delay is built into the switching of ^'NAND Gate 1 and 4 by' means of the inherent capacitance of the gate and the use of resistors R85, R86 which define an RC time constant. Gates Nl through N5 are provided and the connection is as shown so, for example, the "OR" gate 0R6 is connected to NAND Gate N4 and N2 So, NAND Gate N4 is clocked by "OR" gate 0R6 and receives data from "OR" gate 0R4 while NAND Gate 2 receives its data from "OR" gate 0R3. Likewise NAND Gate N2 receives clock data from "OR" gate 0R6 and its data from "OR" gate 0R3. Inverting buffers B11-B14 are provided as shown to supply the outputs signals as shown to the bases of transistors Q13-Q20.

It can be developed that the output from the buffers B1-B4 drive the Mosfets Q13-Q20 which are paired to be connected to the primaries P2-P3 of transformers T4 and T5 so that the buffers, cycle on and off to the primary coils. That is the current from primary P2 is slightly delayed to prevent overlap with the signal from primary 1 which is operated by the outputs from buffers Bl, B2. Operation of the units is cycled in order to provide the push-pull characteristics necessary to operate secondaries S1-S4 of transformer T4-T5 provided to be operated by the primary P2, P3 as shown. Appropriate rectifiers circuits are F1-F4 associated with the secondaries S1-S4 to operate "OR" gates 0R9-0R12 and the outputs 161-164; 171-174; 181-184; and 191-194 to operate drive circuits DR1-DR4 on Figure 3C utilizing quad OR gates 0R13-0R24 as shown which in turn operate MOSFETS Q21-Q28 which, respectively operate MOSFETS Q29-Q32 where the MOSFETS (Q21, Q22), (Q23, Q24), (Q25, Q26) and (Q27,Q28) are tied together and the MOSFETS 29-Q32 are tied together as are MOSFETS Q30, Q31 to supply AC power to load L, through a filter 210 for example a notch filter as known in the art.

Figure 5, represents a simplified schematic of a portion of the arrangement shown in Figures 3B and 3C where the signal D which correspond to the signal 0 which is a data signal generated as previously described Clock signal CL corresponds to the same signal shown in Figure 3B. It is these signals which primarily control the operation of the output are uti lized to generate the necessary square wave arrangement .

In Figure 5 the data signal D is converted to D* which is the inverse of D and in the arrangement shown is generated by passing the D signal through an inverter II to generate an inverse signal D*. The signal D* is then supplied to one input of an "AND" Gate N5 represented schematically in Figure 5. The Clock input CL is supplied likewise through an inverter 12 to provide a CL* signal which- is the inverse ^'of the CL signal . The CL* signals is supplied to the other input of NAND Gate N5 and generates an output signal X. The clock signal is also supplied to a second NAND Gate N6 which is supplied with a signal from D* which has a built in delay DE but in Figure 5 is shown as being generated by the capacitor CA and resistor RA. It will be understood that the representation in Figure 5 is a schematic representation of the delay previously discussed and the value of the delay DE is determined by the value of the RC pair RA, CA. NAND Gate N6 generates an output W which is the compliment of the signal X and which is than supplied to a primary coil PA of a transformer which generally corresponds to the primary P2 of Figure 3. Likewise the signal D is supplied to one input of a NAND Gate N7 with the other input being supplied Clock signal CL to generate a output Y. Another NAND Gate N8 is shown having an input to receive CL* where the second input is supplied signal D. A second delay DE* which is equivalent to the DE delay in the signal D* supplied to NAND Gate N6 is provided by means of a resistor RB and a capacitor CB as previously described. The NAND Gate N8 generates an output Z which in general the compliment of signal Y except for the delay DE* and is supplied to a primary PB which is generally equivalent to the primary P3 of Figur.e 3B. The- output Y is similarly generated by the data and Clock signals so the primary PB is operated in response thereto. The secondaries AA and BB are operated through the driver circuits DA, and DB to the driver system which includes the transistors Q29-Q30 of Figure 3C are illustrated as QA, and QB in the illustration of Figure 5.

Figure 6A-6N indicate the signal patterns at the various designated positions within the device.

It will be noted that the delay signals DE and DE* are indicated on the D* plus delay signal in Figure 6E. The summation of the signals generating the balance of the signals are also illustrated. For example, when the D plus delay is added with the DL* signal the output is shown as output Z illustrated also in Figure 5 as the inverse of signal Y which powers the primary coil PB. The other phases are generated as:

X=D*+CL*

W=D*+DE and CL

Y=CL and D

Z=CL* and D "delay"

The results of these signals driving the two primary coils PA, PB is shown as signals SA and SB which are the symmetrical pulse width modulated signals with no direct curr^'ent component and capable of 0 to 100% modulation. The outputs SA and SB of the transformers are fed to the output system which acts as an exclusive "OR" Gate DA, and DB so the resulting drive signals are shown as EE-FF respectively in Figure 5 and in Figure 6L and 6M. The signals are identical to the D and D* signals except for the delays (DE) and DE* initiated. The delays represent the equivalent of a dead band in the output pulse width modulated signal and is fully adjustable by variation of the capacitance-resistance pairs as previously described to guarantee that both the output field effect transistors are not on at the same time. The secondary winding SA and SB of each of the units is fed to the outputs DA, DB for bridged output. This portion of the amplifier generates isolated 0 to 100 pulse width modulated signal to the output stage by means of a transformer.

Normally, pulse width modulation cannot be supplied through a transformer because of the direct current component carried and which is not passed by the transformer. The present invention overcomes this restriction because the data or 0 signal is actually the pulse width modulated signal to be supplied through the transformer and is inverted to the D* signal by means of exclusive "OR" Gate equivalent to prevent phase shift. The Clock signal CL is also inverted by means of an exclusive "OR" Gate arrangement to prevent phase shift. Since the same clock is used to generate the pulse width data signal it is 90° out of phase with the data with no input signal. Data is modulated with respect to the clock signal. The arrows in Figures 6A, 6B indicate the direction of movement in response to varying audio input signals. Also the D and D* signals are both delayed by the delay time DE and DE* which will alternately be equal to the dead band in the output drive signal so these signals are represented by the signal D* plus DE and D plus DE*.

It will be understood that the foregoing is but one arrangement within the scope of the present invention and that various other arrangements also within the scope of the present invention will occur to those skilled in the art upon reading the disclosure set forth hereinafter.

Claims

CLAIM

1. The audio amplifier system including attenuator means to receive an audio signal and selectively attenuate said signal; modulator means to convert said attenuated signal .to square wave signal having a pulse width as a function of the level of the audio signal; Push-pull converter means to receive said square wave signal and to generate alternating current signal means; Transformer means to receive said alternating current signal and provide amplified output signal in respbnse thereto to load means.

2. The invention of Claim 1 including clipper means to sense the amplified output signal to adust said input audio signal in response to selected values of said output signals.

3. The invention of Claim 1 including buffer means to receive said attenuated signal and selectively condition said signal and supply said signal to said modulator means.