WO1988000392A1 - Procede de fabrication de dispositifs dans des substrats semi-conducteurs iii-v et dispositifs ainsi formes - Google Patents

Procede de fabrication de dispositifs dans des substrats semi-conducteurs iii-v et dispositifs ainsi formes Download PDF

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Publication number
WO1988000392A1
WO1988000392A1 PCT/US1987/001520 US8701520W WO8800392A1 WO 1988000392 A1 WO1988000392 A1 WO 1988000392A1 US 8701520 W US8701520 W US 8701520W WO 8800392 A1 WO8800392 A1 WO 8800392A1
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region
nickel
substrate
electrical contact
gold
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PCT/US1987/001520
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English (en)
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Amiram Appelbaum
Murray Robbins
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American Telephone & Telegraph Company
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Publication of WO1988000392A1 publication Critical patent/WO1988000392A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds

Definitions

  • the invention pertains generally to a method for fabricating devices in III-V semiconductor substrates, as well as the resulting devices.
  • a III-V semiconductor material for purposes of this disclosure, is a semiconductor which includes
  • III-V semiconductor materials include semiconductor materials, such as silicon.
  • electronic and opto-electronic devices e.g., discrete transistors, lasers and integrated circuit devices, fabricated in the III-V semiconductor materials are capable of achieving much higher operating speeds than are the corresponding devices fabricated in, for example, silicon.
  • the I ⁇ -V semiconductor materials are direct bandgap materials, rather than indirect bandgap materials, as is the case with silicon. As is known, stimulated emission of light is only achievable in the former type of materials.
  • opto-electronic devices which depend, for their operation, on stimulated light emission, e.g., lasers, must be fabricated in direct bandgap materials.
  • direct bandgap materials exhibit much higher quantum efficiencies than indirect bandgap materials, and therefore the former materials are preferred for the fabrication of optical detector, opto-electronic devices, such as avalanche photodiode (APD) detectors.
  • APD avalanche photodiode
  • the various types of devices fabricated in ILT-V semiconductor substrates include a variety of device components, such as active regions (a region of semiconductor material in a light-emitting opto-electronic device from which most of the light is emitted), sources, drains, p-n junctions and heterojunctions.
  • Each such device also includes one or more metallic wires or metallic runners, generally fabricated from gold (Au), terminating in one or more non-rectifying, low specific contact resistance (LSCR) electrical contacts to the substrate, through which electrical signals are communicated to the device.
  • LSCR low specific contact resistance
  • the term non-rectifying, LSCR electrical contact denotes an electrical contact which permits electrical current flow in two opposed directions across the contact, and exhibits a specific contact resistance less than or equal to about 10 -4 ohm-cm 2 in both directions.
  • Such contacts to III-V semiconductor substrates are essential because the gold (per se) in the gold wires and gold runners yields a rectifying, rather than non-rectifying, electrical contact to ILT-V semiconductor materials.
  • a non-rectifying, LSCR electrical contact to a ILT-V semiconductor substrate is conventionally formed by depositing, e.g., e-beam evaporating, a region of material which includes gold and a p-type (e.g., zinc or beryllium) or n-type (e.g., tin or germanium) dopant (depending upon whether the underlying semiconductor material is of p-type or n-type conductivity) onto the substrate.
  • a native oxide (or oxides) of the semiconductor material tends to form on the surface of the substrate during the deposition procedure. Such native oxides are generally undesirable because their presence serves to increase specific contact resistance.
  • the surface of the substrate is typically cleaned to remove these oxides, it is generally acknowledged that complete removal of the oxides is impossible. However, the presence of these oxides does not, in this instance, preclude the formation of a LSCR electrical contact. That is, after deposition, the gold-and-dopant-containing region is alloyed at temperatures as high as about 450 degrees Centigrade (C) for periods of time equal to about 7 minutes. Significantly, it is believed that this alloying procedure serves to drive the dopant through the native oxide (or oxides) and into the substrate, and electrically activate the dopant, to produce an electrical contact having a low specific contact resistance.
  • C degrees Centigrade
  • the relatively high alloying temperatures also result in upward diffusion of the p- or n-type dopant to the surface of the electrical contact, where the dopant also tends to become oxidized to form an electrically insulating layer. Unless great care is taken to remove these insulating layers, the electrical contact will exhibit undesirably high series resistance.
  • the downward diffusion of gold into the substrate is also undesirable because the presence of gold in, for example, an active region constitutes a non- radiative recombination center, which serves to reduce the useful lifetime of ' light-emitting opto-electronic devices, such as lasers.
  • the downward diffusion of gold into a substrate containing a relatively shallow p-n junction is undesirable because the gold penetrates through, and thus short circuits, these relatively shallow p-n junctions.
  • the relatively high alloying temperatures employed in forming the gold electrical contacts are further disadvantageous because they sometimes lead to significant, differential thermal expansions of the materials covering the substrate, which in turn leads to high stress in the substrate. Such high stress is undesirable because it leads to bending of the substrate, which makes conventional lithographic processing very difficult, if not impossible. This high stress often also leads to cracking and/or peeling of material layers overlying the substrate.
  • the above contact-fabrication procedure is further disadvantageous because it requires that the relative amounts of gold and dopant be precisely controlled to achieve the eutectic composition. Otherwise, the gold may not melt during the alloying process and/or the alloying process may not produce a sufficient or desired interaction between the dopant and the substrate, leading to an undesirably high specific contact resistance.
  • Schottky barrier contact (a rectifying, metal-semiconductor contact) to InP and, moreover, that a relatively thin nickel phosphide layer is formed at the interface between the nickel and the InP. While no connection was made (in these investigations) between the existence of the nickel phosphide layer and the existence of the Schottky barrier contact, it has long been believed that a non- rectifying, LSCR contact between a metal, such as nickel, and a substrate of InP can only be achieved if the metal-InP interface is rich in indium. But the interfacial nickel phosphide layer found in the investigations was, presumably, the result of nickel reacting, i.e. combining, with the phosphorus in the InP substrate.
  • the invention embodies a method of fabricating a device in a body which includes Group III - Group V semiconductor material and involves the finding that simply depositing any one of a specific class of compounds onto a p- or n- type III-V semiconductor substrate, having a doping level equal to or greater than about 10 17 per cubic centimeter (cm -3 ), yields a non-rectifying, LSCR electrical contact to the substrate.
  • the members of this class of compounds are those having compositions which include at least one metal element and at least one of three specific Group V elements, i.e., phosphorus (P), arsenic (As) or antimony (Sb), and having bulk electrical resistivities equal to or less than about 250 micro-ohm-centimeters ( ⁇ -cm), and preferably equal to or less than about 100 ⁇ -cm.
  • Group V elements i.e., phosphorus (P), arsenic (As) or antimony (Sb)
  • the invention involves the finding that depositing nickel, or a nickel-containing material which is essentially free of gold and silver and does not include any of the above three Group V elements, onto a III-V semiconductor material, and then reacting the nickel, or nickel- containing material with the semiconductor material to produce a compound having a composition which includes nickel as well as at least one of the three Group V elements, also yields a non-rectifying, LSCR electrical contact.
  • these contacts are formed without the use of dopants and without the need for an alloying procedure. Moreover, these contacts are formed (through deposition or deposition followed by chemical reaction) without the use of ultra-high-vacuum conditions, and despite the (presumed) adsorption of contaminants and formation of native oxides of the semiconductor material.
  • a non-rectifying, LSCR electrical contact to a semiconductor substrate of, for example, InP is readily formed simply by depositing a region of nickel phosphide directly onto the substrate. Alternatively, a region of nickel is deposited onto the substrate and allowed to spontaneously react with substrate material to form a relatively thin, interfacial layer of nickel phosphide. Contrary to the conventional wisdom, the (presumably) In-depleted interface between the deposited nickel and the semiconductor substrate does not preclude formation of a non-rectifying, LSCR electrical contact.
  • the inventive LSCR electrical contacts are often subjected to relatively high temperatures during various device fabrication steps. Depending upon the particular compositions of the materials employed in the electrical contacts, these materials may (under the influence of the relatively high temperatures) undergo reactions with the substrate material. As a consequence, Group HI and/or Group V elements in the substrate may be freed to diffuse to the surface of the electrical contacts, where they may undergo oxidation to form electrically insulating layers.
  • compositions of the materials employed in the inventive LSCR electrical contacts are preferably chosen (in accordance with a two-step procedure, described below) to have heats of formation which preclude such reactions.
  • non-rectifying, LSCR electrical contacts having compositions which preclude reactions with the ILT-V semiconductor substrates, which are amorphous, and have thicknesses equal to or greater than about 20 nm are effective barriers to the diffusion of gold (from overlying gold regions, used to facilitate bonding of gold wires or runners) into underlying substrates.
  • light-emitting opto-electronic devices which include such contacts have significantly increased lifetimes.
  • LSCR electrical contacts to relatively shallow p-n junctions are now readily formed, without short-circuiting the p-n junctions.
  • FIGS. 1-6 depict the steps involved in fabricating a channel-substrate-buried-heterostructure indium phosphide laser, using the inventive device fabrication method.
  • the invention involves a method for fabricating devices in ILT-V semiconductor substrates, which is distinguished from previous such methods in that it includes a new technique for forming non-rectifying, LSCR electrical contacts to these substrates.
  • the invention also involves the devices, e.g., transistors, lasers, light-emitting diodes, photodetectors, integrated circuits and integrated optical devices, resulting from the inventive method.
  • the invention involves the finding that non-rectifying, LSCR electrical contacts to p- or n-type III-V semiconductor substrates, having doping levels equal to or greater than about 10 17 cm -3 , are readily formed, using either of two techniques.
  • an electrical contact is formed by first cleaning the substrate (using conventional degreasers and oxide strippers), and then simply depositing, e.g., DC magnetron sputtering, any one of a specific class of compounds onto the substrate.
  • the members of this class of compounds are those having compositions which include at least one metal element and at least one of three specific Group V elements, i.e., P, As or Sb, and having bulk resistivities equal to or less than about 250 ⁇ -cm, and preferably equal to or less than about 100 ⁇ -cm.
  • the compounds which meet these requirements are typically (although not exclusively) binary, ternary, or quatenary metallic compounds which include, for example, NLP, N' P, NiP, Ni ll In 4 P 2' N *1 ⁇ ' Ni ⁇ , NLAs, NigSb, Ni 2 Sb, and NiSb.
  • the compound deposition need not take place under ultra-high-vacuum conditions, and, if possible, even ordinary room atmospheric conditions are useful.
  • the resulting electrical contact is highly useful, i.e., exhibits a specific contact resistance equal to or less than about 10 -4 ohm-cm 2 to current flow in two opposed directions.
  • a non-rectifying, LSCR electrical contact to a III-V semiconductor substrate is formed by (cleaning the substrate and) depositing nickel, or a nickel-containing material which is essentially free of gold and silver and does not include any of the three Group V elements, onto the substrate. Then the deposited material is either induced to react (e.g., heat is supplied), or allowed to spontaneously react (i.e., no external stimulus, such as heat, is supplied), with the substrate to form a compound having a composition which includes both nickel as well as one (or more) of the three Group V elements.
  • heat heat
  • spontaneously react i.e., no external stimulus, such as heat
  • an electrical contact to a substrate of InP is formed by depositing, e.g., e-beam evaporating, a region of nickel directly onto the substrate, and then allowing the nickel to spontaneously react with the substrate (during and after the deposition procedure) to form a relatively thin, interfacial layer of nickel phosphide.
  • the thickness of this interfacial layer is typically several fractions of a nanometer.
  • the nickel-bearing InP-substrate should, for example, be heated, to react additional nickel with the substrate material.
  • a relatively thick layer of essentially pure Ni ⁇ P is readily formed by carrying out the heating process (at a temperature of, for example, 300 degrees C) in an atmosphere of forming gas, i.e., an atmosphere which includes about 15 percent (by volume) of H 2 and about 85 percent of N literature.
  • the nickel-containing electrical contacts formed by deposition and reaction are typically crystalline in nature.
  • the electrical contacts formed by deposition alone, are either crystalline or amorphous in nature, depending upon deposition conditions.
  • a material is amorphous if it either has no grains or, if grains are present, their dimensions are equal to or less than about 50 n .
  • a relatively low substrate-support temperature e.g., -100 degrees Centigrade
  • a relatively low sputtering voltage e.g., 280 volts
  • a substrate-support maintained at room temperature ( 23 degrees Centigrade) and/or a relatively high sputtering voltage (e.g., 300 volts) yields crystalline N P.
  • a relatively high sputtering voltage e.g. 300 volts
  • the inventive method for fabricating devices often involves relatively high temperature processing subsequent to the fabrication of a non-rectifying LSCR electrical contact (or contacts). Such high temperature processing may result in chemical reactions between the material of the electrical contact and the substrate material. As a consequence, some Group III and/or Group V elements in the substrate may be freed to diffuse to the surface of the electrical contact, where they may be oxidized to form electrically insulating layers. Such layers may lead to relatively high series resistance.
  • the composition of the material employed in the inventive electrical contact is chosen in accordance with a two-step procedure. In the first step, those compositions are identified which include P, As, or Sb (and nickel, if the contact is formed by deposition and reaction), have bulk resistivities less than or equal to about 250 ⁇ -cm, and have heats of formation per metal atom
  • compositions which meet this requirement are (by definition) thermodynamically more stable than the substrate composition. However, one or more of these compositions might still react (under the influence of the relatively high temperatures) with substrate material to form an even more stable composition. To avoid this possibility, these particular compositions are identified and weeded out.
  • the most stable composition i.e., the composition having the most negative heat of formation per metal atom
  • the magnitude (the absolute value) of the difference between the heat of formation per metal atom of each composition (identified in the first step) and the most stable composition is calculated. If, for any particular composition, this magnitude is less than the magnitude (absolute value) of the heat of formation per metal atom of the semiconductor composition, then (thermodynamically) this particular composition is precluded from reacting with the substrate to form a more stable composition. Alternatively, and regardless of this requirement, if a particular composition has a larger relative amount of the Group V element than the most stable composition, then this composition too is precluded from reacting with the substrate.
  • the first step implies that the potentially useful compositions include Ni ⁇ P 5 , N P » and N JP.
  • NigPg is the most stable of these compositions.
  • Applying the criterion of the second step implies that all of these compositions are thermodynamically stable, i.e., will not react with InP.
  • NiP is also useful (will not react with InP) because it contains a larger relative amount of P than igPg.
  • a region of gold (and, perhaps, other materials) is deposited onto the contact to facilitate the bonding of gold wires and/or gold runners to the electrical contact.
  • material regions which are thermodynamically stable, as defined by the above two-step procedure are amorphous, and have thicknesses equal to or greater than about 20 nanometers are effective barriers to undesirable interdiffusion of gold (from the overlying gold region) and the underlying semiconductor material. (Such interdiffusion is undesirable for the reasons given above, in relation to conventional gold electrical contacts.)
  • Such materials are useful both as diffusion barriers and as non-rectifying, LSCR electrical contacts.
  • such material regions are highly useful just as diffusion barriers interposed between any of a variety of electrical contacts and, for example, the corresponding, overlying gold regions.
  • the inventive technique for forming electrical contacts makes it possible to form a relatively shallow electrical contact to a relatively shallow p-n junction or a relatively shallow heteroj unction (a p-n junction or heteroj unction having a depth less than or equal to about 1/2 micrometer), without short-circuiting the p-n junction or heterojunction.
  • the depth of a p-n junction, or of a heterojunction is defined with reference to the device surface, or interface between different material regions of the device, on which the electrical contact is formed, or from, or through which, the electrical contact extends.
  • the depth of a p-n junction formed, for example, by producing a p-type region within an n- type substrate is defined as the length of a perpendicular extending from a least-squares-fit planar approximation to the above reference surface or reference material interface to the lowest point where the dopant concentration in the p-type region is equal to the dopant concentration in the n-type substrate.
  • the depth of a heterojunction formed by different semiconductor materials is defined as the length of a perpendicular extending from the above least-squares-fit planar approximation to the lowest point of the interface between the two materials, as determined using, for example, Auger electron spectroscopy.
  • the depth of a heterojunction formed by semiconductor materials having the same composition but different doping levels is as defined above, except that the perpendicular extends to the lowest point of the interface between the two materials where the doping level is the average of the doping levels in the two materials as determined, for example, by SLMS analysis.) That is, and as discussed above, the alloying procedure involved in forming a conventional gold contact typically results in gold being diffused downwardly into the semiconductor substrate. If the electrical contact is to a substrate region containing a p-n junction or heterojunction having a depth equal to or less than about 1/2 micrometer, then the gold invariably diffuses more than about 1/2 micrometer, i.e., the gold diffuses into, and through, the junction, short-circuiting the junction.
  • the inventive technique involves no alloying procedure.
  • the contact material is thermodynamically stable, amorphous, and has a thickness equal to or greater than about 20 nanometers, both gold and contact material are largely precluded from diffusing downwardly into the semiconductor substrate into electrical contact with the p-n junction or heterojunction.
  • Yet another advantage of the invention is the fact that it permits the useful lifetimes of light-emitting, discrete opto-electronic and integrated optical devices to be significantly increased. That is, by forming the material compositions with thicknesses equal to or greater than about 20 nanometers, the downward diffusion of gold into the active regions of such devices is largely precluded. As a consequence, the formation of non-radiative recombination centers is largely avoided.
  • the laser is formed in a substrate which initially includes just a bulk region 10 of, for example, n-type InP, e.g., a wafer of n-type InP.
  • the doping level within the bulk region 10 is, for example, about 8 x 10 17 cm '3 .
  • the first step in the fabrication of the laser is to form a blocking layer 30, i.e., a layer which blocks the flow of currents external to the active region (described below) into the bulk region 10, adjacent to the upper surface 20.
  • the blocking layer 30 is formed, for example, by diffusing a p-type dopant, such as cadmium, into the bulk region 10.
  • the doping level within the blocking layer should be equal to or greater than about 4 x 10 18 cm -3 to avoid the flow of undesirable leakage currents across the blocking layer and into the bulk region 10.
  • the thickness of the blocking layer 30 ranges from about 0.5 ⁇ m to about 1.5 ⁇ m. Thicknesses less than about 0.5 ⁇ m are undesirable because they too result in undesirable leakage currents across the blocking layer. Thicknesses greater than about 1.5 ⁇ m are undesirable because they result in lasers which require undesirably large amounts of electrical power to achieve stimulated light emission.
  • the blocking layer 30 is formed by depositing a layer of semi-insulating InP onto the surface 20, using conventional metal organic chemical vapor deposition techniques.
  • semi-insulating means that the deposited semiconductor material has a bulk resistivity equal to or greater than about 10 ohm-cm.
  • an etch mask 40 is formed on the upper surface of the blocking layer.
  • This etch mask includes, for example, a layer of silicon dioxide which is deposited onto the blocking layer 30 using conventional plasma deposition techniques.
  • the etch mask is formed by patterning the silicon dioxide layer using, for example, conventional lithographic techniques.
  • the thickness of the silicon dioxide layer ranges from 110 nm to about 130 nm. Thicknesses less than about 110 nm are undesirable because they result in an undesirably large number of pinholes in the silicon dioxide. On the other hand, thicknesses greater than about 130 nm are undesirable because they make it difficult to achieve the desired sidewall inclination of the V-groove, described below.
  • a crystallographic, chemical etchant e.g., 3:1 HC1:H 3 P0 4
  • This V-groove 50 serves to channel, and confine, the electrical current to the active region of the laser.
  • the etchant is chosen to expose (111) facets of the crystalline substrate.
  • the width of the V-groove ranges from about 3.5 micrometers ( ⁇ m) to about 4.5 ⁇ m. Widths less than about 3.5 ⁇ m, or greater than about 4.5 ⁇ m, are undesirable because they result in devices which require an undesirably large amount of electrical power to achieve stimulated emission of light.
  • an n-type InP buffer region 60 is grown in the bottom of the V-groove 50 (as well as on the surface of the blocking layer 30) using conventional liquid phase epitaxy (LPE) techniques.
  • LPE liquid phase epitaxy
  • An undoped, active region 70 of III-V semiconductor material is now grown on the buffer region 60 in the V-groove 50 (as well as on the upper surface of the blocking layer 30) using conventional LPE techniques.
  • the bandgap of the semiconductor material employed in the active region should be less than that of the semiconductor material employed both in the blocking layer 30 and in the cladding layer (discussed below).
  • One such useful (active region) material is, for example, (undoped) indium gallium arsenide phosphide (InGaAsP).
  • the thickness of the active region ranges from about 0.2 ⁇ m to about 0.7 ⁇ m.
  • Thicknesses less than about 0.2 ⁇ m are undesirable because such thin regions result in undesirably little stimulated light emission from the laser. Thicknesses greater than about 0.7 ⁇ m are undesirable because they result in lasers which require an undesirably large amount of electrical power to achieve stimulated emission of light.
  • the growth of the active region 70 is followed by the LPE-growth of a cladding layer 80 and of a cap layer 90.
  • the former is, for example, of p-type InP, while the latter is of p-type indium gallium arsenide (InGaAs).
  • the thickness of the cladding layer, and of the cap layer, is typically about 1 ⁇ m.
  • a (patterned) deposition mask 120 is now formed on the upper surface of the cap layer 90.
  • the deposition mask permits the electrical contact to the laser to be formed in vertical alignment with the active region 70.
  • the deposition mask 120 includes a layer 100 of silicon dioxide which is deposited onto the cap layer 90 using, for example, conventional plasma deposition techniques.
  • the deposition mask includes a layer 110 of, for example, photoresist.
  • the thickness of the silicon dioxide layer is typically about 0.3 ⁇ m, while the thickness of the photoresist is typically about 1 ⁇ m.
  • the photoresist is initially patterned, i.e., a region of the photoresist overlying the active region 70 is removed, using conventional exposure and development techniques.
  • the width of this region (and thus the ultimate width of the electrical contact) is typically about 6 ⁇ m.
  • the patterned photoresist layer is then used as an etch mask during the etching of the silicon dioxide layer 100, resulting in the removal of a region of the silicon dioxide layer which also overlies the active region 70.
  • Useful silicon dioxide-etchants include, for example, buffered HF.
  • An electrical contact to the laser is now produced by depositing, e.g., sputtering, an amorphous region 130 of, for example, N ⁇ ⁇ P-. onto the exposed upper surface of the cap layer 90.
  • the thickness of the region 130 is equal to a greater than about 20 nanometers, to avoid the downward diffusion of gold (from a gold region subsequently formed on the region 130).
  • a layer 140 of titanium is deposited onto the upper surface of the region 130 as well as onto the upper surface of the silicon dioxide layer 100.
  • the thickness of the titanium layer is typically about 5 nanometers.
  • a layer 150 of gold is deposited onto the upper surface of the titanium layer 140, to facilitate the subsequent bonding of a gold wire to the electrical contact.
  • the thickness of the gold layer is typically about 1 ⁇ m.
  • a second electrical contact is, of course, needed to apply voltages to the laser. This second contact is formed on the backside of the substrate by initially thinning the bulk region 10 (typically by about 75 ⁇ m) using conventional mechanical lapping, and then depositing successive layers 160 and 170 of, respectively, NigP,. and gold, onto the backside, as described above.
  • the bulk region 10, which is now an integral part of the laser, is typically a portion of a wafer which, at this point, is cleaved (using conventional techniques) to form the end mirror-facets of the laser device.
  • the laser device is separated from the wafer using saw cuts transverse to the mirror-facets.
  • the final steps in the fabrication of the laser typically involve soldering
  • the upper surface of the wafer was degreased, and a layer of SiOo, having a thickness of 500 nm, was plasma deposited onto the upper surface.
  • a layer of photoresist was spin-deposited onto the SiO ⁇ , and conventionally lithographically patterned to remove circular regions of photoresist having diameters ranging from about 20 ⁇ m to about 200 ⁇ m.
  • the silicon dioxide was chemically etched with buffered HF to expose corresponding circular surface areas of the indium phosphide.
  • N P having a thickness of about 100 nm
  • the gas within the sputtering chamber was argon, the pressure of the gas was 1.6 Pa (12 millitorr), and the DC voltage was 300 volts.
  • the NiJP-covered photoresist was then stripped from the wafer using conventional chemical etchants.
  • the conventional Cox and S track technique (see R. H. Cox and H. Strack, Solid State Electronics, Vol. 10, page 1213 (1967)) was employed to measure the specific contact resistance at each of the N P-covered regions of the wafer, using electrical currents of opposite polarity. In all cases, the specific contact resistance was equal to or less than about 3 x 10 -6 ohm-cm 2.
  • a 1.27 cm (one-half-inch) indium phosphide wafer was processed, as in Example 1, except that a different technique was used to form the circular regions of N P on the upper surface of the wafer. That is, after the photoresist and Si0 9 were patterned, a 100 nm-thick layer of Ni was e-beam evaporated onto the exposed, circular surface areas of the wafer, as well as onto the photoresist. After stripping the Ni-covered photoresist, the wafer was placed in an atmosphere of forming gas, and heated to a temperature of 300 degrees C for 30 minutes to produce circular regions of NioP, having thicknesses of about 130 nm, on the wafer.
  • Example 2 Using the technique employed in Example 1, the specific contact resistance, in all cases, was found to be equal to or less than about 3 x 10 "6 ohm-cm 2 .

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Abstract

Nouvelle technique de formation de contacts électriques non redresseurs sur des matériaux semi-conducteurs III-V, sans l'utilisation de dopants ou d'un processus d'alliage. Selon cette technique, un contact électrique est formé simplement en déposant une région de matière p.ex. 130 (sur le substrat semi-conducteur) ayant une composition qui comprend au moins un élément métallique et au moins l'un des trois éléments spécifiques du groupe V, c'est-à-dire P, As, ou Sb, et ayant une résistivité électrique brute égale ou inférieure à environ 250 mu)-cm. Dans une variante, un contact est formé en déposant du nickel, ou un matériau contenant du nickel sensiblement exempt d'or et d'argent, et ayant une composition qui ne comprend aucun des trois éléments du groupe V. On fait ensuite réagir le nickel, ou le matériau contenant du nickel, avec le substrat pour former une région, p.ex. 130, comprenant un composé ayant une composition qui contient du nickel ainsi que l'un des trois éléments du groupe V.
PCT/US1987/001520 1986-06-24 1987-06-22 Procede de fabrication de dispositifs dans des substrats semi-conducteurs iii-v et dispositifs ainsi formes WO1988000392A1 (fr)

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US87807786A 1986-06-24 1986-06-24
US878,077 1986-06-24

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WO1988000392A1 true WO1988000392A1 (fr) 1988-01-14

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PCT/US1987/001520 WO1988000392A1 (fr) 1986-06-24 1987-06-22 Procede de fabrication de dispositifs dans des substrats semi-conducteurs iii-v et dispositifs ainsi formes

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EP0442203A1 (fr) * 1990-02-12 1991-08-21 AT&T Corp. Méthode de réalisation de contacts ohmiques W-Sb à faible résistance, sur matériaux semiconducteurs III-IV
EP1039516A1 (fr) * 1999-03-25 2000-09-27 Sumitomo Electric Industries, Ltd. Electrode ohmique, méthode pour sa réalisation et dispositif semiconducteur
US6734091B2 (en) 2002-06-28 2004-05-11 Kopin Corporation Electrode for p-type gallium nitride-based semiconductors
US6881983B2 (en) 2002-02-25 2005-04-19 Kopin Corporation Efficient light emitting diodes and lasers
US6911079B2 (en) * 2002-04-19 2005-06-28 Kopin Corporation Method for reducing the resistivity of p-type II-VI and III-V semiconductors
US10833199B2 (en) 2016-11-18 2020-11-10 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
US10872964B2 (en) 2016-06-17 2020-12-22 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US10879366B2 (en) 2011-11-23 2020-12-29 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US10937880B2 (en) 2002-08-12 2021-03-02 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11043571B2 (en) 2002-08-12 2021-06-22 Acorn Semi, Llc Insulated gate field effect transistor having passivated schottky barriers to the channel

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FR3061354B1 (fr) * 2016-12-22 2021-06-11 Commissariat Energie Atomique Procede de realisation de composant comprenant des materiaux iii-v et des contacts compatibles de filiere silicium

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Materials Letters, Volume 3, No. 7,8, May 1985, Elsevier Science Publishers B.V., (Amsterdam, NL), S.R. SMITH et al.: "Stable Ohmic Contacts to n-GaAs using Ion-Beam Mixing", pages 294-298 see the whole document *

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0442203A1 (fr) * 1990-02-12 1991-08-21 AT&T Corp. Méthode de réalisation de contacts ohmiques W-Sb à faible résistance, sur matériaux semiconducteurs III-IV
EP1039516A1 (fr) * 1999-03-25 2000-09-27 Sumitomo Electric Industries, Ltd. Electrode ohmique, méthode pour sa réalisation et dispositif semiconducteur
US6365969B1 (en) 1999-03-25 2002-04-02 Sumitomo Electric Industries, Ltd. Ohmic electrode, method of manufacturing the same and semiconductor device
US6881983B2 (en) 2002-02-25 2005-04-19 Kopin Corporation Efficient light emitting diodes and lasers
US6911079B2 (en) * 2002-04-19 2005-06-28 Kopin Corporation Method for reducing the resistivity of p-type II-VI and III-V semiconductors
US6734091B2 (en) 2002-06-28 2004-05-11 Kopin Corporation Electrode for p-type gallium nitride-based semiconductors
US10950707B2 (en) 2002-08-12 2021-03-16 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11043571B2 (en) 2002-08-12 2021-06-22 Acorn Semi, Llc Insulated gate field effect transistor having passivated schottky barriers to the channel
US11355613B2 (en) 2002-08-12 2022-06-07 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US10937880B2 (en) 2002-08-12 2021-03-02 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11056569B2 (en) 2002-08-12 2021-07-06 Acorn Semi, Llc Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11018237B2 (en) 2002-08-12 2021-05-25 Acorn Semi, Llc Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11610974B2 (en) 2011-11-23 2023-03-21 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US10879366B2 (en) 2011-11-23 2020-12-29 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US11804533B2 (en) 2011-11-23 2023-10-31 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US10872964B2 (en) 2016-06-17 2020-12-22 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US11843040B2 (en) 2016-06-17 2023-12-12 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US10833199B2 (en) 2016-11-18 2020-11-10 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
US11462643B2 (en) 2016-11-18 2022-10-04 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
US12034078B2 (en) 2016-11-18 2024-07-09 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

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CA1310433C (fr) 1992-11-17
EP0272303A1 (fr) 1988-06-29
JPS63503583A (ja) 1988-12-22

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