WO1987000688A1 - Methods of producing layered structures - Google Patents

Methods of producing layered structures Download PDF

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Publication number
WO1987000688A1
WO1987000688A1 PCT/GB1986/000424 GB8600424W WO8700688A1 WO 1987000688 A1 WO1987000688 A1 WO 1987000688A1 GB 8600424 W GB8600424 W GB 8600424W WO 8700688 A1 WO8700688 A1 WO 8700688A1
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WO
WIPO (PCT)
Prior art keywords
layer
metallisation
pillar
metal
etching
Prior art date
Application number
PCT/GB1986/000424
Other languages
French (fr)
Inventor
Raymond Edward Oakley
Original Assignee
Plessey Overseas Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Overseas Limited filed Critical Plessey Overseas Limited
Publication of WO1987000688A1 publication Critical patent/WO1987000688A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Definitions

  • This invention relates to methods of producing layered structures for integrated circuits, and in particular, to horizontally layered structures which include a plurality of electrically interconnected 5 metallisation layers.
  • a previously proposed method of producing integrated circuits, and especially one micron feature size integrated circuits includes the formation of layered structures comprising various levels of metallisation 10 defining between them vias, that is, metal to metal connections.
  • a method of forming the interconnections between the layers of metal involves forming a pillar of metal (as described in our co-pending European Patent Application published under the number 0129389) where a 15 via is required and depositing layer of dielectric material around the pillar in order to insulate a subsequent metal layer from the underlying metal layer.
  • the aforementioned method which involves forming the pillar of metal includes the deposition of a barrier layer *20 on the underlying metal layer and a pillar layer of metal
  • the underlying metal layer, the barrier layer and the pillar layer are then etched in accordance with a first masking pattern.
  • the pillar layer is then etched in accordance with a second masking pattern in order to leave the pillars of metal which form the vias..
  • the purpose of the barrier layer is to prevent the plasma used to etch the pillar layer from affecting the underlying metal layer. This helps to ensure that the thickness of the underlying metal layer can be accurately defined.
  • a method of forming a layered structure comprises forming on a substrate a first layer of metallisation, depositing on the first layer of metallisation a pillar layer of an electrically conductive material which material is different from that of the first layer of metallisation, etching the first layer of metallisation and the pillar layer in accordance with a first masking pattern, etching the pillar layer with an etchant to which the first layer of metallisation is resistant in accordance with a second masking pattern, depositing a dielectric layer, etching the dielectric layer to expose the pillar layer, and forming a further layer of metallisation to contact the exposed pillar layer.
  • Layer structures formed in accordance with the present invention are advantageous in that electromigration resistance characteristics between layers of metallisation are improved and the structures are simpler to manufacture.
  • the first layer of metallisation may be aluminium and the pillar layer may be of a refractory metal such as tungsten.
  • Layered structures having several layers of metallisation may be fabricated by repeating the above method until the further layer of metallisation is the final metal layer in the required layer structure.
  • the further layer of metallisation may be etched to remove unwanted metal therefrom.
  • Figure 2 illustrates the structure of Figure 1 after etching in accordance with a first masking pattern
  • Figure 3 illustrates the structure of Figure 2 after the pillar layer of metal has been etched in accordance with a second masking pattern
  • Figure 4 illustrates the structure of Figure 3 after a layer of dielectric has been deposited and etched to expose the surface of the pillar layer of metal; and Figure 5 illustrates a further layer of metallisation after etching, deposited on the structure shown in Figure 4.
  • a first layer of metallisation 2 is deposited on a substrate 4, such as a silicon substrate.
  • a pillar layer of an electrically conductive material such as a metal 8 is then deposited on the first layer of metallisation 2 to give the structure shown in Figure 1.
  • the first layer of metallisation 2 is preferably a 1 micron thick layer of aluminium.
  • the aluminium may be pure aluminium or aluminium doped with silicon and/or copper.
  • the pillar layer of metal 8 is preferably of a metal having relatively high intrinsic electromigration resistance which can be selectively dry etched with respect to the first layer of metallisation 2.
  • the electrically conductive material may be a refractory metal such as tungsten or may be of gold or chromium. Alternatively, the electrically conductive material may be of a semiconductor material such as doped silicon.
  • Pillar layers formed by such methods are advantageous in that there is less risk of electromigration failure due to the relatively high electromigration resistance of such metals.
  • a first masking pattern is formed on the surface of the pillar layer of metal 8.
  • the first masking pattern delineates the interconnect pattern required in the first layer of metallisation 2 in the resulting layered structure.
  • the structure shown in Figure 1 is then etched by anisotropic plasma etching to produce the structure shown in Figure 2.
  • a plasma containing a chlorine species such as carbon tetrachloride may be used. It can be seen that the structure shown in Figure 2 does not contain any undercuts.
  • the pillar layer of metal 8 may be etched using a plasma employing a flourine species, for example carbon tetraflouride.
  • a polyimide may now be spun onto the surface of the pillar layer of metal 8 in order to achieve a planar surface. This stage of planarisation is not essential and may be omitted.
  • the metal pillars 10, shown in Figure 3, which form the vias in the final structure are now fabricated. This is achieved by depositing a second masking pattern on the structure shown in Figure 2. The second masking pattern delineates the areas of the pillar layer of metal 8 where the metal pillars 10 are required.
  • the masking pattern being any known photo-resist material will to some extent extend beyond the defined areas of the pillar layer of metal 8 but will not extend between adjacent metal tracks defined in the pillar layer of metal 8 after etching in accordance with the first masking pattern. This overlap in the masking pattern does not adversely affect the formation of the metal pillars 10 as each metal pillar 10 is defined in a portion of the pillar layer of metal 8 which underlies the masking pattern.
  • the pillar layer of metal 8 is plasma etched, with an etchant such as carbon tetrafluoride to which the first layer of metallisation 2 is resistant, in accordance with the second masking pattern. Since this etchant does not attack the first layer of metallisation 2, the pillar layer of metal 8 is etched down to the first layer of . metallisation 2 to produce the structure shown in Figure 3 with the metal pillars 10 extending from and accurately aligned to the metallisation pattern in the first layer of metallisation 2. The metal pillars 10 are accurately aligned as they are partly formed during the etch used to form the metallisation pattern in the first layer of metallisation 2.
  • an etchant such as carbon tetrafluoride to which the first layer of metallisation 2 is resistant
  • a dielectric layer 12 is now deposited over the structure shown in Figure 3 by, for example, successive spin coatings and cure operations.
  • the dielectric layer is deposited to a thickness sufficient to encase the structure of Figure 3 so that the pillars 10 are surrounded and covered by the material of the dielectric layer so as to provide a planar surface over the metal pillars 10.
  • the dielectric layer 12 is, preferably, formed from a polyimide material such as that sold under the trade name PIQ by Hitachi.
  • the dielectric layer is then plasma etched to expose the top surfaces of the metal pillars 10.
  • the dielectric layer 12 may be etched using a carbon tetrafluoride and oxygen plasma and suitable means may be included in the plasma chamber to ensure that the etch process is terminated as soon as the surfaces of the metal pillars 10 are exposed.
  • the resulting structure is shown in Figure 4 and the exposed surfaces of the metal pillars 10 are used to form the connections to the next metal layer.
  • the substrate 4 is not flat but has a surface topography having a variation in height by an amount comparable with the metal layer thicknesses. Consequently, some pillars 10 stand higher than others and the tops of these are exposed early in the etching of the dielectric layer 12 stage. By the time the tops of the lowest pillars 10 are exposed, the highest pillars protrude.
  • the etchant for the dielectric layer 12 is of flourine-oxygen chemistry
  • the etchant will also etch the pillars 10. If a suitable mixture of flourine and oxygen is used in the etchant, it is possible to etch the dielectric layer 12 and the pillars 10 at equal or nearly equal rates.
  • an etchant for the dielectric layer 12 which also etches the pillars 10, it is possible to provide and improved planar surface to the device at this stage.
  • a further metal layer 14 is then deposited on the structure shown in Figure 4.
  • the metal layer 14 will contact the surfaces of the pillars 10 exposed in the dielectric layer 12. It will now be seen that the metal pillars 10, consisting of the remaining portions of the second metal layer 8, form the metal to metal connections between the first metal layer 2 and the metal layer 14, that is, the pillars 10 form the vias between the metal layers 2 and 14. If only two level metallisation is required in the layered structure, the further metal layer 14 will be the final metal layer of the structure.
  • a further masking pattern may be formed on the metal layer 14 ⁇ id the metal layer 14 etched in accordance with this pattern to remove unwanted metal from the field regions of the metal layer 14. If more than two level metallisation is required a pillar layer of metal similar to the pillar layer of metal 8, may be deposited on the further metal layer 14. The sequence of operations can then be repeated until the desired multi-level metallisation structure is formed, the final metal layer being etched to remove unwanted metal in the field regions as described above the further metal layer 14 in connection with the two level metallisation structure. As the method of the present invention provides vias, in the form of the metal pillars 10, which are aligned accurately to the metallisation in the first metal layer 2, maximum via size in the minimum space available is achieved.
  • materials other than aluminium may be used for the metallisation layers.
  • electrically conductive materials other than tungsten may be used for the pillar layers, such as gold, chromium or a semiconductor material such as doped silicon.
  • materials other than polyimide can be used, such as silicon dioxide, silicon nitride, silicon oxynitride and other organic materials.
  • appropriate deposition and planarisation processes should be employed for the particular material used.
  • the method of forming layered structures may be applied, using an appropriate selection of materials, to gallium arsenide structures.

Abstract

A method of forming a layered structure comprises forming on a substrate (4) a first layer of metallisation (2) and depositing on the first layer of metallisation (2) a pillar layer (8) of an electrically conductive material but comprising of a different material to the first layer of metallisation (2). Then etching these two layers (2, 8) according to a first masking pattern. Further etching of the pillar layer (8) according to a second masking pattern but with an etchant to which the first layer of metallisation (2) is resistant. Deposition of a dielectric layer (12) and etching of said dielectric layer (12) to expose the pillar layer (8), and depositing a further layer of metallisation (14) to contact the exposed pillar layer (8).

Description

METHODS OF PRODUCING LAYERED STRUCTURES
This invention relates to methods of producing layered structures for integrated circuits, and in particular, to horizontally layered structures which include a plurality of electrically interconnected 5 metallisation layers.
A previously proposed method of producing integrated circuits, and especially one micron feature size integrated circuits, includes the formation of layered structures comprising various levels of metallisation 10 defining between them vias, that is, metal to metal connections. A method of forming the interconnections between the layers of metal involves forming a pillar of metal (as described in our co-pending European Patent Application published under the number 0129389) where a 15 via is required and depositing layer of dielectric material around the pillar in order to insulate a subsequent metal layer from the underlying metal layer.
The aforementioned method which involves forming the pillar of metal includes the deposition of a barrier layer *20 on the underlying metal layer and a pillar layer of metal
* -* on the barrier layer. The underlying metal layer, the barrier layer and the pillar layer are then etched in accordance with a first masking pattern. The pillar layer is then etched in accordance with a second masking pattern in order to leave the pillars of metal which form the vias.. The purpose of the barrier layer is to prevent the plasma used to etch the pillar layer from affecting the underlying metal layer. This helps to ensure that the thickness of the underlying metal layer can be accurately defined.
However, horizontally layered structures which include pillars formed using such barrier layers are disadvantageous in that they exhibit relatively poor electromigration resistance characteristics between layers of metallisation. Further, the use of such a barrier layer is disadvantageous in that it makes the aforementioned method complex. It is an aim of the present invention to eliminate
•the need to use a barrier layer thereby improving the electromigration resistance characteristics between the metallisation layers of the structure.
According to the present invention there is provided a method of forming a layered structure, which method comprises forming on a substrate a first layer of metallisation, depositing on the first layer of metallisation a pillar layer of an electrically conductive material which material is different from that of the first layer of metallisation, etching the first layer of metallisation and the pillar layer in accordance with a first masking pattern, etching the pillar layer with an etchant to which the first layer of metallisation is resistant in accordance with a second masking pattern, depositing a dielectric layer, etching the dielectric layer to expose the pillar layer, and forming a further layer of metallisation to contact the exposed pillar layer.
Layer structures formed in accordance with the present invention are advantageous in that electromigration resistance characteristics between layers of metallisation are improved and the structures are simpler to manufacture.
The first layer of metallisation may be aluminium and the pillar layer may be of a refractory metal such as tungsten.
Layered structures having several layers of metallisation may be fabricated by repeating the above method until the further layer of metallisation is the final metal layer in the required layer structure. The further layer of metallisation may be etched to remove unwanted metal therefrom.
The invention will now be further described by way of example with reference to the accompanying drawings, in which:- Figure 1 illustrates a structure having a pillar layer of metal deposited on a first layer of metallisation;
Figure 2 illustrates the structure of Figure 1 after etching in accordance with a first masking pattern;
Figure 3 illustrates the structure of Figure 2 after the pillar layer of metal has been etched in accordance with a second masking pattern;
Figure 4 illustrates the structure of Figure 3 after a layer of dielectric has been deposited and etched to expose the surface of the pillar layer of metal; and Figure 5 illustrates a further layer of metallisation after etching, deposited on the structure shown in Figure 4.
Referring to the drawings, a first layer of metallisation 2 is deposited on a substrate 4, such as a silicon substrate. A pillar layer of an electrically conductive material such as a metal 8 is then deposited on the first layer of metallisation 2 to give the structure shown in Figure 1. The first layer of metallisation 2 is preferably a 1 micron thick layer of aluminium. The aluminium may be pure aluminium or aluminium doped with silicon and/or copper. The pillar layer of metal 8 is preferably of a metal having relatively high intrinsic electromigration resistance which can be selectively dry etched with respect to the first layer of metallisation 2. The electrically conductive material may be a refractory metal such as tungsten or may be of gold or chromium. Alternatively, the electrically conductive material may be of a semiconductor material such as doped silicon.
Pillar layers formed by such methods are advantageous in that there is less risk of electromigration failure due to the relatively high electromigration resistance of such metals.
A first masking pattern, not shown, is formed on the surface of the pillar layer of metal 8. The first masking pattern delineates the interconnect pattern required in the first layer of metallisation 2 in the resulting layered structure. The structure shown in Figure 1 is then etched by anisotropic plasma etching to produce the structure shown in Figure 2. For example when the metallisation 2 comprises aluminium a plasma containing a chlorine species such as carbon tetrachloride may be used. It can be seen that the structure shown in Figure 2 does not contain any undercuts.
The pillar layer of metal 8 may be etched using a plasma employing a flourine species, for example carbon tetraflouride. A polyimide may now be spun onto the surface of the pillar layer of metal 8 in order to achieve a planar surface. This stage of planarisation is not essential and may be omitted. The metal pillars 10, shown in Figure 3, which form the vias in the final structure are now fabricated. This is achieved by depositing a second masking pattern on the structure shown in Figure 2. The second masking pattern delineates the areas of the pillar layer of metal 8 where the metal pillars 10 are required. The masking pattern, being any known photo-resist material will to some extent extend beyond the defined areas of the pillar layer of metal 8 but will not extend between adjacent metal tracks defined in the pillar layer of metal 8 after etching in accordance with the first masking pattern. This overlap in the masking pattern does not adversely affect the formation of the metal pillars 10 as each metal pillar 10 is defined in a portion of the pillar layer of metal 8 which underlies the masking pattern.
The pillar layer of metal 8 is plasma etched, with an etchant such as carbon tetrafluoride to which the first layer of metallisation 2 is resistant, in accordance with the second masking pattern. Since this etchant does not attack the first layer of metallisation 2, the pillar layer of metal 8 is etched down to the first layer of . metallisation 2 to produce the structure shown in Figure 3 with the metal pillars 10 extending from and accurately aligned to the metallisation pattern in the first layer of metallisation 2. The metal pillars 10 are accurately aligned as they are partly formed during the etch used to form the metallisation pattern in the first layer of metallisation 2.
A dielectric layer 12 is now deposited over the structure shown in Figure 3 by, for example, successive spin coatings and cure operations. The dielectric layer is deposited to a thickness sufficient to encase the structure of Figure 3 so that the pillars 10 are surrounded and covered by the material of the dielectric layer so as to provide a planar surface over the metal pillars 10. The dielectric layer 12 is, preferably, formed from a polyimide material such as that sold under the trade name PIQ by Hitachi.
The dielectric layer is then plasma etched to expose the top surfaces of the metal pillars 10. The dielectric layer 12 may be etched using a carbon tetrafluoride and oxygen plasma and suitable means may be included in the plasma chamber to ensure that the etch process is terminated as soon as the surfaces of the metal pillars 10 are exposed. The resulting structure is shown in Figure 4 and the exposed surfaces of the metal pillars 10 are used to form the connections to the next metal layer.
In practice, the substrate 4 is not flat but has a surface topography having a variation in height by an amount comparable with the metal layer thicknesses. Consequently, some pillars 10 stand higher than others and the tops of these are exposed early in the etching of the dielectric layer 12 stage. By the time the tops of the lowest pillars 10 are exposed, the highest pillars protrude. In the case where the etchant for the dielectric layer 12 is of flourine-oxygen chemistry, the etchant will also etch the pillars 10. If a suitable mixture of flourine and oxygen is used in the etchant, it is possible to etch the dielectric layer 12 and the pillars 10 at equal or nearly equal rates. Hence, by using an etchant for the dielectric layer 12 which also etches the pillars 10, it is possible to provide and improved planar surface to the device at this stage.
A further metal layer 14 is then deposited on the structure shown in Figure 4. The metal layer 14 will contact the surfaces of the pillars 10 exposed in the dielectric layer 12. It will now be seen that the metal pillars 10, consisting of the remaining portions of the second metal layer 8, form the metal to metal connections between the first metal layer 2 and the metal layer 14, that is, the pillars 10 form the vias between the metal layers 2 and 14. If only two level metallisation is required in the layered structure, the further metal layer 14 will be the final metal layer of the structure.
A further masking pattern may be formed on the metal layer 14 βid the metal layer 14 etched in accordance with this pattern to remove unwanted metal from the field regions of the metal layer 14. If more than two level metallisation is required a pillar layer of metal similar to the pillar layer of metal 8, may be deposited on the further metal layer 14. The sequence of operations can then be repeated until the desired multi-level metallisation structure is formed, the final metal layer being etched to remove unwanted metal in the field regions as described above the further metal layer 14 in connection with the two level metallisation structure. As the method of the present invention provides vias, in the form of the metal pillars 10, which are aligned accurately to the metallisation in the first metal layer 2, maximum via size in the minimum space available is achieved. It is to be appreciated that the embodiment of the present invention described above with reference to the accompanying drawings has been given by way of example only and that modifications can be effected. Thus, for example, materials other than aluminium may be used for the metallisation layers. Also, electrically conductive materials other than tungsten may be used for the pillar layers, such as gold, chromium or a semiconductor material such as doped silicon. For the dielectric layer 12, materials other than polyimide can be used, such as silicon dioxide, silicon nitride, silicon oxynitride and other organic materials. However, appropriate deposition and planarisation processes should be employed for the particular material used.
Further, the method of forming layered structures may be applied, using an appropriate selection of materials, to gallium arsenide structures.

Claims

CLAIMS t
1. A method of forming a layered structure, which method comprises forming on a substrate a first layer of metallisation, depositing on the first layer of metallisation a pillar layer of an electrically conductive material which material is different from that of the first layer of metallisation, etching the first layer of metallisation and the pillar layerx in accordance with a first masking pattern, etching the pillar layer with an etchant to which the first layer of metallisation is resistant in accordance with a second masking pattern, depositing a dielectric layer, etching the dielectric layer to expose the pillar layer, and forming a further layer of metallisation to contact the exposed pillar layer.
2. A method according to claim 1, wherein the first layer of metallisation comprises aluminium.
3. A method according to claim 2, wherein the first layer of metallisation comprises aluminium doped with silicon or copper.
4. A method according to any one of claims 1 to 3, wherein the pillar layer comprises a refractory metal.
5. A method according to claim 4, wherein the refractory metal comprises tungsten.
6. A method according to claim 4, wherein the refractory metal comprises gold.
7. A method according to claim 4, wherein the refractory metal comprises chromium.
8. A method according to any one of claims 1 to 3, wherein the pillar layer comprises a semiconductor material.
9. A method according to claim 8, wherein the pillar layer comprises doped silicon.
10. A method according to any one of the preceding claims, wherein the dielectric layer comprises polymide.
11. A method according to any one of the preceding claims wherein the first layer of metallisation and the pillar layer are etched by an anisotropic plasma etchant containing a chlorine species.
12. A method according to any one of claims 1 to 10 wherein the etchant for etching the pillar layer, to which the first layer of metallisation is resistant, comprises a plasma containing a fluorine species.
13. A method according to any one of the preceding claims used, wherein the etchant used for etching the dielectric layer to expose the pillar layer, etches the said dielectric layer and said pillar layer at substantially equal rates.
14. A method according to claim 14, wherein the said etchant comprises a fluorine-oxygen compound.
15. A method according to any one of the preceding claims, comprising selectively repeating the method until the further layer of metallisation comprises the final metallisation layer of the structure.
PCT/GB1986/000424 1985-07-19 1986-07-18 Methods of producing layered structures WO1987000688A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8518231 1985-07-19
GB858518231A GB8518231D0 (en) 1985-07-19 1985-07-19 Producing layered structures

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WO1987000688A1 true WO1987000688A1 (en) 1987-01-29

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JP (1) JPS63500346A (en)
GB (2) GB8518231D0 (en)
WO (1) WO1987000688A1 (en)

Cited By (3)

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Publication number Priority date Publication date Assignee Title
EP0289089A1 (en) * 1987-05-01 1988-11-02 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device having interconnections located both above a semiconductor region and above an isolation region adjoining it
EP0834915A1 (en) * 1996-09-27 1998-04-08 NEC Corporation Fabrication method of multi-layered wiring
GB2330453A (en) * 1997-10-14 1999-04-21 Mitsubishi Electric Corp Semiconductor device having wiring layers integrally formed with an interlayer conection plug, and method of manufacturing the same

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Publication number Priority date Publication date Assignee Title
JPH08111460A (en) * 1994-08-16 1996-04-30 Nec Corp Structure of multilayer wiring and fabrication thereof

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US4077854A (en) * 1972-10-02 1978-03-07 The Bendix Corporation Method of manufacture of solderable thin film microcircuit with stabilized resistive films
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EP0129389A2 (en) * 1983-06-16 1984-12-27 Plessey Overseas Limited A method of producing a layered structure
EP0134571A1 (en) * 1983-09-02 1985-03-20 Siemens Aktiengesellschaft Integrated semiconductor circuit having an aluminium or aluminium alloy multilayer wiring, and method for its manufacture
EP0175604A2 (en) * 1984-08-23 1986-03-26 Fairchild Semiconductor Corporation A process for forming vias on integrated circuits

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US4077854A (en) * 1972-10-02 1978-03-07 The Bendix Corporation Method of manufacture of solderable thin film microcircuit with stabilized resistive films
JPS56130947A (en) * 1980-03-17 1981-10-14 Fujitsu Ltd Manufacture of semiconductor device
EP0129389A2 (en) * 1983-06-16 1984-12-27 Plessey Overseas Limited A method of producing a layered structure
EP0134571A1 (en) * 1983-09-02 1985-03-20 Siemens Aktiengesellschaft Integrated semiconductor circuit having an aluminium or aluminium alloy multilayer wiring, and method for its manufacture
EP0175604A2 (en) * 1984-08-23 1986-03-26 Fairchild Semiconductor Corporation A process for forming vias on integrated circuits

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IBM Technical Disclosure Bulletin, Volume 19, No. 9, February 1977, (Armonk, N.Y., US), METZGER et al.: "Forming Planar Integrated Circuit Metallization", see pages 3364-3365 *
PATENTS ABSTRACTS OF JAPAN, Volume 6, No. 9 (E-90) (887), 20 January 1982, & JP, A, 56130947 (Fujitsu) see the Abstract *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0289089A1 (en) * 1987-05-01 1988-11-02 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device having interconnections located both above a semiconductor region and above an isolation region adjoining it
EP0834915A1 (en) * 1996-09-27 1998-04-08 NEC Corporation Fabrication method of multi-layered wiring
GB2330453A (en) * 1997-10-14 1999-04-21 Mitsubishi Electric Corp Semiconductor device having wiring layers integrally formed with an interlayer conection plug, and method of manufacturing the same
GB2330453B (en) * 1997-10-14 1999-09-22 Mitsubishi Electric Corp Semiconductor device having wiring layers integrally formed with an interlayer connection plug and method of manufacturing the same

Also Published As

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JPS63500346A (en) 1988-02-04
EP0231242A1 (en) 1987-08-12
GB2178896A (en) 1987-02-18
GB8518231D0 (en) 1985-08-29
GB2178896B (en) 1988-11-09
GB8617654D0 (en) 1986-08-28

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