WO1987000660A1

WO1987000660A1 - Graphics system for display of shaded polygons

Info

Publication number: WO1987000660A1
Application number: PCT/GB1986/000421
Authority: WO
Inventors: Richard Westmore
Original assignee: Anamartic Limited
Priority date: 1985-07-18
Filing date: 1986-07-18
Publication date: 1987-01-29
Also published as: GB8518129D0; GB2178277A; GB2178277B; EP0230446A1

Abstract

Sets of parameters defining cusps of polygons and corresponding incremental quantities which define the shading of the polygons are stored in a polygon frame buffer. Real time scanline processing is utilised to provide the set of parameter signals from each set of parameters. Each set of parameter signals marks the beginning and end of the part of the scanline crossing the polygon and includes a first signal defining an initial colour and a second signal defining an incremental colour quantity. A plurality of pixel processing units (20) operate on respective ones of the sets of parameter signals. Each unit (20) comprises an interpolator (32) operating on the parameter signal data unit (31) to increment the colour signals at pixel rate or a submultiple CLK/4. The outputs RGB are pipelined and applied to a pixel insertion unit (33) in which pipelined insertion onto a colour bus (22) is effected, subject to control of a priority resolution unit (34) which compares a PRIORITY number included in the parameter signals with a priority number passed from unit to unit on a priority bus (23), the higher priority number being passed on to this bus by the priority resolution (34). The interpolator (32) and priority resolution unit (34) operate during the presence of a signal ACTIVE marking the part of the scanline crossing the polygon.

Description

GRAPHICS SYSTEM FOR DISPLAY OF SHADED POLYGONS

The present invention relates to a graphics system for realtime display of shaded polygons. It is well known that highresolution real time graphics displays (catering say for 1000 x 1000 or even 2000 x 2000 pixels), each with say 24 bits of colour information) make impossible demands if implemented using a multiplane bit-plane frame buffer. It is accordingly known to use what will be called polygon frame buffers which store sets of parameters defining polygons in image space and to employ real-time scan conversion to generate pixel rate signals from the sets of parameters. Examples of such systems are described in:

"Zone Management Processor: A module for generating surfaces in raster-scan colour displays" R L Grimsdale, A A Hadjiaslanis and P J Willis, Computers and Digital Techniques, Feb 1979, Vol 2, No 1, pp 21-25, and

"Computer Generation of Images for Flight Simulators" R L Grimsdale, Y C Lok, S M Price, R Westmore and D J Woolens, IEE International Conference on Simulators, Brighton, England 1983.

The systems described in these references produce uniform colour polygons. It is known that picture quality can be enhanced by shading and it is possible to implement bi-linear shading in real time. The most well-known form of bi-linear shading is Gouraud shading which is described in Chapter 25 of "Principles of Interactive Computer Graphics" W M Newman and R F Sproull, 2nd Ed, McGraw Hill. Use of Gouraud shading in a scan converter is described in:

"A VLSI - Oriented Architecture for Real-Time Raster Display of Shaded Polygons" D Fussel, and B D Rathi, Proceedings of Graphics Interface 82, 1982, pp 373-380, (hereinafter referred to as Fussel).

Fussel explains the benefits of restricting the system to triangles (in object space), including the fact that Gouraud shading produces no anomolies with triangles. Bi-linear shading of polygons with more than three sides is not invariant under rotation. This same restriction is preferably accepted in the present invention although it is not a mandatory restriction. In Fussel the sets of parameters in the polygon frame buffers are restricted to triangles in image space. Each such triangle is processed by a triangle processor which has to perform parallel arithmetic operations at pixel rate which is of the order of MHz. Each processor provides, for each pixel, the colour information plus a Z-coordinate which indicates the distance of the surface from the viewer. Selection is effected down through a tree of comparators to provide as the output pixel the colour information which pertains to the surface closest to the viewer.

It is difficult and expensive to perform the required parallel arithmetic operations at pixel rate and the object of the present invention is to provide a system which can more readily operate at a very hign speed.

According to the present invention there is provided a graphics system for display of shaded polygons, comprising a polygon frame buffer, means for computing and storing in the polygon frame buffer sets of parameters defining cusps of polygons and corresponding incremental quantities which define the shading of the polygons, scanline processing means operative in real time synchronously with respect to a raster-scan display to provide from each set of parameters, a set of parameter signals including signals marking the beginning and end of the part of each scanline crossing a polygon and first and second plural-bit signals defining an initial colour for the said part of the scanline and an incremental colour quantity, a plurality of pixel processing units operative on respective ones of the sets of parameter signals, a colour bus comprising at least one colour line, and a source of clock pulses, each pixel processing unit being responsive to the set of parameter signals supplied thereto and to the clock pulses to perform bitserial incrementing, at a bit rate established by the clock pulses, of the said first signal in accordance with the said second signal, and to reiterate such incrementing over an interval determined by the signals marking the beginning and end of the part of a scanline crossing a polygon, thereby to provide a plurality of bits for the colour bus in respect of each pixel or small group of pixels. The colour bus caters for a number M of colours. This number may be one for a monochrome display but is preferably three for a full colour display. Each colour is assigned a plurality N of bits, e.g. 8 bits for a high colour-resolution display, and these bits have to be generated for every pixel, or small group of pixels.

Particularly if the pixel resolution is high, it may not be necessary to recalculate the colours every pixel, although determination of beginnings and endings of scanlines and pixel insertion are always effected on a per pixel basis. Recalcualtion may suffice once for every small group of pixels such as every four pixels, as in the embodiment described below. Moreover, the scanline processing means may not operate fully on every scanline.

The first and second plural-bit signals may be recalculated only every few scanlines, e.g. every third scanline.

In one implementation of the invention the colour bus has only M lines (one per colour) and a very high clock rate of N x PXCLK is used where PXCLK is a pixel-rate clock. Each pixel processing unit can then be based on one one-bit adder which processes colour quantity and incremental colour quantity bit serially to provide N bits serially on the corresponding colour bus line which carries packets of N serial bits. This approach may be appropriate in a wafer-scale implementation where high clock rates are feasible and it is desirable to minimise the number of bus lines routed all over the wafer.

At the other extreme, the clock rate may be equal to pixel rate. The colour bus then has to have N lines per colour and each pixel processing unit will require N pipelined one-bit adders as in the embodiment described in detail below. This approach is preferred, at least for a printed circuit implementation, as it minimizes the bit-rate within the pixel processing units.

There are various intermediate approaches. For example consider one colour with N = 8. Each pixel processing unit could consist of two pipelined sub-units clocked at 4 x PXCLK to handle the four least significant and four most significant bits respectively or could consist of four pipelined sub-units clocked at 2 x PXCLK to handle pairs of bits. Pipelining is required to take account of carries.

Regardless of the implementation, the bits on the colour bus will require some alignment operations before they are finally decoded to provide analogue signals for driving a CRT or other raster scan display. If the clock rate is N x PXCLK, the packets of bits may be clocked serially into a shift register at clock rate and be transferred out in parallel at pixel rate. If the clock rate equals PXCLK, the bits are already in parallel on the colour bus bit with a 1-bit skew from line to line. The skew is readily removed by a digital delay of N-1 bits in the least significant bit line, a delay of N-2 bits in the next bit line, and so on, where a 1-bit delay is a G-pixel delay. In any intermediate scheme a combination of shift register and delay techniques will yield non-skewed, parallel bits.

The outputs of the pixel processing units may go direct on to the colour bits if there is no requirement for hidden surface removal or overlaying. Such a requirement is, however, more or less universal and some form of priority arbitration scheme establishing control over pixel insertion is required. A preferred scheme which cooperates with the pipelined pixel processing units is described below but other schemes may be employed, e.g. that of Fussel.

The invention will be described in more detail by way of example, with reference to the accompanying drawings, in which:

Fig 1 is a block diagram of a system embodying the invention,

Fig 2 is a block diagram of one pixel rate unit of Fig 1,

Fig 3 is a diagram illustrating pipelined processing within the pixel rate unit of Fig 2,

Fig 4 is a more detailed block diagram of a contour control circuit included in Fig 2,

Fig 5 is a more detailed block diagram of a priority resolution unit included in Fig 2,

Fig 6 is a diagram illustrating the general organization of an RGB interpolator included in Fig 2,

Fig 7 is a block diagram of one element of the RGB interpolator,

Fig 8 is a timing diagram explaining operation of the RGB interpolator,

Fig 9 shows a detail of the RGB interpolator, and

Fig 10 is a more detailed block diagram of the pixel insertion unit of Fig 2. The system illustrated in Fig 1 comprises a host computer 10 which is programmed in a high-level language and controls a plurality of object processors 11, 12 via a communications channel

13. For simplicity only two object processors are shown; there may be very many more. The processor 11 comprises a communications section 14, a configuration section 15, a picture rate process section 16 and a single polygon-processing section 17. The communication and configuration sections are used in a way well known in distributed computing systems in general to accept addressed commands from the host 10, and to establish a configuration required for a given application.

The polygon-processing section 17 operates on a single clipped triangle in image space. The system is restricted to handling triangles for reasons explained above. The worst case clipping of a triangle inside a rectangular window produces a seven-sided polygon. The picture rate process 16 performs all the calculations necessary to produce an image plane description of the clipped triangle from its object space description. The clipping is performed in such a way that the shading over its surface is consistent with that which would have been produced over the surface if the clipping had not been performed.

The object plane description of the polygon (triangle) consists of six parameters for each cusp: x, y, z, red, green, blue, i.e. three coordinates and three colour values. After transformation to image space and clipping, the image plane description consists of a left side cusp list, a right side cusp list and a surface priority value, explained below. Each cusp in the cusp lists is defined by three parameters: (1) x, y

(2) red, green, blue

(3) d(x)/dy

(4) d(red)/dy, d(green)/dy, d(blue)/dy.

(1) gives the cusp position in screen coordinates, (2) gives the colour at the cusp, (3) gives the gradient of the edge extending from the cusp and (4) specifies the shading.

The polygon-processing section 17 comprises a polygon frame buffer 18, a scanline process section 19 and a pixel rate processing unit 19. The image plane description which is written once per frame into the buffer 18 consists of the cusp lists explained above plus the priority value.

A fixed priority value (unsigned binary number) is used for each surface. This together with a back face cull is sufficient to determine whether or not a polygon is in front of other surfaces. A fixed priority scheme imposes two important restrictions on the system. These are that the polygons cannot intersect, and that they must be single sided. These restrictions are accepted because the cost of varying the priority value over the surface of the polygon using bi-linear interpolation is disproportionately high. The problem arises because priority resolution is performed in a bitwise manner from the most significant bit to the least significant bit (see below), whereas, the additions required to perform the interpolation are performed in a bit-wise manner from the leastsignificant bit to the most-significant bit. If there are N-bits in the priority word then N*(N-1) delay elements would be required to align the output of a priority interpolator with the input to the priority resolver.

As so far described, the system merely represents the application of well-known techniques (see for example the aforementioned book by Newman and Sproull) and no more detailed description will be given. The invention is not concerned with the way in which the image space polygon description is generated but with the way in which it is utilized by the polygon-processing section 17. The object processor 11 presumes that the host processor has carried the analysis down to the level of object space triangles. The object processor 12 illustrates another possible approach. The host processor 10 specifies n-gons (or n-hedra) and the picture rate process 16 performs the analysis into n clipped image space triangles processed by n (illustrated as n = 3) polygonprocessing sections 17.

Turning now to the construction and operation of these sections 17, the scanline process 19 operates on the cusp lists in the buffer 18 to generate, in each scanline, the following parameters:

X LEFT = X ON, defining the start of the active part of the scanline, i.e. the part crossing the polygon.

(X LEFT - X RIGHT) = X EXTENT, defining the length of the active part of the scanline,

PRIORITY, i.e. the surface priority which essentially gives the surface a fixed z-coordinate.

RED LEFT = RED

GREEN LEFT = GREEN

BLUE LEFT = BLUE, together defining the colour at the start of the active part of the scanline, d(RED)/dx = RED DX d(GREEN)/dx = GREEN DX d(BLUE)/dx = BLUE DX, together defining the incremental change of colour (change per four pixels).

The way in which these parameters are generated is shown by the pseudo-Pascal listing and full algorithm appended to this description. It is assumed in the listings that interpolation takes place at every scanline, and for each group of pixels. The hardware described below assumes that interpolation takes place at quarter pixel rate. In the algorithm a group counter is used to achieve this. In the pseudo-pascal listings the group counter is represented by thevariable G_COUNTER and the number of pixels in each pixel group is represented by the constant DX_CLR_STEP.

The pixel rate process 20 takes the parameters provided by the scanline process 19, converts X ON and X EXTENT into a timing waveform ACTIVE which marks off the active part of the scanline, and during the interval of ACTIVE true repeatedly increments, RED, GREEN and BLUE at a quarter pixel rate by RED DX, GREEN DX and BLUE DX respectively. The hardware which performs these operations will be described below but the operations can be expressed by the pseudoPascal listing algorithm appended to the end of this description.

Referring again to Fig 1, the pixel rate processes 20 are synchronized to VIDEO CLOCKS passed from unit to unit on a bus 21. These clocks comprise HSYNC (horizontal sync) and PXCLK, the pixel rate clock. RED, GREEN and BLUE are all output as skewed 8-bit values on buses 39 for insertion on to a 8-bit R, G and B buses 22. Whether insertion takes place or not is determined by a priority contest between the number on a priority bus 23 and the local value of PRIORITY. If the bus wins, insertion dues not take place and the priority bus carries the bus number on to the next unit 20. If PRIORITY wins, insertion does take place and PRIORITY is passed on as the bus number to the next unit 20. In this way, the final output of the R, G, B buses 22 represents the pixel colour for the highest priority surface pertaining to that pixel, but with skewed bits, which may be de-skewed as explained above.

Fig 2 illustrates one pixel rate processing unit 20. A contour control unit 30 receives X ON and X EXTENT by way of a DATA bus 31 from the scanline process 19 and operates synchronously with PXCLK to generate ACTIVE. The start and end of ACTIVE must be timed correctly to within one pixel as the full pixel resolution must be utilized to create non-ragged edges. The values RED, RED DX etc are supplied to an R G B interpolator 32 which operates at quarter pixel rate defined by a clock signal denoted CLK/4. This is generated within the contour control signal 30 in such a way as to be phaselocked to the left hand edge of the polygon being drawn. The interpolator 32 starts interpolating when ACTIVE goes true and produces outputs R, G, B on the buses 39, which are fed to a pixel insertion unit 33 through which pass the 8-bit colour buses 22. Whether insertion takes place or not is determined by an ENABLE signal provided by a priority resolution unit 34 which compares PRIORITY with the number on the priority bus 23.

Each of the incremental quantities RED DX etc is a fractional quantity and for simplicity it is assumed in this embodiment that RED, GREEN, BLUE, R, G, and B and priority are all 8-bit quantities and that RED DX, GREEN DX and BLUE DX are all fixed point numbers with 8 fractional bits in addition to the 8 integer bits used for RED, GREEN and BLUE. Fig 3 then shows the relative time positions of the bits involved in computations. On the time axis in Fig 3, each little square occupies one pixels.

At an initial time t₀ the priority resolution unit 34 starts to process the bits on the priority bus and in PRIORITY, starting with the most significant bit, as indicated by the eight squares 34. Simultaneously the interpolator 32 starts to process the least significant fractional bits of RED and RED DX, etc. as indicated by eight dotted squares 35 for the RED bus only. At t₁ which is eight bit intervals after t₀, priority is resolved and the non fractional bits 36, 37, 38 for the RED, GREEN and BLUE buses start to appear, working from the least to the most significant bits. It is these bits which are output as R, G and B (Fig 2) for insertion on the colour buses, conditional upon the presence of ENABLE which is available at t₁.

The groups of squares in Fig 3 are shown as staircases because they are generated by pipelined elements, one per bit of each relevant bus. If single line buses were to be employed, the bit rate would have to increase from PXCLK up to 8 x PXCLK and all eight bits for the RED bus line (for example) would appear serially as a packet occupying the duration of one little square (four pixels) in Fig 3.

The four units of Fig 2 will now be described in more detail, commencing with the contour control unit 30, shown in Fig 4. This unit has an X ON counter 40 and an X EXTENT counter 41 for the current (n^th) line and buffer registers 42 and 43 for the values to be used in the next, (n+1)^th line. At the start of each line, HSYNC transfers the contents of the buffer registers 42, 43 to the counters 40, 41 and the buffer registers are then reloaded from the data bus 31. The counters are clocked by PXCLK to count down but initially only the X ON counter 40 is enabled (EN). When the left hand edge of the polygon is reached, the X ON counter 40 is empty and provides a signal TC (terminal count) which disables the X ON counter via an inverter 44, enables the X EXTENT counter 41 and sets a flip-flop 45 providing the aforementioned signal ACTIVE. The counter 41 counts down until the right hand edge of the polygon, whereupon its signal TC resets the flip flop 45 through an OR gate 46. In case the right hand edge should be off-screen, HSYNC also resets the flip-flop via the OR gate. The third bit of the X EXTENT counter 41 is also taken off as the interpolation bit rate clock CLK/4 which is accordingly phase locked to the left hand edge of the polygon, i.e. phase locked to the start of ACTIVE. This marks the time t₀ in Fig 3.

So long as ACTIVE is false it forces the priority resolution unit 34 to provide ENABLE also false (eight bits later since this unit is also pipelined). As soon as ACTIVE goes true the priority contest starts and ENABLE either stays false or goes true depending upon whether the priority bus or PRIORITY wins the contest. The priority resolution unit 34 is shown in Fig 5.

If the number input on the priority bus is A, the number

PRIORITY is B and the output number on the priority bus is Z, the bits of numbers A, B and Z will be denoted as follows:

A = a₁ . . . a_j . . . a₈

B = b₁ . . . b_j . . . b₈

Z = z₁ . . . z_j . . . z₈ where the subscripts 1 and 8 denote the most and least significant bits respective and j denotes a general bit.

The priority resolution unit 34 comprises eight bit logic units T₁ to T₈. Considering the general unit T_j, it receives the bits a_j and b_j and ouputs z_j. The unit T_j also receives inputs c_j-1 and d_j-1 from the next more significant unit T_j-1 and outputs c_j and d_j to the next less significant unit. The signal c_j indicates whether or not priority has been resolved at the unit T_j or at a unit of higher significance and d_j indicates, when priority has been resolved, in whose favour. The final bit dg constitutes the ENABLE signal, z _j becomes a_j for the priority resolution unit of the next pixel rate unit 20.

One set of equations defining the structure for T_j in the case of minimum priority resolution is as follows:

C_j = c_j-1 + (a_j

V (1) d_j = c_j-1.d_j-1 + a_j.

(2) z_j = a_j.b_j + c_j-1 (b_j.d_j-1 + a_j. (3)

The convention assumed is that c_j-1 = 0 means "not resolved" while c_j-1 = 1 means "resolved". If c_j-1 = 0 the value of d_j-1 is without significance. If c_j-1 = 1, then d_j-1 = 1 means the device has won the priority contest whereas d_{j -1} = 0 means the bus has won the priority contest.

The provision of the initial values c₀ and d₀ will now be considered. c₀ is the signal ACTIVE while d₀ is tied to logical 0. This cases ENABLE to be forced false by ACTIVE false, whereas during ACTIVE true, ENABLE is true only if PRIORITY has higher priority than the bus priority number A, (save that the state of ENABLE is delayed eight bits relative to the state of the ACTIVE). A fuller explanation of the priority resolution unit, and an example which resolves in favour of the maximum priority number, will be found in our copending application of even date, entitled

"Priority Resolution System".

Fig 6 shows part of the RG B interpolator 32, namely the part for one colour, which may be assumed to be RED. Fig 6 is replicated for the other colours. The interpolator handles sixteen bits, namely eight fractional bits and eight integer bits, in eight DFUs (dual function units) 50 for the fractional bits and eight DFUs 51 for the integer bits. All sixteen DFUs are pipelined and receive input bits from an initial colour value register 53 into which RED is wrtten at the start of each line and an incremental colour value register 54 into which RED DX is similarly written. RED which does not provide any inputs to the fractional DFUs; their RED inputs may be tied to 0. The incremental value RED DX provides inputs to the DFUs occupying both integer and fractional positions in the colour word. Only the outputs from the integers DFUs 51 are employed. They are denoted P1 (MSB) to P8 (LSB) (only PI to P4 show) and together form the R bus of Fig 2.

The basic action of each DFU 50 or 51 is as follows. When a signal on an input FI (function input) is false, the DFU latches its I input which is the corresponding bit of RED. When FI is true, it adds the latched vlaue to its D input which is the corresponding bit of RED DX, providing an output bit P and a carry bit to the next more significant DFU on CI. Moreover FI is pipelined on to the next DFU. The least significant DFU 50 has ACTIVE applied to its FI input. All DFUs are clocked CLK/4 so that pipelined bitwise additions takes place at quarter pixel rate.

This is illustrated in Fig 8 in which the abscissa represents CLK/4 which starts at 0 at the start of ACTIVE. At CLK/4 = 8 ENABLE goes true or stays false, depending upon who has won the priority contest and the integer DFUs 51 start to produce RED (latched in when ACTIVE was false) which appears in bit-skewed fashion on the R BUS, as indicated by the diagonal line 55. At CLK/4 = 9, RED + (RED DX) starts to appear (diagonal line 56) and so on.

Fig 7 shows the construction of one DFU 50 or 51 handling one bit. The registers 53 and 54 of Fig 6 are represented by one bit latches I(N) 60 and D(n) 61 for the current line, line n. These are loaded by HSYNC from buffers I(n+1) 62 and D(n+1) 63 which then receive the new bits of RED and RED DX respectively from the data bus 31.

The latches 60 and 61 are connected to a 1-bit multiplexer 64 which is controlled by FI to output I when FI is false and D when FI is true. The selected input is applied to an input A of a 1-bit adder unit 65 which receives inputs FI, CI = carry in and A and provides outputs F0 - function out (to the next DFU), CO = carry out and P = result. The unit 65 is clocked by CLK/4 and has the following properties. At each clock pulse, FO latches FI. If FI is false, P latches A. If FI is true, one bit addition of A, P and CI is effected to generate the new P and CO. Fig 9 is a block diagram of the unit 65, which comprises a function flip-flop 66, a P flipflop 67 and a carry flip-flop 68 which are set-reset flip-flops clocked by CLK/4. The flip-flop 66 simply latches FI to provide FO. An adder 69 adds A, P and CI to produce Q. A multiplexer 70 selects either A (FI false) or Q (FI true) to be latched in the P flip-flop 67. The carry produced by the adder 69 is latched by the carry flipflop 68 to provide CO. It will be appreciated that the phases at which the various items are clocked will need correct adjustment to ensure correct operations i.e. multiphase clock signals may be used. This design detail is not illustrated in Fig 9.

Fig 10 shows the pixel insertion unit 33, again just for RED. The lines for the input red bus 22, RED IN, are denoted R1 (MS) to R8 (LS) while the corresponding lines of the red bus 39 from the interpolator 32 are denoted SI to S8. The insertion unit is essentially an eight-channel multiplexer controlled by ENABLE but, because of the pipelined operation of the interpolator 32 and the corresponding skew of the bits on the buses 22 and 39, ENABLE has to be pipelined through eight multiplexer stages, one per bit. Each stage comprises a 1-bit multiplexer 71 and each, other than the last comprises a flip-flop 72 clocked by CLK. The flip-flops are cascaded, least to most significant bit and the least significant copies ENABLE. It will be noted that, although the interpolator 32 is pipelined at CLK/4 rate, the pixel insertion unit 33 treats RGB as if they were pipelined at CLK rate.

It will also be noted that the inteprolation effected by the R G B interpolator 32 carries on regardless of the state of ENABLE. This is because each processor 17 deals with one triangle (or clipped triangle) and the colout value of each pixel is produced by incremental calculation. Therefore, even if part of the object is hidden, the interpolation must still continue to ensure that the correct colour value is present if and when the surface emerges from hidding.

The interpolator has been somewhat simplified in Figs 6 and 7. In practice, the two's complement fixed point number representation is preferably used in the interpolator utilising a sign bit as well as an 8-bit integer portion and fraction bits. The colour values RED etc must always be positive but the incremental values RED DX etc may be positive or negative. The result of the difference accumulation is always positive and the sign bit may therefore be ignored. It is merely required to determine whether the DFUs add or subtract the incremental values. In two's complement arithmetic, the sign bit of the difference value cannot influence the result at less significant bit positions, therefore, the sign bit need not have any physical representaiton within the colour interpolator.

The number of fraction bits is determined by the minimum colour graident which has to be represented. Eight fractional bits have been assumed above. The number required is one more than that required to represent the minimum colour gradient. The extra bit is required to prevent an error in the least significant bit position from propogating into the integer part of the colour value. If the horizontal resolution is 1024 pixels and the colour is interpolated every fourth pixel, then the minimum colour gradient is one in 256. Eight fractional bits are required to represent this quantity. A one bit error will propogate 8-bit positions towards the most significant bit after 256 successive accumulations. Therefore nine fraction bits are required for a system with a minimum horizontal colour gradient of one in 256.

It is convenient to have the same number of fractional bits as there are bits on the priority bus. However, if there is a discrepancy, it can be compensated for by a corresponding delay element. For example, ACTIVE can be delayed at the input to the interpolator 32 or the input to the priority resolution unit 34, as may be required to generate ENABLE synchronously with interpolation of the least significant integer bit.

The reasons for accepting a fixed priority value for each surface have been explained above. This restriction could be avoided if the priority resolution was effected in a pipelined manner, least significant bit first. A most significant bit first difference adder would allow the same result to be achieved in conjunction with most significant bit first priority resolution.

As described above, inserted pixels completely overwrite the colour buses, i.e. overlaying surfaces are assumed to be opaque. The effect of overlaying a transparent surface could be achieved by positioning transparent surfaces last along the linear array of polygon processing sections 17. If the priority comparison for such a surface succeeded, the colour values on the corresponding buses 39 would not overwrite the values on the buses 22 but would modify these by pipelined subtraction.

In the above description, although interpolation is effected once every four pixels, the scanline algorithm is assumed to be performed every line. However, the division operations required to calculate the incremental colour quantities are expensive in computing time. The scanline algorithm may accordingly be implemented less than every scanline, say every third scanline (or on any scanline which contains a cusp). There is then some risk of colour interpolators overflowing or underflowing which will produce dramatic and unacceptable visual results. Accordingly, guard bands may be established at the extremes of the colour values so that black is equal to 16 and saturated colour is equal to 235, for exmaple.

SHADED SURACE GENERATION ALGORITHM

Version

RECALCULATE PARAMETERS ON EVERY SCANLINE

RECALCULATE COLOUR VALUES FOR EACH GROUP OF PIXELS ALONG SCANLINE

SCANLINE ALGORITHM

INPUTS

From Polygon Frame Buffer :-

LEFT, RIGHT : cusp lists Y-TOP, Y_BOTTOM : integer PRIORITY : positive integer

The following parameters are defined for each cusp in the cusp lists; X, Y, RED, GREEN, BLUE, d(x)/dy, d{RED)/dy, d(GREEN)/dy, d(BLUE)/dy.

OUTPUTS

X_ON : integer;

X_EXTENT, PRIORITY : positive integer; RED, GREEN, BLUE : positive Integer; d[RED)/dx, d(GREEN)/dx, d(BLUE)/dx : fixed point; ALGORITHM

Set the current left, and current right, cusps to the first Left, and first right, cusps respectively.

For each scanline in turn from the first scanline to the last scanline;

BEGIN

If scanline intersects the polygon

( e.g if scanline is between Y_TOP and Y_BOTTOM ) then BEGIN

If a left cusp is on this scanline then

initialise X_LEFT, RED_LEFT, GREEN_LEFT, BLUE_LEFT with the values of the current left cusp; make the next cusp in the left cusp list the current cusp;

else

add the dy increments from the previous cusp to X_LEFT, RED_LEFT, GREEN_LEFT, and BLUE_LEFT.

If a right cusp is on this scanline then

initialise X_RIGHT, RED_RIGHT, GREEN_RIGHT, BLUE_RIGHT with the values in the current right cusp; make the next cusp in tha right cusp List the current cusp,

else

add the dy increments from the previous right cusp to X_LEFT, RED_LEFT, GREEN_LEFT, and BLUE_LEFT,

Calculate the extent, .in pixels, of the intersection of the scanline and the polygon. Partially intersected pixels are included.

Calculate the extent, in pixel groups, of the intersection of the scanline and the polygon. Partially intersected pixel groups are included.

Calculate the red, green, and blue colour gradients, per pixel group.

Pass parameters to the pixel rate process.

END; { if scanline intersects polygon } END; { for each scanline in turn }

PIXEL RATE ALGORITHM

INPUTS

From Scanline Algorithm:-

X_ON : integer;

X_EXTENT, PRIORITY : positive integer; RED, GREEN, BLUE : positive integer; d(RED)/dx, d(GREEN)/dx, d(BLUE)/dx : fixed point;

From previous object processor :-

RED_BUS_IN, GREEN_BUS_IN, BLUE_BUS_IN : positive integer; PRIORITY_BUS_IN : positive integer;

OUTPUTS

RED_BUS_OUT, GREEN_BUS_OUT, BLUE_BUS_OUT : positive integer; PRIORITY_BUS_OUT : positive integer;

ALGORITHM

Initialise group counter.

Set RED, GREEN, and BLUE to the input values. For each pixel in turn along the scanline from the first pixel to the last pixel.

BEGIN

If pixel is inside, or on the edge of the polygon

[ e.g. if pixel is between X_ON and (X_ON+X_EXTENT) inclusive ] then BEGIN

If priority is greater than PRI0RITY_BUS_IN then Transfer the colour values RED, GREEN, BLUE to their respective output colour busses.

Transfer the priority value to the priority output bus else

Transfer the colour vaLues on the input colour busses to the output colour busses.

Transfer the priority value on the input priority bus to the output priority bus. END

Increment group counter. If start of a pixel group then Add dx increments to the colour values RED, GREEN, and BLUE. END PROGRAM SHADED_SURFACE_GENERATION_ALGORITHM;

CONST

DX_CLR_STEP = 4; GUARD_BITS = 1; SIGN_BIT = 1;

X_INTEGER_BITS = 9;

X_DY_FRAC_BITS = 9;

X_DY_BITS = SIGN_BIT + X_INTEGER_BITS + X_DY_FRAC_BITS;

CLR_INTEGER_BITS = 8;

CLR_DX_FRAC_BITS = 7 + GUARD_BITS;{ quarter resolution or a 512 display }

CLR_DX_BITS = SIGN_BIT + CLR_INTEGER_BITS + CLR_DX_FRAC_BITS;

CLR_DY_FRAC_BITS = 9 + GUARD_BITS ;{ CLR_DY_FRAC_BITS >= CLR_DX_FRAC_BITS }

CLR_DY_BITS = SIGN_BIT + CLR_INTEGER_BITS + CLR_DY_FRAC_BITS;

MAX_NUM_OF_CUSPS = 7;

FIRST_SCANLINE = 255;

LAST_SCANLINE = -256;

FIRST_PIXEL = -256;

LAST_PIXEL = 255;

TYPE

POS_INTEGER = 0..MAXINT;

Y_RANGE = LAST_SCANLINE.. FIRST_SCANLINE;

X_RANGE = [BIT [X_INTEGER_BITS]] FIRST_PIXEL.. LAST_PIXEL;

DELTA_X_RANGE = [BIT [X_INTEGER_BITS]] 0.. [LAST_PIXEL - FIRST_PIXEL];

X_DY_RANGE = [BIT [X_DY_BITS]] FIXED_POINT;

CLR_RANGE = [BIT [ CLR_INTEGER_BITS]] 0..[2**CLR_INTEGER_BITS]-1;

CLR_DX_RANGE= [BIT [CLRJ0XJ3ITS]] FIXED_POINT;

CLR_DY_RANGE= [BIT [CLR_DY_BITS]] FIXED_POINT;

CUSP = RECORD

Y : Y_RANGE;

X : X_RANGE; RED : CLR_RANGE

GREEN : CLR_RANGE

BLUE : CLR_RANGE

X_dy : X_DY_RANGE;

RED_dy : CLR_DY_RANGE

GREEN_dy : CLRJ3Y_RANGE

BLUE_dy : CLR DY RANGE end ; CUSP_PTR = O . .MAX_NUM_OF_CUSPS ; CUSP_LIST = ARRAY[CUSP_PTR ] OF CUSP ;

FUNCTION TRUNC_TO_INTEGER (X:FIXED_POINT) :INTEGER ;

BBGIN

{ This function performs a type conversion from a fixed point representation to an integer representation. The integer part of the fixed point number is returned as the result. The fractional part of the fixed point number is disregarded. 1

END;

FUNCTION FLOAT_TO_FXP (X:INTEGER ] :FIXED_POINT;

BEGIN

{ This function performs a type conversion from an integer representation of a number to a fixed point representation of the same number, }

END;

PROCEDURE PIXEL_PROCESS(X_ON : X_RANGE;

X_EXTENT : DELTA_X_RANGE;

PRIORITY : POS_INTEGER ;

RED_LEFT, GREEN_LEFT, BLUE_LEFT :CLR_RANGE; VAR RED, GREEN, BLUE : CLR_DX_RANGE;

RED_BUS_OUT, GREEN_BUS_OUT, BLUE_BUS_OUT : CLR_RANGE; PRIORITY_BUS_OUT : POS_INTEGER; X_DISPLAY : X_RANGE; G_COUNTER : DELTA_X_RANGE; BEGIN

RED : = FLOAT_TO_FXP (RED_LEFT]; GREEN: = FLOAT _TO_FXP (GREEN_LEFT]; BLUE : = FLOAT_TO_FXP (BLUE_LEFT]; G_COUNTER: =0; FOR X_DISPLAY:=FIRST_PIXEL TO LAST_PIXEL DO

IF [ X_ON <= X_DISPLAY ] AND [ X_DISPLAY <= [X_ON+X_EXTENT) ) THEN BEGIN

IF PRIORITY>PRIORITY_BUS_IN THEN BEGIN

RED_BUS_OUT : = TRUNC_TO_INTEGE_R(RED);

GREEN_BUS_BUT : = TRUNC_TO_INTEGER [GREEN];

BLUE_BUS_OUT : = TRUNC_TO_INTEGER [BLUE];

PRIORITY_BUS_OUT : = PRIORITY; END ELSE BEGIN

RED_BUS_OUT : = RED_BUS_IN; GREEN_BUS_OUT : = GREEN_BUS_IN; BLUE_BUS_OUT : = BLUE_BUS_IN; PRIORITY_BUS_OUT : = PRIORITY_BUS_IN ; END; G_COUNTER : = G_COUNTER+1; IF (G_COUNTER MOD DX_CLR_STEP] =0 { simulates divided down pixel clock } THEN BEGIN

RED : = RED + RED_dx; GREEN := GREEN + GREEN_dx; BLUE := BLUE + BLUE_dx; END; END; END;

PROCEDURE SCANLINE_PROCESS [LEFT, RIGHT : CUSP_LIST;

Y_TOP, Y_BOTTOM : INTEGER; PRIORITY : POS_INTEGER];

VAR X_LEFT, X_RIGHT : X_DY_RANGE; { fixed point }

RED_LEFT, GREEN_LEFT, BLUE_LEFT : CLR_DY_RANGE; { fixed point ] RED_RIGHT, GREEN_RIGHT, BLUE_RIGHT : CLR_DY_RANGE; { fixed point } Y_DISPLAY : Y_RANGE; { subrange of INTEGER } LEFT_PTR, RIGHT_PTR : CUSP_PTR; { subrange of INTEGER } X_EXTENT, X_CLR_GROUP : DELTA_A_RANGE; { subrange of INTEGER } RED_DX, GREEN_DX, BLUE_DX : CLR_DX_RANGE; { fixed point }

PROCEDURE DY_STEP (SIDE : CUSP_LIST; VAR SIDE_PTR : CUSP_PTR; VAR X_SIDE : X_DY_RANGE;

VAR RED_SIDE, GREEN_SIDE, BLUE_SIDE : CLR_DY_RANGE); BEGIN { procedure dy_sep } IF Y_DISPLAY = SIDE [SIDE_PTR]. Y THEN

WITH SIDE [SIDE_PTR] DO BEGIN

X_SIDE : = FLOAT_TO_FXP [X];

RED_SIDE : = FLOAT_TO_FXP [RED]; GREEN_SIDE:= FLOATJTO_FXP(GREEN); BLUE_SIDE : = FLOAT_TO_FXP (BLUE); SIDE_PTR : = SIDE_PTR+1;

END ELSE BEGIN

WITH SIDE [SIDE_PTR-1] DO BEGIN

X_SIDE : = X_SIDE + X_dy; RED_SIDE : = RED_SIDE + RED_dy; GREEN_SIDE:= GREEN_SIDE + GREEN_dy; BLUE_SIDE := BLUE_SIDE + BLUE_dy; END; END; END; { procedure dy_step ]

BEGIN [* procedure line rate *] LEFT_PTR: = 0; RIGHT_PTR: = 0;

FOR Y_DISPLAY : = FIRST_SCANLINE DOWNTO LAST_SCANLINE DO BEGIN

IF (Y_BOTTOM <= Y_DISPLAY] AND [Y_DISPLAY <= Y_TOP) THEN BEGIN

DY_STEP [ LEFT, LEFT_PTR, X_LEFT, RED_LEFT, GREEN_LEFT, BLUE_LEFT ]; DY_STEP [ RIGHT, RIGHT_PTR, X_RIGHT, RED_RIGHT, GREEN_RIGHT, BLUE_RIGHT ];

X_EXTENT : = TRUNC_TO_INTEGER [X_RIGHT - X_LEFT) + 1;

X_CLR_GROUP : = [X_EXTENT DIV DX_CLR_STEP] + 1;

RED_dx = TRUNC_TO_INTEGER [RED_right - RED_left) DIV X_CLR_GROUP; GREEN_dx = TRUNC_TO_INTEGER [GREEN_right - GREEN_left) DIV X_CLR_GROUP; BLUE_dx = TRUNC_TO_INTEGER [BLUE_right - BLUE_left) DIV X_CLR_GROUP;

PIXEL_PROCESS [TRUNC_TO_INTEGER [X_LEFT), X_EXTENT, PRIORITY,

TRUNC_TO_INTEGER [RED_LEFT], TRUNC_TO_INTEGER [GREEN_LEFT],

TRUNC_TO_INTEGER [BLUE_LEFT],

RED_DX, GREEN_DX, BLUE_DX );

END;

END; { procedure scenline_process ]

Claims

1. A graphics system for display of shaded polygons, comprising a polygon frame buffer, means for computing and storing in the polygon frame buffer sets of parameters defining cusps of polygons and corresponding incremental quantities which define the shading of the polygons, scanline processing means operative in real time synchronously with respect to a raster-scan display to provide from each set of parameters, a set of parameter signals including signals marking the beginning and end of the part of each scanline crossing a polygon and first and second plural-bit signals defining an initial colour for the said part of the scanline and an incremental colour quantity, a plurality of pixel processing units operative on respective ones of the sets of parameter signals, a colour bus comprising at least one colour line, and a source of clock pulses, each pixel processing unit being responsive to the set of parameter signals supplied thereto and to the clock pulses to perform bitserial incrementing, at a bit rate established by the clock pulses, of the said first signal in accordance with the said second signal, and to reiterate such incrementing over an interval determined by the signals marking the beginning and end of the part of a scanline crossing a polygon, thereby to provide a plurality of bits for the colour bus in respect of each pixel or small group of pixels.

2. A graphics system according to claim 1, wherein the clock pulses are at a submultiple of the pixel rate.

3. A graphics system according to claim 2, wherein each pixel processing unit comprises pixel insertion means operable at pixel rate to introduce respective bits from the said plurality of bits on to respective lines of the colour bus.

4. A graphics system according to claim 1, wherein the clock pulses are at pixel rate and each pixel processing unit comprises pixel insertion means operable at pixel rate to introduce respective bits from the said plurality of bits on to respective lines of the colour bus.

5. A graphics system according to claim 1, wherein the clock pusles are at an integral multiple of pixel rate and each pixel processing unit comprises pixel insertion means operable at clock rate to introduce packets of bits per pixel on to the or each line of the colour bus.

6. A graphics system according to claim 3, 4 or 5, wherein the pixel insertion means are pipelined.

7. A graphics system according to any of claims 1 to 6, wherein the said bit-serial incrementing is pipelined.

8. A graphics system according to claim 7, wherein each pixel processing unit comprises first and second registers for storing the first and second plural-bit signals, means for updating each register from the scanline processing means at scanline rate or a submultiple thereof, and a plurality of function units, one per bit of the registers, pipelined in order of increasing significance to transfer from unit to unit, at the said clock rate, an active signal whichis asserted during the said part of each scanline crossing a polygon, each function unit comprising a 1-bit adder with an output register and being operative to latch the corresponding bit of the first plural bit signal in the output register when the active signal is not asserted, and, when the active signal is asserted, to form in the output register the sum bit from the bit in the output register, the corresponding bit of the second plural bit signal and a carry-in bit from the preceding function unit, and to provide a carry-out bit to the succeeding function unit.

9. A graphics system according to claim 8, wherein the plurality of bits for the colour bus are taken from a most significant subset only of the function units.

10. A graphics system according to any of claims 1 to 9, wherein each pixel processing unit incudes a priority resolution unit and wherein a priority bus is routed through the priority resolution units in parallel with the colour bus.

11. A graphics system according to claim 10, wherein the sets of parameters include priority numbers individual to the pixel processing units and each priority resolution unit is adapted to compare with the processing unit priority number the incoming bus priority number on the priority bus, to pass on to the priority bus whichever number pertains to the higher priority and to control introduction of bits on to the colour bus in dependence upon the sense of the priority resolution.

12. A graphics system according to claim 11, wherein each pixel processing unit includes a pixel insertion unit which passes the colour bus unchanged if the priority resolution is in favour of the priority bus bit substitutes the bits provided by the pixel processing means for the bits on the colour bus if the priority resolution is in favour of the pixel processing unit.

13. A graphics system according to claim 12, wherein each priority resolution unit comprises pipelined stages in order of decreasing significance which pass on a bit signaling the sense of the priority resolution from the first stage whereat corresponding bits of the processing unit priority number and the bus priority number disagree, the output of the last such stage signalling the sense of the priority resolution to the pixel insertion unit.

14. A graphics system according to claim 13, wherein the stages of the priority resolution unit are pipelined at pixel rate.

15. A graphics system according to claim 13 or 14, insofar as dependent upon claim 8, wherein the active signal also controls the first stage of the priority resolution unit so as to indicate resolution in favour of the priority bus if the active signal is not asserted.