JPS62219182A - Display processor for graphics display system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Background of the Invention The use of computers to synthesize visual scenes (computer graphics) is a growing field of computer science. The applications of computer graphics are countless and include computer-aided design (CAD), composition of illustrative diagrams, generation of titles and other graphic displays for use in television, and simulation of physical events. ing.

In order to computerize the generation of a scene involving object(s), the primary step is to create a three-dimensional description of the object to be displayed and store it in mathematical form in a database. It is normal that this is the case. The data is then processed and manipulated so that the scene can be displayed on a viewing screen.

Processing information from a database can be thought of as using five basic functions.

1. Divide (mathematically) an object into smaller pieces that can be conveniently handled. These sections are usually planar polygons, each representing a portion of the surface of the object to be displayed.

2) Extract data corresponding to the classification of objects from the database.

3. Convert the 3D description to a 2D description in "screen" coordinates.

4. Select the pixels of the visible screen that must be activated to display the segment and define their color and intensity.

Determine which areas of the 56 segments are visible in the scene and display those areas.

By repeating this process for all segments of all objects in the scene, a display representing the desired scene is obtained.

This invention relates to the latter two processes. Further, the invention relates to drawing vectors or line segments on a visible screen, which may or may not display the visible screen or other objects.

Traditional display processors are limited in the speed at which they can process and display data. This restriction is due, in part, to the conventional tendency to use general-purpose computers that are controlled by software that includes algorithms for performing the required operations. This necessarily requires that the calculations be performed serially, so that the final result may not be achieved as quickly as desired.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an improved display processor for a graphics processing system that has significantly improved operating speed as compared to the prior art.

Using dedicated hardware and pipelines, the display processor of the present invention performs many of the necessary calculations in parallel, resulting in significantly faster operating speeds. Additionally, it utilizes unique efficient algorithms to further improve speed.

This invention, as opposed to random scanning or stipple display,
A raster scan type display is used. This is an external database,
and shape processors that provide data in the form of data packets, each data packet describing a planar polygon or line segment in a three-dimensional coordinate system. In the presently preferred embodiment system, the origin of the coordinate system is the upper left corner of the screen, although other locations may be used if desired. The integer value of X refers to the pixel location to the right of the origin, and the integer value of Y refers to the raster scan line number from top to bottom. The depth (Z) value refers to the relative distance behind the screen.

As is common in the field of computer graphics, each object in the scene to be displayed is divided into a series of small, but not necessarily regular, planar polygons. For complex objects, such as a human face, the polygons should be small enough, and their shapes and colors should be such that together they give a satisfactory representation of the desired object. Simpler objects, such as flat surfaces with uniform illumination, can be represented satisfactorily by larger polygons.

The display processor of this invention seeks to reproduce the display of both complex and simple objects.

There are two basic modes of operation for display processors.

In one mode (referred to as polygon fill mode), the polygons are reproduced on the visible screen, positioned so that the composite effect of all polygons is a representation of the desired object or scene. Ru. In this mode, each polygon is represented on the screen as an area of color that is not delimited by contrasting contours. Each polygon is characterized by a uniform color over its area, the intensity of which can be varied depending on the desired shading.

Shading is controlled by intensity gradient information provided by an external shape processor. The shading of the polygon may be flat (uniform) or may vary linearly across the face of the polygon in the X direction, the Y direction, or both.

In the presently preferred embodiment of the invention, the color and intensity information for each pixel on the screen is combined into a 12-bit binary number and this number is stored in a frame buffer.

The upper bits are used to select the color and the lower bits are used to select the intensity. The user is free to decide how many of the words are used to define the color as well as how many are used to define the intensity. To form a combination word, the results of the intensity calculations are right-shifted by the number of bits necessary to place them in the desired position in the word, and then the shifted intensity values are color-shifted. Add to the binary number to be selected. The bit that selects the color occupies the most significant position.

In fill polygon mode, the display processor utilizes data defining each side of the polygon to create a "span" that includes color and intensity information. Each span contains information about one raster line to be displayed. If there is a previously processed polygon (by using Z or depth buffer), the depth position of the polygon at each pixel address is
By comparing its depth, only if this comparison shows that the new polygon is closer to the screen at that pixel location than any previously processed polygon. Color and intensity information is entered into the pixel address of the frame buffer. In this way, all but the hidden faces of the polygon are not displayed. The polygons used in polygon fill mode are not necessarily solid and may have internal openings. According to the idea of the present invention, polygons having such openings or notches do not need to be specially treated, and are treated in the same way as ordinary polygons. For each raster line intersecting a polygonal aperture, more than one span is generated, but the operation of the device remains the same.

The second mode, called "vector drawing," allows you to draw straight line segments at desired locations on the screen. The vector drawing mode is also used for "edge highlighting", ie, separating a polygon (or a group of polygons) with lines of a different color from the polygon itself.

Vector drawing mode uses information that defines the coordinates of each vertex and the slope of the line (in the XY, XZ, and YZ planes) to sequentially address the pixels to be activated to draw the line. .

A means is also provided for drawing vectors that look like dashed lines. The repetition of the "shape" to create the desired pattern of on and off pixels can be up to 64 pixels. This is accomplished by using a unique shift register with continuously rotating combinations of 1's and 0's corresponding to the desired pattern. The output of the shift register inhibits writing to the frame buffer when the output of the register is in the "1" state. Character features can be used in conjunction with the polygon fill mode to create the effect of a surface with fabric.

Other features of the invention will become apparent from the following detailed description of presently preferred embodiments of the invention.

DETAILED DESCRIPTION OF THE INVENTION FIG. 1 is an overall block diagram of a complete graphics processing system such as may be used with the display processor of the present invention, showing the major devices and their connections. Information describing each object or surface in the scene to be displayed is entered into the system via the user interface 10.

This user interface may include, for example, a joystick, a mouse, a graphics tablet, a dial,
It can be a box, trackball or alphanumeric keyboard.

To synthesize a scene, each object in the scene is constructed as a series of planar polygons, which together form a close approximation of the object or objects to be displayed. do. Data defining these polygons is stored in a database 11. When displaying a scene, data packets each describing one polygon are sent to the VME data bus 12.1 at a time. via shape processor 13
will be forwarded to. While the shape processor is performing calculations on one data packet, database 11 prepares to transfer the next packet.

For each polygon to be displayed, the shape processor 13 supplies the display processor with raster coordinate data defining each side of the polygon, as well as certain data regarding the polygon as a whole. Data bus 12
transmitted via. The display processor 20 converts the received side and polygon data into a color for each pixel of the effective raster;
Convert the intensity and relative depth into data that specifies the intensity and relative depth, and send this data to the frame buffer and z-buffer 22.23
(Fig. 2) and finally a visual representation of the scene in the CR
Display on T21.

Frame buffer 22 and Z buffer 23 are common devices used in the field of computer graphics. In the presently preferred embodiment of the invention, the frame buffer consists of a randomly addressable memory device with 1280x1024 addresses, each address being a randomly addressable memory device.

Tres stores 12 bits. The Z buffer is the same device size, but accommodates 16 bits.

As will be explained later, there are basically two modes of operation for data processing in a display processor.

These modes are modes that color polygons, i.e.
These are a "polygon filling" mode and a line segment drawing mode, that is, a "vector drawing" mode. In addition, the r-side route mode allows initialization commands to be sent to the frame buffer and Z buffer 22.23 to set the X and Y addresses to be used as starting addresses for the respective modes of operation.

In the following description, the coordinate system and notation shown in FIG. 4 will be used. As an example, FIG. 4 shows a plane polygon (42, 43, 44, 45) superimposed on a grid of coordinates. There are triangular holes (46, 47, 48) inside the polygon. The illustrated polygon may be a complete surface by itself, or it may be a small segment of a complex surface to be displayed. The display processor handles both cases the same way.

An XY coordinate system is used with the origin at the upper left corner of the screen.

Raster lines are numbered sequentially downward, and pixel positions are numbered sequentially from the origin to the right. A pixel location is defined by the drift of the upper left corner of the square containing that pixel. For this reason, 41
The pixel represented by the shaded line shown in is located at coordinates (7, 3).

Each pixel address (eg, X, , Y,) consists of an integer number represented by the most significant bit of a 12-bit binary word. However, as shown by point Xu in FIG. 4, the exact value of X at the intersection of the side and the raster line is usually not an integer. In some cases, rather than its exact value, Xu
Integer values of quantities such as are used in calculations, and in these cases an underline is used (for example, Xu) to represent the integer value. Integer values are obtained by simply truncating the binary word for the precise value to the number of bits representing the integer.

Side 42 of the polygon terminates in two vertices 40.49. A set of coordinates X L by the pixel with the upper vertex (40)
, Yt + Zt is defined, and Zt is the point X, , Yt
represents the distance behind the screen. The value we call Xu is also at the intersection of this side and the first raster line it intersects (i.e. raster line Y, +1, which we call Yu).
defined as the value of X (with high precision).

Similarly, it can be seen that Xd is the precise X coordinate of the intersection of side 42 and the raster line just above vertex 49.

Xb, Y, , Z are the drifts of pixels with vertex 49.

The slopes of the sides with respect to the three axes are expressed by the functions dX/dY, dZ/
It is expressed by dX and dZ/dY.

Another variable that is relevant to the display is intensity, which is denoted by the letter S. Depending on the desired shading of the polygon, S is the function dS
/dXSdS/dY and dS/dZ may vary about any or all axes.

In the presently preferred embodiment of the invention, the strength calculation is 2 to ensure that rounding errors of 2 do not affect the display.
Implemented with 7-bit precision. This precision is much higher than needed for display purposes, but fewer bits are used to set the CRT's pixel intensity. The color and intensity information for each pixel is contained in a 12-bit word formed during processing and stored at a pixel address in frame buffer 22. The color is the highest and 7
1. The user selects the number of bits necessary to specify the desired number of colors. The strength is specified by the least significant bit. 12 containing both types of information
To generate the bit words, a 12-bit color word is first generated (by the shape processor), with the color information occupying the number of most significant bits specified by the user, and the remaining bits being O's. The 27-bit intensity word is truncated to 12 bits and then right-shifted by the number of bits necessary to avoid the color bits. The color word and intensity word are then added to find a compound word containing both quantities. A limiting circuit is provided to prevent the intensity word from overflowing into the color bit area of the word.

A simplified block diagram of display processor 20 of the presently preferred embodiment of the invention is shown in FIG.
This diagram shows the main blocks of the processor and shows the main data and instruction paths. The processor is directly controlled by microsequencer 26. The microsequencer receives commands via the VME data bus 12 from the geometry processor, user interface, or other portion of the system as appropriate. There is a writable control store (randomly addressable memory device) in the microsequencer 26, which in the presently preferred arrangement can accommodate 8 words by 60 bits. During initialization, a microprogram for controlling the display processor is downloaded to the writable control storage portion of the microsequencer 26 via the VME data bus 12. In operation, the microsequencer generates a series of addresses to which program instructions are issued by the writable control store.

Instructions for the microprocessor 27 pass through bus 39 and instructions for the video processing means pass through bus 34. In this specification, references to microsequencer 26 refer to both the microsequencer and the writable control storage device u.

As previously mentioned, display processor 20 receives data from shape processor 13 and processes the data to obtain the desired display.
Manipulate that data. The data arriving from the shape processor is fed into one of two identical input memories 24.25. Each human powered memory 24,25 consists of bus gates, input and output registers, address counters/registers, and random access memory devices. At any given time, one of these memories is
one is coupled to the E data bus 12 and the other is coupled to the Y and D buses of the display processor. Thus, one memory can receive human input data via an external interface while operating on previously received data stored in the other memory. Instructions from writable control storage 26 control selection of input memory functions.

Memory addressing may be sequential or random under the control of the microprogram. When performing a read operation, data is loaded into the memory's output register and applied to the Dl line at the appropriate time. In a write operation, data from the Y bus is loaded into an input register of the memory and then into the memory device under control of the microprogram. When processing an input data block, the input memory can be used to directly store the results.

Arithmetic processing elements and data buffers (microprocessor 27, multiplier 28 and associated registers)
Performs 6-bit parallel arithmetic and logical operations. Arithmetic operations consist of addition, subtraction, multiplication, division, increment, subtraction, sum, single and polyshift, and comparison. All common logic functions can be performed including and, or, exclusive or, logical inversion, and others.

Multiplication is performed in high speed multiplier 28. It receives two 16-bit operands from the Y bus and outputs (in two cycles) a 32-bit product on the D bus. Division is performed by passing one operand through a reciprocal table. This table can be considered to be within multiplier 28 in this specification.

All arithmetic operations other than multiplication and division and all logical operations are performed by a microprogrammable microprocessor 27, which in the presently preferred embodiment is a fully 16-bit parallel arithmetic/logic unit, 16-bit - Consists of a barrel shifter, 32 16-bit registers and associated logic. The output data and/or intermediate data can be temporarily stored in the input memory 24, 25 or in the scratch memory 31.

The output of the processing functions is provided to a memory 29, typically a 64-word by 18-bit first-in, first-out FIFO. This memory provides flexible data coupling to a video processing system (VPS) 30.

The information provided to display processor 20 relates to whether a mode of operation is desired, polygon filling or vector rendering. Regardless of which mode is selected, information is provided in packets. In polygon filling mode, a packet describes one polygon, and in vector drawing mode, a packet describes one line segment.

In polygon filling mode, the packet contains information defining each side of the polygon and information about the polygon as a whole. For each edge, the following data (referred to as "edge packet")
There is.

PTR: An identification pointer that allows access to data related to a polygon.

HOR: Flag indicating whether the side is horizontal.

SSF: Start/stop flag indicating whether the interior of the polygon is on the left or right side of the side.

Xt s Y IZ t% X u% S u+, Yb
, dX/dY, dS/dY0 For the polygon as a whole, we have the following. That is, the color of the face of the polygon, dZ/dX, dZ/dY0 The above information for the complete polygon is stored in the manual memory 24.
．． 25, microsequencer 26 couples its memory to the D and Y busbars and begins calculations to determine which pixels in the raster to activate to display the polygon.

For ease of understanding, the operation of the system will be explained using a polygon shown as an example in FIG. Note that the dimensions of the pixels shown in FIG. 4 are very large compared to the dimensions of the polygon, so that the polygon of FIG. 4 is substantially distorted when displayed. However, for convenience of explanation, the idea of the present invention will be easier to understand if a relatively large pixel is explained.

Generally speaking, a microprocessor 27, a multiplier 28
and related components receive edge and polygon data provided to input memories 24-25 and, for each valid raster line of the polygon, provide a video processing system (VPS) 30 with start and stop information on that line. Provide data identifying the pixel and the Z and S values for the starting pixel. VPS 30 receives this data along with the gradient data sent to it and calculates the intensity and Z values for each pixel between the start and stop pixels. The Z value is used to exclude hidden surfaces and is stored in the Z buffer 23, while the intensity values for non-hidden surfaces are stored in the frame buffer 22 for later display on the CRT 21. .

When starting a calculation, a list of input memory addresses ("
ordering Y, list) and scratch
It is stored in the memory 31. The addresses in this list are valid input memories (24 or 25) that contain edge bucket data for each edge of the polygon being processed.
) indicates the position within. This list consists of the top vertex of each edge,
That is, Y.

Raster line order is maintained with . Ordering Y (a given item in the list may have more than one set of addresses of edge buckets I...data.

The ordered Yt list for the simple polygon shown in FIG. 4 has addresses for locating edge packet data in the following order.

Item Number Edge Packet Address 1 42.43 2 46.47 Notice that edge 48 does not appear in this list. This is because side 48 is a horizontal side and does not separate identical internal pixels. The horizontal edge flag HOR prevents processing of horizontal edges. By using an ordered Yt list, you can process raster lines that intersect each edge sequentially, without having to process the raster lines above and below the end of the edge, thus speeding up the display processor. becomes higher. In other words, taking the polygon shown in FIG. 4 as an example, the ordering Y, list includes the raster line associated with the upper vertex of the edge packet associated with edges 42 and 43, i.e., line 0 rather than line O. To enable data processing to be started from 1. As we will see, because of the way the data is processed, it will actually be raster line Yt+1, or Yu (or raster line 2 in the case of sides 42 and 43), which is the first raster line with valid pixels.

After the ordering Y, the list is complete, calculations by the display processor proceed to create a series of spans. The sum of these spans is made to appear on the CRT screen as a polygon with the desired color.

"Span" is data that defines the state of each pixel along a raster line separated by two sides of a polygon. For a given polygon, there may be more than one span in a single scan line. For example, in FIG. 4, raster line 6 includes two spans. The spans start with the span associated with the lowest numbered raster line (this is determined by ordering Y, by looking up the list) that intersects the polygon,
They are generated one at a time. In order to prepare the processing, create and manage "a effect strike". The valid edge list includes the address of edge packet data corresponding to each edge that intersects the raster line currently being processed.

The generation of spans will be explained in two steps.

At first, there were 27 microprocessors and 27 microprocessors! ::28
and the calculations performed by related components, the second being the operations performed by VPS 30.

Considering the ordering Y and list for the polygon shown as an example in FIG. 4, it can be seen that the valid edges corresponding to the first raster line to be processed are edges 42 and 43. At this time, the valid edge list has edge packet addresses for edges 42 and 43. The edge packet for edge 42 has a start flag, whereas the edge packet for edge 43 has a stop flag.

In connection with the presently preferred embodiment of the invention, there is an option that a pixel is not considered part of a polygon unless its coordinates (the coordinates of the upper left corner of the pixel's space) are within the boundaries of the polygon. rules were adopted. For this reason, this rule:
The first valid pixel of the polygon in FIG. 4 is pixel (5,2). The start and stop pixels along the raster line can be determined by the following equation.

On the start side, X 1 - X 1 + 1 On the stop side, X2 = mXl Here, Xl is the X coordinate of the start pixel of the span, X2 is the X coordinate of the last pixel of the span, and Xl is the Y of the side and span is the integer value of the actual intersection of the coordinates. First span (Y-2)
Then, Xl for side 42 is Xu%, that is, 4, and side 4
3, X, is 6.

As can be easily seen, before performing the calculations described above, the X coordinates of the start and stop sides for the raster line must be ordered and paired. In conjunction with the pairing calculations, a test is performed to eliminate apparent spans where the stop pixel is a smaller address than the start pixel. Such anomalies can occur when a portion of a polygon looks smaller than one pixel, or when calculation rounding errors cause the edges to be slightly out of order. In either case, such data is not processed. Pairing and sequencing is performed by microprocessor 27 under control of a program located in writable control storage 26. As a result of the ordering of start/stop coordinates and not handling pairs where the stop pixel has a smaller address than the start pixel, holes in the plane automatically appear as holes, and an equivalent special ordering is required to deal with it. No further processing is required.

First raster t! ; The value of Zl (Z coordinate of the first effective pixel) for I(Yu) is calculated from the Z and Z gradient supplied from the shape processor 13 as follows.

Z+ −Z* + (Xu X,)(dZ/dX)+
d Z/d Y knee, where Xu is an integer value of Xu.

The formula for the raster line following Yu is as follows.

Z+ wZ+ (p r ev) 10(, x, -X+ (p r ev) (dZ/d
X) + dZ/dY Z+ (p r e v) is 21 of the previous raster line,
X, is the integer value of the actual intersection of the Y coordinate of the edge and the current raster line, and X+ (prev) is the previous raster line.

The data supplied from the shape processor 13 are S,
That is, it includes the intensity of the first valid pixel u+1 (ie, Xu+1) of the raster line Yu. For the raster lines that follow, use the following formula:

S+ -S+ (prev)+dS/dY ＼S+
(p r ev) is 81 of the previous raster line.

The ending strength (S2) for each raster line is similarly calculated using the starting S value and the slope of the stopping F side of the span. Then, calculate the span slope dS/dX.

dS S! -S+ dX x, -x, +1 The extra 1 in the denominator indicates that the calculated S2 is actually not for the last pixel in the span, but for the next pixel beyond the last. taking into account.

There may be more than one span in a given raster line, such as in the polygonal region of FIG. 4 that contains holes. Each side of the hole is treated as a side of a polygon, and when pairing the sides it will be appreciated that side 46 with the stop flag is ahead of side 47 with the start flag. For this reason, side 46
．． The region of raster lines between 47 and 47 is not processed. The above calculation must be performed for many pairs of valid edges. Once all spans have been calculated for the raster line, compare Yb for all valid edges with the current raster line address. If Y is reached for any edge, that edge is not processed any further. Furthermore, the ordering Y
(Access the edge packet corresponding to the next item in the list to determine whether Y, for the new edge has been reached. If either has happened, adjust the edge pair appropriately.

After passing through the last Yb, the calculation for that polygon is finished and the calculation for the next polygon is started.

For example, for the polygon shown in FIG. 4, the valid edges list initially has addresses for edge buckets that describe edges 42 and 43. After raster line 3 is processed, edge 46
and 47 are added to the valid edge list, and the pair of edges is 42 and 4.
6, and updated to 47 and 43. After raster line 4, Y for edge 43 and Y for edge 44 have been reached, so edge 43 is deleted and edge 44 is added to the effective edge list. The pairs are adjusted appropriately.

When the span calculation is complete, the result is loaded into FIFO register 29 and then passed through buffer register 33 to the appropriate register in VPS 30 when requested by VPS 30.

FIFO 29 allows Vr'S 30 to operate on one set of spanned data while another set of data is loaded into the FIFO. To allow for this overlap, it is preferred that the F I FO 29 be of sufficient "depth" to hold at least two complete sets of span data. - The data sent to the VPS 30 in polygon fill mode is as follows (the number of bits following each item is the number of bits conveyed in the presently preferred embodiment of this invention, and is used here as an example) Note that since the data bus used can only accommodate 16 bits, some data values may require two machine cycles to be completely transferred).

Polygon data: dZ/dX...30 bits Y+-1 (address of the raster line above the first Yu of the polygon)...12 bits color...12 bits intensity shift...4 bits I... Character pattern: 64 bits (all 0s) Character length
...6 bits (all 1) Span fist data: Xl...12 bits X2...12 bits Zl...30 bits Sl...27 bits Y, ...1 bit 1nC As mentioned above\ Additionally, the gradient dS/dX is transmitted.

Depending on the type of shading desired, dS/dX may be a polygon-related quantity or a span-related quantity. A flag Y, is signaled to the +nc VPS 30 with the first span on a given raster line, and the Y register and frame buffer and Z buffer within the VPS 30 are
Increments to the next raster line before processing span data. The meaning of the character-shaped signal will be explained later in connection with the vector drawing mode.

Polygon filling mode (all character pattern registers are 01)
As mentioned in connection with 1), all the length registers of the glyph type are
The glyph function has no effect. However, as will be apparent to those skilled in the art after reading the description of the glyphs in the vector rendering mode, glyph functions can be used in the polygon fill mode to define the texture of the display surface.

3A and 3B are block diagrams of a VPS 30 (video processing device). FIG. 3A shows various data processing elements, and FIG. 3B shows a control device 30B that controls the data processing functions of the PS. Arrow C in Figure 3A is
Connections to control device 30B are shown. Control lines from controller 30B to the various registers, multiplexers (MUX), adders and comparators (CMP) are not shown for clarity.

Upon receiving the command on line 34, VPS 30 begins loading data to the data register via line 35. The data is transferred to the Y bus register 31 and buffer in a predetermined order under the control of the microsequencer 26.
From register 32, via line 35, the following registers are loaded.

Quantity Register dZ/dX: dZ/dX (52) Yl: Frame buffer 22 and Z buffer 23 Color Two colors (54) Intensity shift: Intensity shift (55) Character pattern: Shift register 56 (all 0) Character type Length: Character length (57) (all 1) After the polygon-related quantities described above are loaded, the span-related quantities described next are transferred from the FIFO 29 to the buffer register 3.
3 and line 35.

Melon Register X+ :X+ (5g) - The X address registers of buffer 22 and Z buffer 23 are also set to Xl. Y, crawl 1C only accompanies the first span of the star line.

The presently preferred embodiment of this invention is 10 MI
Operating at a clock speed of Iz, each quantity with 16 bits or less can be loaded in one machine cycle of 100 nanoseconds, but a melon with more than 16 bits can be loaded in two machine cycles. Loaded in cycles. After loading is complete, processing of span data for the first span begins. Calculation of various parameters is 1
It is done in parallel with a clock speed of 00 nanoseconds. Note that although the Z and S calculations are done with high precision (30 and 27 bits, respectively), only 16 and 12 bits are left in the Z buffer and frame buffer, respectively. This is to prevent rounding errors from accumulating and affecting the operation of the device. Truncating to 16 and 12 bits, respectively, is indicated by “TRUNC” in the block diagram of FIG.
The size of the data is also limited to be within an acceptable range. This limiting effect is indicated in FIG. 3A by the letters "LIMIT."

Y1□ when the calculation of the brightest span begins. According to
The Y address register of the frame buffer and Z buffer 22-23 is incremented by one, making the address the value Yu for the first raster line of the polygon.

At the same time, the Z buffer 23 at position (XI, Y+)
The value of Z in is coupled via register 62 to comparator 63 where it is compared with the contents of Z register 60 (truncated to 16 bits). When the value from register 60 is equal to or less than the value in Z-buffer, the truncated one in Z-register 60 is sent to multiplexer 64.
66 to the Z buffer and is written in place of the old Z value. If the contents of register 60 are greater than the old value in the Z-buffer, the old value is written to the Z-buffer again. Thus, at each address, the Z buffer records the Z value of the object closest to the screen. The result of the comparison in the comparator 63 is stored in the character pattern register 5.
6 along with a signal from AND gate 65 to inform controller 30B whether to enable writing to that address in the frame buffer. This discussion assumes that the output of the glyph pattern register 56 is such that it enables the AND gate 65, and therefore whether a new value is written to the frame buffer 22 or not. It is only a comparison of the values of Z that determines whether. Characteristics of character shapes will be explained later. By comparing the values of Z,
It will be appreciated that by ensuring that the frame buffer only contains information related to the closest objects, hidden surfaces are eliminated.

At the same time, the contents of dZ/dX register 52 are added to the contents of Z register 60 in adder 67 and the result is coupled to Z register 60 via multiplexer 68. The new content of Z register 60 is the value of Z (Z+ +dZ/dX) corresponding to pixel location X1+1.

In parallel with the 1° calculation described above, the intensity shift register 5
5 acts on the shift device 75, and the contents of S register 61
The truncated contents of are shifted to the right by a predetermined number of bits, and the resulting value is sent to the color register 54 by the adder 76.
is added to the contents of A limiting circuit 98 is provided to ensure that the intensity value added to the contents of the color register 54 does not invade the color bits. The sum thus formed determines the color and intensity as previously explained. The output of adder 76 is coupled to frame buffer 22 via multiplexer 77 and frame data register 78. If the Z comparison shows that the polygon being processed is closer to the screen at this address than the previously processed polygon, then the frame buffer is This value is written to.

Furthermore, at the same time, the contents of the dS/dX register 85 are transferred to the adder 8.
6 is added to the contents of S register 61 and the resulting new intensity value is coupled to S register 61 via multiplexer 87 .

This is the value of S used for pixel X1+1 (S1+dS/d
X).

Finally, a comparison of XI register 58 and X2 register 59 is performed in comparator 90. If they are not the same,
The Xl register and the X address registers in the frame buffer 22 and Z buffer 23 are all incremented, and the above calculation is repeated for pixel X1+1. X
The number of registers is increased by adding 1 to the contents of the register in adder 93 and writing the result to the register. The contents of the XI register are X2 register 59
Continue this process until the contents of
• When the comparator 90 causes the controller 30B to send a 1-bit "done" signal to the microsequencer 26 via line 36. The “Completed” signal is the VPS
Upon receiving this "done" signal, microsequencer 26 causes FIFO 29 to begin filling the registers of VPS 30 with data for the next span.

This process continues until all spans for a given polygon are completed, and then another polygon is started, or the line segment can be drawn in vector drawing mode.

If the next function to perform is to draw a vector,
Or draw the sides of the polygon with a different shading from the shading of the faces (
(edge highlighting), a different processing algorithm than described above is used to fill the frame buffer and Z buffer.

The information received by the input memory 24, 25 in the vector drawing mode is similar to the information received in the polygon filling mode, but
It's a little different from that. As an example, a case in which the line segment shown in FIG. 5 is drawn in vector drawing mode will be described next. This line segment has an upper vertex in pixel space (9,1) and a lower vertex in space (1,5). The symbols are the same as those used for the polygon filling mode.

As an example, the pixel area that is activated when drawing the line segment considered here is given a shading line (assuming that the line segment being drawn is the closest object to the visible screen). .

For each vector, the VME from the shape processor 13
The following quantities are sent via the data bus 12:

XL (XI) Yz(YI) X, (X?) Y, (Yz) Zt or Zb instead Xu or Xv instead dX/dY dZ/dX dZ/dY Color (including intensity) Letter pattern Depending on the length of the shape XL + Yt and the order in which X, , Yb are sent,
Whether a line segment is drawn from top to bottom is determined by whether it is drawn from bottom to top. They are drawn downwards in the order listed above. x,,yb at XI I Y1 position,
X, ,Y, as X2. By sending to position Y2 and sending alternating amounts Z and Xb, it will be drawn upwards.

The next explanation will be about drawing downward.

The drawing direction is determined by two flags SBX and SBY. These flags set Xl to X, and Y
As a result of comparing l with Yl, microprocessor 2
Generated by 6.

If Xl is larger than X2, it is 5BX-1, and if Yl is larger than Yz, it is 5BY-1.

These flags are
Determine whether to increment or decrement the l and/or Yl registers (58 and 95). SB flag set (1)
If so, the associated register is set to decrement, and when this flag is not set (0), the register is incremented. XI Increase register 58 5BX-1)
, YI When the register 95 is incremented (SBY-0), the vector is drawn downward to the left. If set to SBX or O, the X register is incremented and the vector advances to the right. If SBY is 1, the vector is drawn upward. Incrementing or decrementing the Xl and Yl registers is performed by adders 93.94 that add 1 or d-multiply the contents of the associated register and write the result to the register.

As in the polygon filling mode, the data needed to draw a line segment is routed through one of two paths: via FIFO 29 and buffer register 33, or via line register 31 and buffer register 32. via VPS 3
Combined with 0. Loaded into the following registers.

Data register XI:XI (58)YV
:YI (95)Zt :Z(60) Xu :Xu (61) Xb :X2 (59) Yk+ :Yz (96)dX/dY
: dX/dY (85) dZ/dX : dZ/
dX (52) dZ/dY: dZ/dY (97) Color Two colors (54) Letter pattern Two letter pattern (56) Letter length
Two-character length (57) 1 (OR: Control unit 30B SBX: Control unit 30B SBY; Control unit 30B frame buffer 22 and Z buffer 23 address registers x, , y, Set to .

After loading data into the registers of VPS 30, a command from microsequencer 26 initiates the rendering sequence. Comparison of the contents of the Z register 60 (truncated to the same number of bits as the Z buffer (16)) and the previous contents of the Z buffer is done in the same way as described above for the fill polygon mode, but for each After the calculation, the Z register 60
The difference is that each time the address is increased, the number is not only increased by dZ/dX, but also each time the Y address is increased, the number is increased by dZ/dY from the dZ/dY register 97.

If the truncated contents of Z register 60 in any comparison is less than or equal to the contents of Z buffer 23 at that address, then the new value of Z is written to the Z buffer and the contents of color register 54 are written. It is coupled to frame buffer 22 via multiplexer 77 and frame data register 78 in the same manner as previously described.

The initial pixel addresses are Xt and Yt as described in 1. Using the vectors shown in Figure 5 as an example,
It can be seen that , is at the coordinates (9, 1). Since Xl is larger than X2 and Y2 is larger than Yl, 5BX-1 and 5BY=0.

Therefore, as the drawing of the vector progresses, the Xl register 58 is decremented and the Y] register 95 is incremented.

Before incrementing or decrementing the register of fEm, set Yl to Y2.
comparator 9'l) and compares Xl with X2 (comparator 92). Compare Xl with Xu (Xu register 61
The content of is truncated to 12 bits. comparator 90). In the particular example line segment shown in FIG. 5, YL=1, Y=5, X1-9, X2-1, and Xu-8. If none of the comparisons are equal, as is the case in the example chosen here, the X register 58 is decremented by one pixel space, and the X address registers of the frame buffer and Z buffer are similarly done. After this, the Z comparison and write operations to the Z buffer and frame buffer are repeated for the now addressed pixel (8,1). A current comparison of X and Y shows that Xu is equal to the contents of the Xl register 58. When this happens, comparator 92 causes controller 30B to register Y1, frame buffer and Z
It is possible to increase the number of Y address registers of buffers (22, 23). At the same time, the contents of the dX/dY dimeter 85 are added to the contents of the Xu register 61. At this time, the contents of the Xu register 61 are the vector and Y-
This will be the exact coordinates of the intersection of 3. It will be appreciated that the intersection of the vector and the Y pixel coordinate is calculated with 27 bit precision and that the value is later truncated to represent the integer address of the X coordinate. The reason is that when drawing a vector to highlight an edge, the vector appears exactly on the edge of the polygon, and pixels with the polygon's color do not protrude beyond the highlighted edge. It is for the purpose of

After repeating the comparison of Z at the address of pixel (8, 3) and the one-input operation, three comparisons of X are performed, but they are not equal. Therefore, the Xl register 58 and Z
The buffer and frame buffer X address registers are decremented by one address. Xl register 58 and X2 register 59 are equal, but Yl register 95
This procedure is repeated every clock cycle until and/or both occur. After Xl (58) becomes equal to X2 (59),
The X register no longer decrements and YL(95) becomes Y2(9
6), the Y register no longer increments. When both are equal, the vector is complete and controller 30B sends a "done" signal to microsequencer 26 via line 36.

As can be easily seen, the Z value stored in the Z buffer 23 of the vector is the Z value of the vector at that address.
Areas smaller than the value of will not be drawn, and objects previously entered in that area will be buffered and displayed in the final scene. Similarly, subsequent polygons or lines whose Z values indicate that they are closer to the front of the scene than the vector drawn at any pixel address are , displaces the vector at that address.

The discussion so far about drawing line segments has not taken into account the "character shape" capabilities of the device.

The term ``character'' as used here refers to the ability of the device to generate broken lines, such as broken lines. By using glyph pattern register 56 and glyph register 57 to control whether particular pixels of the vector are activated, various combinations of glyph patterns can be used.

The digit pattern register 56 is a 64-bit parallel-in, serial-out circular shift register that is loaded with four sequential 16-bit words when the VPS3Q is loaded with vector rendering data. Additionally, a 6-bit word is loaded into the glyph register or counter 57. A 6-bit word in glyph counter 57 controls the working length of glyph pattern register 56, so up to 64 stages can be utilized, but the contents of glyph counter 57 Accordingly, the register may act as a shorter register. That is, if the repetition of the glyph pattern is 40 pixels, the glyph counter 57 is set so that the glyph pattern register 56 operates as a 40-stage circular shift register.

The 64-bit programmable length glyph pattern register 56 is uniquely designed to minimize gate count and area. A typical shift register is designed using a flip-flop type memory element and a multiplexer for each cell. 2 to 1
The multiplexer selects either the previous value of the cell or the bus value in response to the shift/load signal. Making the shift register have a programmable length from 1 to 64 further complicates the multiplexer and selection logic. The multiplexer in this case becomes a 3-to-1 selector. The three inputs are a preset or loadable value, a nearest neighbor for shift mode, and a rotation bit to select a programmable length.

Due to the unique 11 configuration of letter pattern register 56 in this invention, the gate count is reduced to approximately 400 gates from a typical design requiring over 600 two-man equivalent gates. .

To achieve this, we first changed the memory cells to D-type gates and increased the number of gates from 6 to 3.5 per cell.
decreased to 1. This is possible because registers multiplex output connections rather than shifting data from cell to cell. The output shift effect is 3
This is done by a 4-to-1 multiplexer in stages. The first stage reduces the 64 bits to 16, the second stage selects 4 of the 16, and the third stage selects 1 bit from the remaining 4. Stepping through the 64 latches across the three stages of the multiplexer is accomplished by a 6-bit digitizer counter 57. The output of the counter controls the select line of the multiplexer. After reaching the programmed length, the counter is reset and starts counting again. Overall, the number of gates is reduced by a factor of 3 with comparable performance and flexibility compared to the prior art.

A block diagram of the glyph counter 57 and glyph pattern register 56 is shown in FIG. Sixty-four D-type switches 101 are shown coupled to four 16-bit input registers 105.

Input data defining the glyph pattern entering from line 35 is sent as four sequential 16-bit words to 64 D-shaped registers 101 via manual registers 105-1, -2)-3 and -4. -1 to 101-64. 4
The Q output of each latch in each group is provided to sixteen multiplexers 102-1 through 102-16. Similarly, the outputs of each group of four multiplexers 102 are output from four multiplexers 103-1 to 1.
03-4. Finally, the outputs of the four multiplexers 103 are output to the last multiplexer 104.
supplied to

A glyph counter 57 receives a 6-bit signal on line 35 which sets the counter to count up to the number of repeats in the glyph pattern and then start over. The output of the shape tool counter 57 is 64 latches 10
1 to be coupled to the output of the glyph pattern register 56 via multiplexers 102, 103, 104, depending on the count of the counter. The output of multiplexer 104 sequentially scans latch 101 as the count in shape length counter 57 changes. This allows the glyph pattern register 56 to act as a parallel-in-serial-out shift register with programmable length.

To illustrate the effect of the glyph features of this invention in vector rendering mode, we will turn on 15 pixels, 5 pixels off, 5 pixels on, 5 pixels off, 5 pixels on, and finally 5 pixels. Suppose we want to draw a vector with a dashed line effect where is off. In other words, a longer dash is followed by two shorter dashes. The length of the character shape is set to 40 pixels by the character length counter 57. this is,
This is because it is the total number of pixels in the repetition. The letter pattern register 56 then operates as if it were a 40 stage shift register, with the output of the fourth O stage circulating to stage one. The glyph controller uses negative logic (O from register 56 is a valid pixel), so register 5
The loading of 6 is 15 0s, 5 1.5 0s,
It should be 1.5 0's and 5 1's. The output of the character-shaped pattern register 5'6 is connected to the AND gate 65.
This instructs controller 30B (depending on the appropriate Z comparison) to inhibit writing data to the frame buffer whenever glyph pattern register 56 has an output of 1. Give a signal.

When all polygons and line segments in the scene have been processed, frame buffer 22 stores t!2 12-bit words corresponding to each pixel on the screen of CRT 21. 1 is there. Each word carries information regarding the color and intensity required for each pixel to be illuminated. To display a scene, the addresses of the frame buffer are scanned in raster fashion, and the contents of each address are passed through a color lookup table 36 and a D/A converter 37 before being sent to the CRT 21. For each address in the frame buffer, three digital words are generated by the look-up table 36, which are converted to voltage amplitudes by the D/A converter 37, and then the red, green and blue signals of the CRT 21 are generated. The electron gun is activated to generate the desired color and intensity for each pixel.

[Brief explanation of drawings]

FIG. 1 is a simplified block diagram of the entire graphics processing system, FIG. 2 is a block diagram of the display processor of the present invention, FIGS. 3A and 3B are block diagrams together showing the video processing device of the present invention, and FIG. The figure is a line diagram showing an example of a polygon for explaining the invention in detail in the polygon filling mode, and Fig. 5 is an example of a line segment for explaining the invention in detail in the vector drawing mode. FIG. 6 is a block diagram of the glyph pattern register and glyph length counter of the present invention.

Claims (1)

Claims: 1) In a display processor for a raster scan computer graphics system, an input memory receives and stores data related to at least a portion of a scene to be displayed, and a processing program is stored. a control storage device;
an arithmetic processing unit that performs arithmetic and logical operations on data in the memory under control of the program; and receiving data from both the input memory and the arithmetic processing unit;
a video processing device for calculating in parallel relative depth and intensity within said scene for each pixel forming part of said portion of said scene to be displayed; means for storing data defining the color and intensity of each pixel in the portion of the scene to be displayed; and means for storing data defining the color and intensity of each pixel in the portion of the scene previously processed; means for comparing the relative depth at the pixel position of the previously processed portion of the scene to be displayed; means for preventing the storage of color and intensity data for pixels forming part of said portion of the scene to be displayed if the depth is less than the depth of said portion of the scene to be displayed. 2) A display processor according to claim 1, further comprising: a data path between the input memory, the arithmetic processing unit and the video processing unit; a display processor including a path for program instructions to the device and the video processing device; 3) A display processor according to claim 1, further comprising a first-in-first-out memory for coupling data from said arithmetic processing unit to said video processing unit. 4) In the display processor according to claim 1), the input memory is constituted by two sections, the sections being arranged so that previously received data can be used in the display processor. a display processor alternating between being coupled to an input bus and coupled to said arithmetic processing unit for receiving data; 5) A system for displaying a representation of a three-dimensional object in a two-dimensional raster, in which a raster is generated in a video processing device that generates data defining a desired intensity of each pixel on at least a portion of a raster line of a display screen. a first data register storing data defining a desired pixel intensity of the first pixel of the above schedule; a second data register storing data defining an incremental value of intensity; iteratively forming the sum of the contents of the two data registers of the first
means for replacing the contents of the data register with said sum;
a third data register for receiving each sum and storing it at a predetermined address. 6) The video processing device according to claim 5) further comprising: a fourth data register for storing data defining a color of a pixel in the portion of the raster line;
Add the contents of the data registers to each of the above sums.
means for forming a number of digital words, wherein the color defining data is represented by a first group of digits in the digital word, and the intensity defining data is represented by a first group of digits in the digital word. such that said digital word is represented by two groups of digits,
The video processing device stores the sum in the third data register instead of the sum. 7) The video processing apparatus according to claim 6), wherein said means for adding the contents of said fourth data register to each sum changes the position of a digit of each said sum; A video processing device comprising means for producing a binary number containing only zeros in the digit positions occupied by color data within the contents of said fourth data register. 8) In the video processing device according to claim 5), data defining the relative depth within the scene of a point on the object corresponding to each pixel within the scene to be displayed is provided. a fourth data register for storing data; a fifth data register for storing data defining a depth increment;
and means for iteratively forming a sum of the contents of a fifth data register; and a sixth data register for receiving and storing said sum at a predetermined address; Compare with the previously determined sum stored in the corresponding address of the register, and if said sum exceeds the previously determined sum stored in the corresponding address;
a video processing device comprising said sum and corresponding means for inhibiting storage of said sum.