WO1985004037A1 - Self-tuning coin recognition system - Google Patents

Self-tuning coin recognition system Download PDF

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Publication number
WO1985004037A1
WO1985004037A1 PCT/US1985/000369 US8500369W WO8504037A1 WO 1985004037 A1 WO1985004037 A1 WO 1985004037A1 US 8500369 W US8500369 W US 8500369W WO 8504037 A1 WO8504037 A1 WO 8504037A1
Authority
WO
WIPO (PCT)
Prior art keywords
coin
coins
test
limits
output signal
Prior art date
Application number
PCT/US1985/000369
Other languages
English (en)
French (fr)
Inventor
Frederic P. Heiman
Original Assignee
Mars, Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24340677&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO1985004037(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Mars, Incorporated filed Critical Mars, Incorporated
Priority to BR8505538A priority Critical patent/BR8505538A/pt
Priority to KR1019850700279A priority patent/KR930006098B1/ko
Priority to JP60501328A priority patent/JPH0727585B2/ja
Priority to KR1019850700280A priority patent/KR930007271B1/ko
Publication of WO1985004037A1 publication Critical patent/WO1985004037A1/en
Priority to DK502785A priority patent/DK502785A/da

Links

Classifications

    • GPHYSICS
    • G07CHECKING-DEVICES
    • G07DHANDLING OF COINS OR VALUABLE PAPERS, e.g. TESTING, SORTING BY DENOMINATIONS, COUNTING, DISPENSING, CHANGING OR DEPOSITING
    • G07D5/00Testing specially adapted to determine the identity or genuineness of coins, e.g. for segregating coins which are unacceptable or alien to a currency
    • G07D5/08Testing the magnetic or electric properties
    • GPHYSICS
    • G07CHECKING-DEVICES
    • G07DHANDLING OF COINS OR VALUABLE PAPERS, e.g. TESTING, SORTING BY DENOMINATIONS, COUNTING, DISPENSING, CHANGING OR DEPOSITING
    • G07D5/00Testing specially adapted to determine the identity or genuineness of coins, e.g. for segregating coins which are unacceptable or alien to a currency
    • G07D5/02Testing the dimensions, e.g. thickness, diameter; Testing the deformation

Definitions

  • the present invention related to the examination of coins for authenticity and denomination, and more particularly to an adjustment-free self-tuning mechanism for coin testing.
  • the present invention can be applied to a wide range of electronic coin tests for measuring a parameter indicative of the acceptability of a coin.
  • the coin acceptance limits for a coin test are set and readjusted by the apparatus itself, based upon computed statistical function of the parameter measured by the coin test for a predetermined number of previously accepted coins.
  • a standard set of initial acceptance limits for any coin which is to be tested such as the U.S. 5-cent coin, is initially stored in all coin testing apparatuses made in accordance with the present invention. These initial limits are set rather wide so that virtually 100% acceptance of all genuine 5-cent coins is assured.
  • acceptable coins are inserted into the apparatus and are tested by one or more sensors.
  • a statistical function of the parameter measured by each sensor is computed. For example, a running average of the parameter can be computed.
  • the new acceptance limits can be set at the running average plus or minus a stored, preestablished constant or a stored, preestablished percentage of the running average.
  • standard initial acceptance limits are not stored and tuning is begun by transmitting an instruction signal that the apparatus is to be tuned for particular coin such as the 5-cent coin. Then, a predetermined number of valid 5-cent coins are inserted and tested. A single test coin representative of the average 5-cent coin may be used. A statistical function is computed and acceptance limits are set based thereon. Similarly, the process is repeated for additional denominations of coins which are to be accepted. In either case, the initial factory tuning is accomplished by merely inserting predetermined number of valid coins.
  • the statistical function is continuously recomputed by the electronic coin testing apparatus as additional acceptable coins are inserted.
  • the coin testing apparatus reweights the computation so that the computation of the statistical function is based upon information for only a predetermined number of the most recently inserted and accepted coins.
  • Fig. 1 is a schematic block diagram of an embodiment of electronic coin testing apparatus in accordance with the invention
  • Fig. 2 is a detailed schematic diagram of circuitry suitable for the .embodiment of Fig. 1
  • Fig. 3 is a schematic diagram indicating suitable positions for the sensors of the embodiment of Fig. 1
  • Figs. 4A and B are a flowchart of the operation of the embodiment of Fig. 1.
  • the coin examining method and apparatus of this invention may be applied to a wide range of electronic coin tests for measuring a parameter indicative of a coin's acceptability and to the identification and acceptance of any number of coins from the coin sets of many countries, the invention will be adequately illustrated .by explanation of its application to identifying the U.S. 5-cent coin.
  • the following description concentrates on the details for setting the acceptance limits for a high frequency diameter test for U.S. 5-cent coins, but the application of the invention to other coin tests for U.S. 5-cent coins, such as a high frequency thickness test, and to. other coins will be clear to those skilled in the art.
  • Fig. 1 shows a block schematic diagram of an electronic coin testing apparatus 10 in accordance with the present invention.
  • the mechanical portion of the electronic coin testing apparatus 10 is shown in Fig. 3.
  • the electronic coin testing apparatus 10 includes two principal sections: a coin examining and sensing circuit 20 including individuals sensor circuits 21, 22 and 23, and a processing and control circuit 30.
  • the processing and control circuit 30 includes a programmed microprocessor 35, an analog to digital (A/D) converter circuit 40, a signal shaping circuit 45, a comparator circuit 50, a counter 55, and NOR-gates 61, 62, 63, 64 and 65.
  • A/D analog to digital
  • Each of the sensor circuits 21, 22 includes two-sided inductive sensor 24, 25 having its series connected coils located adjacent opposing sidewalls of a coin passageway. As shown in Fig. 3, sensor 24 is preferably of a large diameter for testing coins of wideranging diameters. Sensor circuit 23 includes an inductive sensor 26 which is preferably arranged as shown in Fig. 3.
  • Sensor circuit 21 is a high frequency low power oscillator used to test coin parameters, such as diameter and material, and to "wake up" the microprocessor 35.
  • the frequency and amplitude of the output of sensor circuit 21 change as a result of coin interaction with the sensor 24.
  • This output is shaped by the shaping circuit 45 and fed to the comparator circuit 50.
  • the comparator circuit 50 produces an output on line 36 which is connected to the interrupt pin of microprocessor 35.
  • a signal on line 36 directs the microprocessor 35 to "wake up” or in other words, to go from a low power idling or rest state to a full power coin evaluation state.
  • the electronic coin testing apparatus 10 may be employed in a coin operated telephone or other environment in which low power operation is very important. In such environments, the above described wake up feature is particularly useful.
  • the above described "wake up" is only one possible way for powering up upon detecting coin arrival. For example, a separate arrival detector could be used to detect coin arrival and wake up the microprocessor.
  • the output from shaping circuit 45 is also fed to an input of the A/D converter circuit 40 which converts the analog signal at its input to a digital output.
  • This digital output is serially fed on line 42 to the microprocessor 35.
  • the digital output is monitored by microprocessor 35 to detect the effect of a passing coin on the amplitude of the output of sensor circuit 21. In conjunction with frequency shift information, the amplitude information provides the microprocessor 35 with adequate data for particularly reliable testing of coins of wideranging diameters using a single sensor 21.
  • the output of sensor circuit 21 is also connected to one input of NOR gate 61 the output of which is in turn connected to an input of NOP gate 62.
  • NOR gate 62 is connected as one input of NOR gate 65 which has its output connected to the counter 55.
  • Frequency related information for the sensor circuit 21 is generated by selectively connecting the output of sensor circuit 21 through the NOP gates 61, 62 and 65 to the counter 55.
  • Frequency information for sensor circuits 22 and 23 is similarly generated by selectively connecting the output of either sensor circuit 22 or 23 through its respective NOR gate 63 or 64 and the NOR gate 65 to the counter 55.
  • Sensor circuit 22 is also a high frequency low power oscillator and it is used to test coin thickness.
  • Sensor circuit 23 is a strobe sensor commonly found in vending machines.
  • the sensor 26 is located after an accept gate 71.
  • the output of sensor circuit 23 is used to control such functions as the granting of credit, to detect coin jams and to prevent customer fraud by methods such as lowering an acceptable coin into the machine with a string.
  • the microprocessor 35 controls the selective connection of the outputs from the sensor circuit 23 to counter 55 as described below.
  • the frequency of the oscillation at the output of the sensor circuits 21, 22 and 23 is sampled by counting the threshold level crossings of the output signal occurring in a predetermined sample time. The counting is done by the counter circuit 55 and the length of the predetermined sample time is controlled by the microprocessor 35.
  • One input of each of the NOR gates 62, 63 and 64 is connected to the output of its associated sensor circuit 21, 22 and 23.
  • the output of sensor 21 is connected through the NOP gate 61 which is connected as an inverter amplifier.
  • the other input of each of the NOP gates 62, 63 and 64 is connected to its respective control line 37, 38 and 39 from the microprocessor 35.
  • the signals on the control lines 37, 38 and 39 control when each of the sensor circuits 21, 22 and 23 is interrogated or sampled, or in other words, when the outputs of the sensor circuits 21, 22 and 23 will be fed to the counter 55.
  • microprocessor 35 produces a high (logic "1") signal on lines 38 and 39 and a low signal (logic "0") on line 37
  • sensor circuit 21 is interrogated, and each time the output of the NOR gate 61 goes low, the NOR gate 62 produces a high output which is fed through NOR gate 65 to the counting input of and counted by the counter 55.
  • Counter 55 produces an output count signal and this output of counter 55 is connected by line 57 to the microprocessor 35.
  • Microprocessor 35 determines whether the output count signal from the counter 55 and the digital amplitude information from A/D converter circuit 40 are indicative of a coin of acceptable diameter or not by determining whether the outputs of counter 55 and A/D converter circuit 40 or a value or values computed therefrom are within stored acceptance limits. When sensor circuit 22 is interrogated, microprocessor 35 determines whether the counter output is indicative of a coin of acceptable thickness. Finally, when sensor circuit 23 is interrogated, microprocessor 35 determines whether the counter output is indicative of coin presence or absence. When both the diameter and thickness tests are satisfied, a high degree of accuracy in discrimination between genuine and false coins is achieved.
  • Fig. 2 is a detailed schematic diagram of circuitry suitable for the embodiment of Fig. 1 including the following components: Resistors
  • Sensor circuit 21 is a low power oscillator circuit having an inductive sensor 24 comprising two coils connected in series and located on the opposing sidewalls 36 and 38 shown in Fig. 3.
  • the two coils of sensor 24 have a combined inductance of approximately 3.5mH and the sensor circuit 21 oscillates at an idling frequency of approximately 170kHz.
  • An oscillating output signal from sensor circuit 21 is taken from point A and connected through shaping circuit 45 to A/D converter 41 and comparator circuit 50.
  • the signal at point B is the envelope of the oscillation output signal of sensor circuit 21.
  • the amplitude of the signal at the point B is approximately 3.5 volts.
  • the comparator circuit 50 produces an output on line 36 which is fed through a NOR gate and a diode to the interrupt port of microprocessor 35 and wakes up microprocessor 35. Amplitude and frequency information for diameter testing are then generated and evaluated as discussed above.
  • Sensor circuit 22 shown in detail in Fig. 2 is also an oscillator circuit and it produces frequency test information relating to the width of a coin passing sensor 25.
  • the oscillator shown in Fig. 2 has an inductive sensor 25 comprising two coils connected in series and located on the opposing side walls 36 and 38 shown in Fig. 3.
  • the two coils of sensor 25 have a combined inductance of approximately 400uH and the oscillator circuit has an idling frequency of approximately 750kHz.
  • the sensor circuit 23, the strobe sensor has its inductive sensor 26 located after a coin routing gate 71 as shown in Fig. 3.
  • the single coil of inductive sensor 26 has an inductance of approximately 240uH and sensor circuit 23 has an idling frequency of approximately 850Hz.
  • the strobe sensor is used to detect coin passage, to prevent coin jamming and customer fraud.
  • the microprocessor 35 is a CMOS device with its RAM power supply 80 backed up by a 3 volt lithium battery LB. This power arrangement provides for nonvolatile memory. Other devices including EEPROM and NOVPAM devices can be used to achieve the same result. As shown in Fig. 2, the three chips labeled 58, 59 and 60 constitute the external program memory. Where a microprocessor 35 is used which has sufficient internal memory, such as an Intel 80C49, the chips 58, 59 and 60 may be eliminated.
  • the electronic coin testing apparatus 10 is incorporated into a coin operated telephone.
  • the apparatus 10 is only powered up when the phone is off-the-hook.
  • each of the sensor circuits begins to oscillate.
  • the microprocessor 35 samples and stores idling or no coin amplitude (A o ) and frequency (f o ) values for sensor circuit 21 and frequency values for sensor circuits 22 and 23. Then, the microprocessor "goes to sleep” or enters rest or standby mode. In this mode, it consumes very little power until an interrupt signal is produced on line 36 thereby indicating that a coin has been inserted and waking up microprocessor 35.
  • Microprocessor 35 upon being awakened is fully powered and it evaluates the information from the sensor circuits 21 and 22 and determines whether or not the detected coin is an acceptable coin.
  • a diroensionless quantity F- ⁇ f/f o is then computed and compared with stored acceptance limits to see if this value of F for the coin being tested lies within the acceptability range for a valid coin.
  • this type of measurement technique also applies to parameters of a sensor output signal other than frequency, for example, amplitude.
  • the present invention is specifically applied to the setting of coin acceptance limits for particular sensors providing amplitude and frequency outputs, it applies in general to the setting of coin acceptance limits derived from a statistical function for a number of previously accepted coins of the parameter or parameters measured by any sensor.
  • the F value is stored and added to the store of information used by microprocessor 35 for computing new acceptance limits.
  • a running average of stored F values is computed for a predetermined number of previously accepted coins and the acceptance limits are established as the running average plus or minus a stored constant or a stored percentage of the running average.
  • both wide and narrow acceptance limits are stored in the microprocessor 35.
  • these limits might be stored in RAM or ROM.
  • whether the new acceptance limits are set to wide or narrow values is controlled by external information supplied to the microprocessor through its data communication bus.
  • a selection switch connected to one input of the microprocessor 35 might be used.
  • microprocessor 35 tests for the state of the switch, that is, whether it is open or closed and adjusts the limits depending on the state of the switch.
  • the narrow range achieves very good protection against the acceptance of slugs; however, the tradeoff is that acceptable coins which are worn or damaged may be rejected.
  • the ability to select between wide and narrow acceptance limits allows the owner of the apparatus to adjust the acceptance limits in accordance with his operational experience.
  • Other ports of the microprocessor 35 are connected to a relay control circuit 70 for controlling the gate 71, shown in Fig. 3, a clock 75, a power supply circuit 80, interface lines 81, 82, 83 and 84, and debug line 85.
  • the microprocessor 35 can be readily programmed to control relay circuit 70 which operates a gate to separate acceptable from unacceptable coins or perform other coin routing tasks.
  • the particular details of controlling such a gate do not form a part of the present invention.
  • For further details of typical gate operation see for example, U.S. Patent No. 4,106,610 assigned to the assignee of the present invention. See also, Plesko, "Low Power Coin Routing Gate", U.S. Application No. 585,252 assigned to the assignee of the present invention and filed on even date herewith for details of a preferred gate suitable for use in conjunction with this invention.
  • the clock 75 and power supply 80 supply clock and power inputs required by the microprocessor 35.
  • the interface lines 81, 82, 83 and 84 provide a means for connecting the electronic coin testing apparatus 10 to other apparatus or circuitry which may be included in a coin operated vending mechanism which includes the electronic coin testing apparatus 10. The details of such further apparatus and the connection thereto do not form part of the present invention.
  • Debug line 85 provides a test connection for monitoring operation and debugging purposes.
  • Fig. 3 illustrates the mechanical portion of the coin testing apparatus 10 and one way in which sensors 24, 25 and 26 may be suitably positioned adjacent a coin passageway defined by two spaced side walls 36, 38 and a coin track 33, 33a.
  • the coin handling apparatus 11 includes a conventional coin receiving cup 31, two spaced sidewalls 36 and 38, connected by a conventional hinge and spring assembly 34, and coin track 33, 33a.
  • the coin track 33, 33a and sidewalls 36, 38 form a coin passageway from the coin entry cup 31 past the coin sensors 24, 25.
  • Fig. 3 also shows the sensor 26 located after the gate 71, which in Fig. 3 is shown for separating acceptable from unacceptable coins.
  • Figs. 4A and 4B are a flowchart of the operation of the embodiment of Figs. 1-3.
  • initial acceptance limits for each test are stored in the microprocessor 35 of the electronic coin testing apparatus 10. These initial limits are set quite wide guaranteeing almost 100% acceptance of acceptable coins. These acceptance limits are used only in the original tuning.
  • a predetermined number of known acceptable coins of each denomination are inserted. For example, eight acceptable 5-cent coins are inserted. The inserted coins are detected by the sensor circuit 21, microprocessor 35 is awakened, amplitude and frequency tests are conducted for each coin using sensor circuit 21, and a second frequency test is conducted using sensor circuit 22.
  • new acceptance limits are computed based.on the test information for the eight acceptable coins. These new limits are used for testing additional coins which are inserted.
  • the frequency test using sensor circuit 21 will be further discussed, but it should be understood that similar processing is performed for each test undertaken in the coin validation process.
  • Figs. 4A and 4B illustrates the process involved in the coin telephone context. It will be understood that the method and apparatus of the present invention can be used in other contexts.
  • the general method of Figs. 4A and 4B may be understood by taking all f variables as representing any function which might be tested, such as frequency, amplitude and the like, for any coin test. The specific discussion which follows will be in terms of frequency testing for United States 5-cent coins.
  • the microprocessor 35 After a phone off-the-hook condition is detected, the microprocessor 35 is powered up, an idling frequency, f o is measured and stored and the microprocessor 35 enters its low power rest state. For initial calibration and tuning, a phone off-the-hook signal may be artificially simulated. Then, in one embodiment, a series of eight acceptable
  • a dimensionless quantity, F is calculated by dividing ⁇ f by f o .
  • F ⁇ f/f o .
  • the computed F for the first 5-cent coin is compared with the stored acceptance limits to see if it lies within those limits. Since the first 5-cent coin is an acceptable 5-cent coin, its F value is within the limits.
  • the method of the present invention is not limited to frequency based testing . Neither is the statistical function limited solely to a running average. Further, while the specific example of the flowchart discussed above uses the numbers 8, 16 and 32 in the computation process, other predetermined numbers may be used without departing from the present invention.
  • 16 and 32 were selected because: a) F AVE NEW is fairly well determined after eight coins have been accepted; b) F AVE NEW becomes heavily weighted after 32 coins have been inserted so that the insertion of additional acceptable coins has little effect; and c) the number 16 is between 8 and 32.
  • the microprocessor 35 is programmed according to the attached printout; however, the operation of the electronic coin testing apparatus 10 will be clear to one skilled in the art from the above discussion.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Coins (AREA)
  • Inspection Of Paper Currency And Valuable Securities (AREA)
  • Small-Scale Networks (AREA)
  • Refuge Islands, Traffic Blockers, Or Guard Fence (AREA)
  • Devices For Checking Fares Or Tickets At Control Points (AREA)
  • Noodles (AREA)
  • Control And Other Processes For Unpacking Of Materials (AREA)
  • Control Of Vending Devices And Auxiliary Devices For Vending Devices (AREA)
PCT/US1985/000369 1984-03-01 1985-03-01 Self-tuning coin recognition system WO1985004037A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
BR8505538A BR8505538A (pt) 1984-03-01 1985-03-01 Sistema auto-regulavel de reconhecimento de moedas
KR1019850700279A KR930006098B1 (ko) 1984-03-01 1985-03-01 절전형 코인 경로 게이트 장치
JP60501328A JPH0727585B2 (ja) 1984-03-01 1985-03-01 自己同調硬貨認識装置
KR1019850700280A KR930007271B1 (ko) 1984-03-01 1985-03-01 주화검사 장치 및 그 작동방법
DK502785A DK502785A (da) 1984-03-01 1985-10-31 Selvafstemmende moentgenkendelsesapparat

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58525384A 1984-03-01 1984-03-01
US585,253 1984-03-01

Publications (1)

Publication Number Publication Date
WO1985004037A1 true WO1985004037A1 (en) 1985-09-12

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ID=24340677

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1985/000369 WO1985004037A1 (en) 1984-03-01 1985-03-01 Self-tuning coin recognition system

Country Status (16)

Country Link
EP (1) EP0155126B2 (de)
JP (2) JPH0727585B2 (de)
KR (1) KR930007271B1 (de)
AT (1) ATE61136T1 (de)
AU (1) AU584330B2 (de)
BR (1) BR8505538A (de)
CA (1) CA1228921A (de)
DE (1) DE3581817D1 (de)
DK (1) DK502785A (de)
ES (1) ES8700886A1 (de)
GR (1) GR850518B (de)
HK (1) HK36396A (de)
IE (1) IE56794B1 (de)
MX (1) MX160403A (de)
WO (1) WO1985004037A1 (de)
ZA (1) ZA851248B (de)

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FR2609197A1 (fr) * 1986-12-29 1988-07-01 Laurel Bank Machine Co Dispositif discriminateur de pieces de monnaie
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US4951799A (en) * 1988-02-10 1990-08-28 Tamura Electric Works, Ltd. Method of correcting coin data and apparatus for inspecting coins
EP0394067A1 (de) * 1989-04-21 1990-10-24 Sanden Corporation Vorrichtung zum Prüfen von Münzen
US5083652A (en) * 1988-08-11 1992-01-28 Kabushiki Kaisha Nippon Conlux Classification accuracy setting device for a coin selector
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GB2238152B (en) * 1989-10-18 1994-07-27 Mars Inc Method and apparatus for validating coins
US5404987A (en) * 1989-10-18 1995-04-11 Mars Incorporated Method and apparatus for validating money
DE4121034C1 (de) * 1991-06-26 1992-09-10 National Rejectors Inc. Gmbh, 2150 Buxtehude, De
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GB2284293B (en) * 1993-11-30 1998-06-03 Mars Inc Article classifying method and apparatus
US5931277A (en) * 1995-05-09 1999-08-03 Mars, Incorporated Money validation system using acceptance criteria
DE69713510T2 (de) * 1996-07-29 2002-10-24 Qvex, Inc. Vorrichtung und verfahren zum prüfen von münzen
GB2341263B (en) 1998-08-14 2002-12-18 Mars Inc Method and apparatus for validating currency
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GB2348729A (en) 1999-04-07 2000-10-11 Mars Inc A money validator reprogrammable using externally recieved data
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GB2199438A (en) * 1986-12-29 1988-07-06 Laurel Bank Machine Co Coin discriminating device
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AU4110285A (en) 1985-09-24
JPS61501349A (ja) 1986-07-03
EP0155126A3 (en) 1987-01-07
EP0155126A2 (de) 1985-09-18
DK502785D0 (da) 1985-10-31
CA1228921A (en) 1987-11-03
KR930007271B1 (ko) 1993-08-04
EP0155126B1 (de) 1991-02-27
HK36396A (en) 1996-03-08
DE3581817D1 (de) 1991-04-04
JPH0785277B2 (ja) 1995-09-13
ZA851248B (en) 1985-11-27
BR8505538A (pt) 1986-02-18
JPH0727585B2 (ja) 1995-03-29
DK502785A (da) 1986-01-02
JPH04211888A (ja) 1992-08-03
ATE61136T1 (de) 1991-03-15
IE56794B1 (en) 1991-12-18
EP0155126B2 (de) 2001-07-11
IE850477L (en) 1985-09-01
MX160403A (es) 1990-02-16
GR850518B (de) 1985-07-01
AU584330B2 (en) 1989-05-25
KR850700280A (ko) 1985-12-26
ES8700886A1 (es) 1986-11-16
ES540860A0 (es) 1986-11-16

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