WO1985000933A1

WO1985000933A1 - Self-driven proportional dc-dc converter with overcurrent protection

Info

Publication number: WO1985000933A1
Application number: PCT/US1984/001296
Authority: WO
Inventors: Richard W. Lawrence
Original assignee: Astec Components, Ltd.
Priority date: 1983-08-11
Filing date: 1984-08-13
Publication date: 1985-02-28
Also published as: EP0153372A1

Abstract

A self-driven DC-DC converter (10) has a primary winding (20) of a power transfer (22) driven by a pair of complementary power transistors (Q1 and Q2). The base of each power transistor (Q1 or Q2) is alternatively driven by an associated base drive winding (40 or 42) of a current transformer (38), each of which develops a base drive current proportional to the primary current. Normally, one of the base drive windings (40 or 42) saturates to turn off its associated transistor (Q1 or Q2), which cause the polarity of the other base drive winding (40 or 42) to reverse and thereby turn on its associated power transistor (Q1 or Q2). An overcurrent protection circuit (70) senses excessive primary current resulting from an overload or short circuit on the secondary side of said power transformer (22) and clamps the voltage of one base drive winding (40 or 42) for a preselected time after its associated base drive winding (40 or 42) saturates to prevent the other base drive winding (40 or 42) from reversing polarity. After the preselected time has expired, the voltage clamp is removed, allowing the other base drive winding (40 or 42) to reverse polarity, enabling normal operation to resume. A second DC-DC converter (102) may be placed on the secondary side of said power transformer (22) to provide enhanced voltage regulation.

Description

Sfi F-PR VEN PROPORTIONAE PC-DC CONVERTER WITH OVERCURRENT PROTECTION The present invention relates generally to DC-DC converters and more particularly to a method and apparatus for protecting switching circuit components such as power transistors within such converters from overcurrent conditions and thus damage due to overheating.

Various types of known DC-DC converters can provide one or more output voltages derived from an unregulated DC voltage provided by a DC power source. The DC power source conventionally develops the unregulated DC voltage by rectifying a voltage provided by an AC power source. when the output voltages of the DC-DC converter are low power level, well regulated DC voltages, for example 5 volts and 12 volts, the DC-DC converter may find particular usefulness as the power supply for computer circuits. It is well known that computer circuits and their electronic hardware require well regulated DC voltages for proper operation. For example, should the output voltages of the computer's power supply become momentarily unregulated, i.e. producing a voltage whose value is outside of specified operating ranges, data bit errors may be generated within the computer.

A DC-DC converter may also find particular usefulness in other types of devices which have electromechanical components operable from a DC voltage power source. In this class of devices, the DC-DC converter may be able to develope one or more output voltages of high power capability, typically in the range of 30-50 volts, which need not be well regulated but should be current limited to protect the components of the DC-DC converter from potential damage due to

^SUB excessive current demands as when the output of the converter is inadvertently short-circuited. Prior art DC-DC converters have generally been unable to protect, in a simple manner, such DC-DC converter components when a short circuit is seen at the output of the converter.

One such electromechanical device is a printer which has various electromechanical components whose current demands are not steady state but vary as a function of the particular printing function being performed, e.g., the typing of a character. Although the average power consumption by the printer may be relatively low, such printing functions may require very high current pulses for short periods of time. It is forseen that computers and printers will be provided as an integrated system preferably operable from a single power supply, or that a separate printer will be powered by the same power supply that powers a computer. In a DC-DC converter power supply designed to power such a system, a feedback regulating means of some sort would normally be provided to limit power transfer through the power transformer of the power supply during periods of excessive load. The drawback of such power supplies is that if high current pulses are required by an electromechanical load, e.g., during the operation of the printer, such power demands may be excessive, thereby causing the low power DC voltages, which are also generated by the power supply, to momentarily become unregulated, thereby causing a data error in the computer or other device being operated by such low power DC voltages.

The present invention is directed at overcoming the above problems by providing a DC-DC converter that provides a high power substantially unregulated DC voltage, wherein the converter compensates for overcurrent conditions as a predetermined function of the amount of excessive current being demanded at the power supply output and provides a simple means for protecting the converter from output short circuits. This substantially unregulated DC is then used to power the printer or other electromechanical load that is relatively insensitive to voltage regulation. A second DC-DC converter stage may also be fed by this unregulated DC voltage according to the present invention, which functions to generate the well regulated voltages required by the computer or other more sensitive electronic hardware.

According to the present invention, output load overcurrent "protection is added to the primary side of the power transformer of a self-driven proportional DC-DC converter. In operation, the DC-DC converter is current limited by periodically momentarily suspending operation of the switching circuit on the primary side of the DC-DC converter in response to excessive current loads experienced on the secondary side of the DC-DC converter. The frequency of these momentary operational suspensions is a predetermined function of the level of the excessive current. By suspending operation of the power transistors or other power supply switching components, the power which they must dissipate is lessened, thereby protecting them against damage or catastrophic failure due to overheating. The output voltage of the DC-DC converter may then be used to power a printer and also to power a second stage, as mentioned above, such as a second DC-DC power supply, for developing one or more well regulated, low power output voltages usable by a computer, or the like. The output voltage regulation of this second stage remains relatively

OM unaffected by variations in the output voltage of the DC-DC converter first stage, so long as the overcurrent protection mechanism described above continues to allow some voltage to be applied to the input to the second stage DC-DC converter, e.g. where a complete short circuit does not exist.

It is therefore an object of the present invention to provide a novel method and apparatus for providing overcurrent and short circuit protection in a proportional-drive DC-DC converter power supply.

A further object of the present invention is to provide overcurrent protection in a DC-DC converter switching circuit as a function of the degree of excessive current demand. Another object of the present invention is to provide such overcurrent protection without affecting the well regulated, low power DC output voltages.

These and other objects, advantages and features of the present invention will become more apparent from the following specification when studied in conjunction with the drawings, wherein:

FIG. 1A illustrates a self-driven proportional DC-DC converter power supply;

FIG. IB is a schematic diagram of a circuit which provides overcurrent protection of the DC-DC converter of FIG. 1A according to the present invention;

FIG. 2 illustrates two modes of operation of the DC-DC converter illustrated in FIG. 1; and

FIG. 3 illustrates an overall functional block diagram of a two stage DC-DC power supply utilizing the overcurrent protection circuit of the present invention.

Generally, a self-driven proportional DC-DC converter includes a pair of complementary power transistors which alternately turn on to push or pull current through the primary winding of a power transformer. The base of each power transistor, when on, is driven by current proportional to the current through the primary winding. During normal operation, the voltage at the node common to the primary winding of the power transformer and each of the power transistors is a square wave voltage having a peak to peak amplitude determined by the differential DC voltage applied to the converter.

In the power transformer, excessive current demand due to a short circuit or overload on the output of such converter will be reflected back through the primary winding and hence to the proportional current driven base drive windings of the power transistors. Should the collector current though each of the power transistors exceed a predetermined maximum level, these power transistors may burn up.

The overcurrent protection circuit of the present invention clamps the voltage at the base of one of the power transistors when a high output current demand is detected. By clamping the base voltage for a predetermined time, the normal, alternate on-off operation of each power transistor is stopped for the duration of the predetermined time. By delaying the transition from having one power transistor on to having the other transistors on, the current through the primary winding is limited and hence so is the current delivered to the load. After the predetermined time has expired, the alternate on-off operation of the power transistors is resumed with the cycle continuing until the next overcurrent condition is detected.

The output voltage developed by the DC-DC converter is thus useful for supplying high current pulses and also provide an unregulated source DC

SUBSTITUTE S voltage to a secondary power supply stage for developing low level, well regulated voltages.

Referring now to FIG. 1, there is shown a typical self-driven, proportional DC-DC converter 10. A differential, unregulated DC voltage is applied to converter 10, the high voltage Vn being applied to voltage rail 12 and the low voltage V^ being applied to voltage rail 14. A pair of energy storage capacitors 16 and 18, are connected in series between rails 12 and 14, and operate to store the energy applied to each of voltage lines 12 and 14. During free running operation of DC-DC converter 10, a pair of power transistors Ql and Q2 are alternately turned on to push or pull current through a primary winding 20 of a current transformer 22. For example, when power transistor Ql is on, the direction of current is into the dotted side of primary winding 20 and returns to the node 23 between the series connection of energy storage capacitors 16 and 18. When the direction of current is into the dotted side of primary winding 20, a secondary winding 24 of transformer 22 forward biases a diode 26 and the direction of current is out of the dotted side of secondary winding 24. This current is applied to the inductance of an C filter 28 and charges the capacitor C to provide a "raw" output DC voltage V₀. The output current of secondary winding 24 returns to its center tap 25.

Similarly, when power transistor Q2 is on, the direction of current through primary winding 20 is from the node 23 between energy storage capacitor 16 and 18 and outward from the dotted side of primary winding 20. Secondary winding 24 of current transformer 22 forward biases a second diode 30 so that the direction of current is again into center tap 25 but out of the undotted side of secondary winding 24. -This current is

SUBSTITUTE SHEET also applied to the inductance of LC filter 28 and charges the capacitance C to provide the output voltage

In a preferred embodiment of the present invention, the turns ratio of primary winding 20 to secondary winding 24 (measured end tap to end tap) is selected to be 25:12.

A pair of diodes 32 and 34 clamp the voltage at the dotted side of primary winding 20 to the high voltage VJJ on voltage rail 12 and the low voltage VL on voltage rail 14. Thus, the voltage at the dotted side of primary winding 20 is a square wave whose peak to peak voltage goes substantially "rail to rail" between the high voltage V_H and the low voltage L. Each of power transistors Ql and Q2 are driven by a base drive current which is proportional to the current through primary winding 20 and thus their respective collectors. A base drive transformer 36 is provided to apply a base drive current to each of power transistors Ql and Q2 in proportion to the current through primary winding 20. Transformer 36 has a first winding 38 coupled in series with the dotted side of primary winding 20, a second winding 40 coupled to the base of power transistor Ql and a third winding 42 coupled to the base of power transistor Q2. Second and third windings 40 and 42 are arranged with respect to first winding 38 so that current into the dotted side of primary winding 20 drives a current into the base of power transistor Ql whereas a current out of the dotted side of primary winding 20 drives a current into the base of power transistor Q2 through third winding 42. In one embodiment, the dotted side of first winding 38 is coupled to the dotted side of primary winding 20, the dotted side of second winding 40 is disposed away

SUBSTITUTE S SHHEPEPT-p from the base of power transistor Ql, and the dotted side of third winding 42 is coupled to the base of power transistor Q2. In a preferred embodiment of the present invention, the turns ratio of first winding 38 to each of second winding 40 and third winding 42 is 1:5. It should be obvious, however, that the turns ratio is determined by the large signal DC gain factor, or "beta", of power transistors Ql and Q2.

A pair of diodes 44 and 46 have their respective anodes coupled to the emitters of power transistors Ql and Q2. These diodes are provided to raise slightly the emitter voltage of each of power transistors Ql and Q2 to speed the turnoff response time of each of these transistors. The means by which power transistors Ql and Q2 are held off during an output load overcurrent condition is described in detail hereinbelow. The dotted side of second winding 40, the cathode of diode 44 and the collector of power transistor Q2 are coupled at a common node 48. The cathode of diode 46 and the undotted end of third winding 42 are coupled to voltage rail 14. The collector of power transistor Ql is coupled to voltage rail 12.

Referring now also to FIG. 2, there is shown an exemplary waveform of the voltage at node 48. It is seen that this voltage is a square wave which goes substantially "rail to rail" between the high voltage Vg and the low voltage VL. Waveform 48a illustrates the timing of DC-DC converter 10 during a normal mode of operation and preferably has a frequency of at least 20 kHz. This choice of frequency eliminates annoying audio frequency noise that might be created by DC-DC converter 10 if it were operated at some lower frequency. Upon initial power up of DC-DC converter 10,

OM

> each of power transistors Ql and Q2 is off. An initial start up current is generated by means of a resistor 50 which charges a capacitor 52. When capacitor 52 is charged to a voltage sufficient to trigger a diac 54, capacitor 52 discharges through diac 54 to apply a current pulse to the base of power transistor Q2 causing transistor Q2 to turn on in response thereto. When power transistor Q2 turns on, a current is drawn out of the dotted side of primary winding 20 and into the dotted side of first winding 38. This current develops a proportional current out of the dotted side of third winding 42 and into the base of transistor Q2, thereby maintaining transistor Q2 on once the current out of diac 54 goes away. When the voltage across third winding 42 has been present long enough for transformer 36 to saturate, the voltage across third winding 42 collapses, thereby turning off power transistor Q2. The decreasing voltage across third winding 42 turns off power transistor Q2 when it falls to a voltage substantially equal to the voltage at voltage rail 14 plus the forward bias voltage across diode 46. Thus, diode 46 operates to increase the turn off response time of power transistor Q2. When power transistor Q2 goes off, the polarity of first winding 38 and hence second winding 40 reverses thereby elevating the voltage at the base of power transistor Ql above the voltage at node 48. The direction of current is now into the dotted side of primary winding 20 and the proportional base drive current is applied to the base of transistor Ql through second winding 40 of transformer 36. Again, when second winding 40 thereafter saturates, the voltage across it collapses, thereby turning off power transistor Ql. Diode 44 operates to- increase the turn

OMP

SUBSTSTUTE SHEET \ ^~ off response time of power transistor Ql in the same manner as hereinabove described with respect to diode 46. Power transistor Ql turns off when the decreasing voltage across second winding 40 falls to a voltage substantially equal to the voltage of node 48 plus the forward bias voltage across diode 44. As a result, the voltage across third winding 42 reverses polarity to again turn on power transistor Q2. Thus, DC-DC converter 10 operates in a free-running mode once it is started.

A resistor 56 and a diode 58 are coupled in series between the node between resistor 50 and capacitor 52 and node 48. Diode 58 is arranged to become forward biased when the voltage of node 48 goes low so that capacitor 52 is discharged into node 48.

The continuous discharging of capacitor 52 prevents the voltage across capacitor 52 from triggering diac 54 during the free-running mode. Resistor 50, capacitor 52 and diac 54 thus comprise just a starting circuit for DC-DC converter 10. Resistor 56 and diode 58 provide means for inhibiting operation of this starting circuit during the free running operation of DC-DC converter 10.

In parallel with primary winding 20 is a snubber circuit comprising a resistor 60 and a capacitor 61. The snubber circuit filters voltage spikes appearing across primary winding 20 during transitions of the direction of current therethrough. Power transformer 22 also includes a first feedback winding 64 and a feedback resistor 62.

Feedback resistor 62 is coupled between the base of power transistor Ql and the dotted side of feedback winding 64. The other side of feedback winding 64 is coupled to the undotted side of first winding 38 of transformer 36. For very small current loads out of

- OMP secondary winding 24, the current through primary winding 20 is proportionally smaller. However, the primary current through first winding 38 may be insufficient to provide an adequate base drive current to the appropriate one of power transistors Ql and Q2 through second winding 40 and third winding 42, respectively. Therefore, one of power transistors Ql or Q2 may not properly turn on. Feedback winding 64 couples sufficient feedback current to the base of power transistor Ql to drive transistor Ql or Q2 into an on state during times of low current demand.

Although it is clear how transistor Ql is assisted to cycle by means of winding 64, transistor Q2 is also assisted in its operation by winding 64 in the following manner. By assisting the on and off states of power transistor Ql by the feedback current provided by winding 64, the voltage across third winding 42 is increased, which assists in the complementary turn off and turn on of power transistor Q2. Thus, feedback winding 64 and feedback resistor 62 provide an exemplary means for maintaining DC-DC converter 10 in a free running state at very light loads.

According to the present invention, a resistor 68 is positioned in series between node 48 and first winding 38 of transformer 36. Resistor 68 provides means for developing a voltage which is proportional to the current through primary winding 20. To minimize power loss, resistor 68 is a small resistance, e.g. 0.20-0.25 ohms, and has a power rating sufficient to handle the expected maximum values of the primary current. The voltage across resistor 68 is used in the operation of the overcurrent protection circuit shown in FIG. IB, as described hereinbelow. As seen in FIG. 1A, points A and B shown at resistor 68 correspond to similarly marked points in FIG. IB.

SUBSTITU A second feedback winding 66 of power transformer 22 is also provided for connection to the overcurrent protection circuit. The dotted side of feedback winding 66 is coupled to point B and its other side is coupled at a point C. Point C also designates a point common to FIG. 1A and FIG. IB. The overcurrent protection circuit comprises means for providing a signal which clamps the base voltage of power transistor Ql. A point D indicates the point common to FIG. 1A and IB wherein said clamping signal appears. Referring now to FIG. IB, there is shown an overcurrent protection circuit 70. Circuit 70 provides a preferred means for practicing the method and apparatus of the present invention. As described above, circuit 70 is shown with external connections A-D for connection to the like referenced connections of DC-DC converter 10 in FIG. 1A. Overcurrent protection circuit 70 is primarily responsive to the voltage across resistor 68. An overcurrent condition, such as a short circuit, will be indicated by the absolute value of the voltage across resistor 68 exceeding a predetermined voltage. Of course, the polarity of the voltage across resistor 68 reverses on each half cycle, depending on whether transistor Ql or transistor Q2 is on.

Circuit 70 includes a timing circuit comprising a resistor 72 and a capacitor 74 coupled in series between points A and B, and therefore in parallel with resistor 68. The voltage across resistor 68 develops a current through resistor 72 which charges capacitor 74. The time constant of the timing circuit is determined by the values of resistor 72 and capacitor 74, and is selected so that when the voltage across resistor 68 is equal to or greater than the preselected voltage, the voltage on capacitor 74, depending on polarity, will turn on one of transistors Q3 or Q4 prior to a next transition in the on-off states of transistors Ql and Q2. As seen in FIG. IB, the emitters of transistors Q3 and Q4 are coupled to the potential at point B. Hence, capacitor 74 develops the base-emitter voltage for each of transistors Q3 and Q4.

When transistor Ql is on, and the voltage across resistor 68 exceeds the predetermined voltage, the voltage drop from points A to B has a positive polarity and after capacitor 74 has been charged, transistor Q3 turns on. When transistor Q3 turns on, its collector current lowers the voltage at the base of a transistor Q5 by means of a voltage divider formed by resistors 76 and 78. The base-emitter junction of transistor Q5 then becomes forward biased to turn on transistor Q5, which in turn elevates the voltage at its collector. The collector voltage of transistor Q5 forward biases a diode 80 and causes a further base current to be coupled through a resistor 82 to the base of transistor Q3. Thus, transistors Q3 and Q5 form a latch wherein transistor Q3 turns on transistor Q5 and transistor Q5 maintains transistor Q3 on. The emitter current for transistor Q5 is provided through a forward biased diode 84, which is coupled at point C to the undotted side of feedback winding 66 in FIG. 1A. The polarity of the voltage across points B and G in FIG. IB is determined by the voltage of feedback winding 66. When diode 84 is forward biased, a capacitor 88 also becomes charged. As described in greater detail below, when second winding saturates, it is clamped for a preselected delay time to zero volts to delay a transition between the turn off of transistor Ql and the turn on of transistor Q2. The preselected delay time is determined by the RC time constant of capacitor

SUBSTITUTE SHEET OMPI 88 and a resistor 86 in as much as capacitor 88 is caused to discharge through transistor Q5 and resistor 86. FIG. 2 at 48b, illustrates a delayed transition between the turning off of transistor Ql and the turning on of transistor Q2. The voltage at the collector of transistor Q5 is applied through resistor 86 to the base of a transistor Q6. When power transistor Ql is on, the voltage at point D (the base of power transistor Ql) is at a higher potential then the voltage at point A (node 48) . Therefore, transistor Q6 remains off. However, when second winding 40 begins to saturate and its voltage collapses, transistor Q6 senses this and turns on. The base voltage of power transistor Ql is thereby clamped to the collector voltage of transistor Q6, such that the voltage at point A and point D is substantially equal. Thus, the voltage across second winding 40 cannot change polarity, but is forced by transistor Q6 to remain at zero volts, keeping the magnetic flux stored within transformer 36. Furthermore, since the voltage across second winding 40 cannot change polarity and there is no consequent change in the polarity of the magnetic flux, the voltage across third winding 42 also cannot change polarity. As described above, the duration of this delay time is preselected and is_. determined by capacitor 88 and resistor 86. Since the voltage across feedback winding 66 has reversed its polarity when transistor Ql turned off, diode 84 becomes reverse biased. However, since transistor Q5 is still on, capacitor 88 discharges a current through the emitter of transistor Q5 which is coupled through resistor 86 to the base of transistor Q6. Thus point D, the base of transistor Ql, remains clamped to the emitter voltage of transistor Q6 while capacitor 88 is discharging. After capacitor 88 has discharged, transistor Q5 turns off thereby allowing transistor Q6 to turn off. When transistor Q6 goes off, the stored flux in transformer 36 is enabled to change polarity, allowing the polarity across second and third windings 40 and 42 to reverse to thereby turn on transistor Q2.

Thus, it is seen that when transistor Ql is on during an overcurrent condition, the voltage across second winding 40, after collapsing during saturation, does not change polarity but is forced by transistor Q6 to remain at zero volts.

When the voltage across resistor 68 is of reverse polarity e.g., when transistor Q2 is on, and is developing a voltage indicative of excessive current in the opposite through primary winding 20, the voltage at the base of transistor Ql is also clamped so that second winding 40 does not change polarity. However, the voltage at the base of transistor Ql is clamped at the time when transistor Q2 turns off when third winding 42 saturates.

Transistor Q4 and a transistor Q7 form a latch as hereinabove described with respect to transistor Q3 and Q5 but are operable when the polarity of the voltage across resistor 68 is reversed. Initially, when each of transistors Q4 and Q7 turn on, a diode 85 becomes forward biased which couples a current from feedback winding 66 to charge a capacitor 90 and to bias the base of a transistor Q8 through a resistor 92. When the voltage across third winding 42 collapses, transistor Q8 then turns on, if there has been an overcurrent detected by transistor Q4, and will clamp the voltage at the base of transistor Ql to store the present polarity of magnetic flux in transformer 36 as hereinabove described. In FIG. 2, at 48c, the delay before the turning on of power transistor Ql after

SUBSTITUTE SHEET power transistor is. turned off is illustrated. The symmetrical nature of overcurrent protection circuit 70 is obvious from a study of FIG. IB. Those circuit elements associated with transistors Q4, Q7 and Q8 function as hereinabove described with reference to the symmetrical circuit elements associated with transistors Q2, Q5 and Q6.

Waveform 48d in FIG. 2 illustrates the operation of the overcurrent protection circuit 70 at maximum detected overcurrent. As can be seen at each transition of either transistor Ql or Q2, the circuit 70 operates to generate an off delay or suspense time as hereinbaove described. Consequently, only a minimum amount of power is coupled to the output of converter 10 when in this operating mode.

The overcurrent protection means of the present invention is useful in a power supply system as illustrated in FIG. 4. DC-DC converter 10 and overcurrent protection circuit 70 may provide an output voltage both to a printer 100 and a further DC-DC converter power supply 102. Since power supply 102 operates from a substantially unregulated input DC voltage, any sudden power surges required by printer 100 will not affect the regulated DC output voltages illustrated in FIG. 4 as being generated by power supply 102. The unregulated DC voltage applied to DC-DC converter 10, may be developed in a conventional manner from a diode bridge 104 cascaded with an LC filter stage 106 at its input and a differential RLC filter stage 108 at its output. AC power may be applied to LC filter stage 106 through a fuse 110. One input of diode bridge 104 may be switched to the center node of the input of differential RLC filter 108 to provide selection between an AC power source at 23Ov and an AC power source at 115v.

SUBSTITUTE SHEET It is of course understood that although the preferred embodiments of the present invention have been illustrated and described, various modifications, alternatives and equivalents thereof will become apparent to those skilled in the art, and, accordingly, the scope of the present invention should be defined only by the appended claims and equivalents thereof.

SUBSTITU

Claims

WHAT IS CLAIMED IS:

1. In a self-driven proportional drive DC-DC converter having a power transformer and a switching circuit to switch a primary current through a primary winding of said power transformer, said switching circuit causing said primary current to alternate between a first polarity and a second polarity opposite said first polarity, an overcurrent protection circuit for limiting the primary current through said primary winding and said switching circuit comprising: means for sensing a level of said primary current above a preselected level; and means responsive to said sensing means for terminating operation of said switching • circuit for a preselected time to delay the transition of said primary current from one of said polarities to the other of said polarities.

2. An overcurrent protection circuit as set forth in Claim 1 wherein said sensing means includes: means for developing a first voltage as a function of the level of said primary current; means for developing a second voltage as a function of said first voltage, said second voltage increasing in time with respect to said first voltage; and latch means responsive to said ^• second voltage for latching when a preselected voltage araplitide of said second voltage is reached.

3. An overcurrent protection circuit as set forth in Claim 2 wherein said second, voltage developing means includes a resistor and a capacitor coupled in series with each other, the RC time constant of said resistor and capacitor being selected so that said second voltage obtains a preselected amplitude within one half cycle time of said switching circuit when said primary current is above said preselected level.

4. An overcurrent protection circuit as set forth in Claim 3 wherein said terminating means includes timing circuit means including a capacitor and a resistor for causing said capacitor to be discharged through said resistor starting at the end of said half cycle, for applying a current for said preselected time to said switching circuit, the operation of said switching circuit being suspended in response to said current.

5. In a self-driven proportional drive DC-DC converter having a power transformer, a first power transistor and a second power transistor, means for alternatingly driving the base of each said power transistor with a base current proportional to a primary current through a primary winding of said power transformer, and means for connecting each transistor to said primary winding such that a primary current having a first polarity is generated in said transformer when said first power transistor is being driven and has turned on and a primary current having a second polarity opposite said first polarity is generated in said transformer when said second power transistor is being driven, said driving means including a base drive transformer having a first winding in series with said primary winding, a second winding coupled to the base of said first transistor and a third winding coupled to the base of said second transistor and wherein a reversal of polarity in said second and third windings causes one of said power transisters to turn off and the other to turn on, an overcurrent protection circuit comprising: means for sensing an absolute value of the level of the primary current greater than a preselected level; means responsive to said sensing means for setting a latch;

SUBSTITUTE SHEE ^OMH means responsive to said latch means for maintaining the voltage at the base of the presently on transistor clamped for a preselected time to prevent each of said second winding and third winding from reversing polarity and for resetting said latch means at the end of said preselected time, such that the polarity of said second winding and said third winding is enabled to reverse after said preselect time has expired.

6. An overcurrent protection circuit as set forth in Claim 5 wherein said means responsive to said sensing means includes an RC timing circuit including a capacitor which is charged by a voltage from said sensing means, the voltage of said capacitor setting said latch means when it becomes greater than a preselected voltage during the on state of one of said power transistors.

7. An overcurrent protection circuit as set forth in Claim 5 wherein said maintaining means includes a second RC timing circuit, including a second capacitor, and a clamp transistor connected across one of said second or third windings, said second capacitor being connected to discharge and couple current the base of said clamp transistor to maintain said clamp transistor conductive for said preselected time.

8. An overcurrent protection circuit as set forth in Claim 7 wherein said clamp transistor goes off and said latch means resets when the voltage across said capacitor falls below a preselected voltage.

9. In a self driven proportional drive DC-DC converter which has a power transformer, a first power transistor and a second power transistor, and means for alternatingly driving the base of each of said power transistor with a base current proportional to a primary current through a primary winding of said primary transformer so that said primary current has a first polarity when said first power transistor is being driven during a first half cycle of said driving means and a second polarity opposite said first polarity when said second power transistor is being driven during a second half cycle of said driving means, said driving means including a base drive transformer having a first winding in series with said primary winding, a second winding coupled to the base of said first transistor and a third winding coupled to the base of said second transistor said base drive transformer saturating to cause each said transistor to change state, an overcurrent protection circuit comprising: means for sensing an absolute value of the level of the primary current greater than a preselected level; means responsive to said sensing means, the voltage of said second winding at the base for clamping of said first transistor when the level of said primary current is greater than the preselected level; and means for maintaining the clamped voltage of said second winding for a preselected time after said first transistor has turned off whereby suspending the operation of said driving circuit to prevent said second transistor from changing state.

10. An overcurrent protection circuit as set forth in Claim 9 wherein said sensing means is operative to sense a level of said primary current during each said half cycle.

11. An overcurrent protection circuit as set forth in Claim 10 wherein said sensing means includes a series resistor-capacitor timing circuit and a resistor in series with said primary winding for developing a first voltage as a function of said primary current, said first voltage being applied to said timing circuit which develops a second voltage as a function thereof, the level of said second voltage indicating an

*m,, . mm._mm. < OMPI ^" overcurrent condition if greater than a preselected level at any time during each half cycle.

12. An overcurrent protection circuit as set forth in Claim 10 wherein said clamping means includes: a first transistor which turns on in response to said second voltage with a first polarity exceeding said preselected level; a second transistor which turns on in response to said second voltage with a second polarity opposite said first polarity exceeding said preselected level, each of said first polaity and said second polarity of said second voltage being commensurate with said first polarity and said second polarity of said primary current; a third transistor which turns on in response to said first transistor turning on to maintain said first transistor on; a fourth transistor which turns on in response to said second transistor turning on to maintain said second transistor on; means for clamping the voltage of said second winding at the base of said first power transistor to the voltage of the collector of said third transistor when said second voltage has said first polarity and for clamping the voltage of said second winding at the base of said first power transistor when said second voltage has said second polarity.

13. A power supply system comprising: rectifying means for rectifying an AC voltage to develop an unregulated DC voltage; a first DC-DC converter responsive to said unregulated DC voltage for developing a high power level DC output voltge, said first converter including a current transformer having a primary winding and a secondary winding, and a switching circuit for switching a primary current through said primary winding with an alternating first polarity and a second polarity; means responsive to said primary current for detecting a level of said current above a preselected level to suspend operation of said switching circuit for a preselected time; and a second DC-DC converter responsive to said high power level DC-DC output for developing a plurality of low power level DC voltages.

SUBSTITUTE SHEI °^MH