WO1984002411A1 - Systeme de regulation d'operations de transfert de donnees - Google Patents

Systeme de regulation d'operations de transfert de donnees Download PDF

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Publication number
WO1984002411A1
WO1984002411A1 PCT/US1983/001915 US8301915W WO8402411A1 WO 1984002411 A1 WO1984002411 A1 WO 1984002411A1 US 8301915 W US8301915 W US 8301915W WO 8402411 A1 WO8402411 A1 WO 8402411A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
peripheral
buffer memory
host computer
unit
Prior art date
Application number
PCT/US1983/001915
Other languages
English (en)
Inventor
Glenn Hotchkin
Jayesh V Sheth
David J Mortensen
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Priority to JP59500263A priority Critical patent/JPH0644259B2/ja
Publication of WO1984002411A1 publication Critical patent/WO1984002411A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements

Definitions

  • This invention is related to systems where data transfers are effectuated between a peripheral terminal unit and a main host computer wherein an intermediate I/O subsystem is used to perform the housekeeping duties of the data transfer.
  • I/O subsystems which are used to relieve the monitoring and housekeeping problems of the main host computer and to assume the burden of controlling a peripheral terminal unit and to monitor control of data transfer operations which occur between the peripheral terminal unit and the main host computer system.
  • peripheral controllers known as data link processors whereby initiating commands from the
  • peripheral-controller which manages the data transferOperations with one or more peripheral units.
  • the main host computer also provides a "data link word" which identifies each task that has been initiated for the peripheral-controller. After the completion of a task, the peripheral-controller will notify the main host system with a result/descriptor word as to the completion, incompletion or problem involved in the particular task.
  • DLP data link processors
  • peripheral-controller which was built of modular components consisting of a common front end control circuit which was of a universal nature for all types of peripheral controllers and which was connected with a peripheral dependent board circuit.
  • the peripheral dependent circuit was particularized to handle the idiosyncrasies of specific peripheral terminal units.
  • the present disclosure likewise uses a peripheral-controller (data link processor) which follows the general pattern of the above described system, in that the peripheral-controller uses a common control circuit or common front end which works in coordination with a peripheral dependent circuit which is particularly suited to handle a specific type of peripheral terminal unit, such as a Tape Control Unit (TCU) which connects to one or more magnetic tape units.
  • TCU Tape Control Unit
  • the present invention involves a data transfer network wherein a peripheral-controller known as a data link processor is used to manage and control data transfer operations between a peripheral such as a magnetic tape unit (or a tape control unit) and the main host computer system, whereby data is transferred rapidly in large blocks, ** such as a block of 256 words.
  • a peripheral-controller known as a data link processor
  • the data link processor provides a RAM buffer memory means for temporary storage of data being transferred between peripheral and host system.
  • the RAM buffer is capable of holding at least six blocks or units of data, each of which consists of 256 words, each word being of 16 bits.
  • a peripheral-controller senses blocks of data stored in its RAM buffer in order to choose routines for data transfer appropriate to the data condition of the RAM buffer.
  • the peripheral-controller makes use of a block counter monitoring system which will inform the peripheral-controller and the main host system of the "numerical block status" of data in the RAM buffer memory means.
  • the present invention discloses a system whereby the common front end (common control) circuit uses routines providing microcode instructions to address registers which access locations in the RAM buffer memory for the insertion of data or the withdrawal of data.
  • O PI two address registers one for addresses of data taken from/to the peripheral unit and one for addresses of data which are to be forwarded from/to the main host computer.
  • a block counter logic circuit receives input from the peripheral address register and the system address register.
  • a flip-flop output to the block counter logic circuit indicates the direction of data flow as being a "Write" (host-to-peripheral) or a "Read” (peripheral-to-Host) .
  • the block counter logic circuit provides two output logic signals which control a block counter. This enables the block counter to be shifted up or shifted down so that the internal signal data indicates the number of blocks of data residing in the RAM buffer memory. Certain parameters may be set to trigger signal output conditions when the amount of data in the RAM buffer memory falls below a certain figure.
  • FIG. 1 illustrates the block counter system of the present disclosure which is used to inform the data transfer system of the status of a buffer memory means.
  • FIG. 2 is a system diagram showing the host computer cooperating with a peripheral-controller in order to control data transfer to and from a peripheral unit.
  • FIG. 3 is a drawing showing an eight bit shift register which can be shifted up or down according to conditions which occur between certain logic signals and clock signals.
  • FIG. 4 is a diagram showing how the block counter logic unit of FIG. 1 is organized to operate during Read or Write operations and the effect of either shifting up or shifting down the shift register.
  • FIG. 5A is a schematic drawing illustrating the significance of each bit-position in the block counter.
  • FIG. 5B is a chart indicating various "shift" relationships of the block counter with regard to "Read” and “Write” operations.
  • a "Read” operation takes data from a peripheral magnetic tape unit and temporarily stores it in a RAM memory buffer for later transfer to the host system.
  • a "Write" operation takes data from the main host system for temporary storage in the RAM buffer memory for subsequent transfer to a selected magnetic tape unit via a TCU or Tape Control Unit.
  • the host system 10 sends the peripheral-controller (data link processor 20t) an I/O descriptor and also descriptor link words.
  • the I/O descriptor specifies the operation to be performed.
  • the descriptor link contains path selection information and identifies the task to be performed, so that when a report is later sent back to the main host system 10, the main host system will be able to recognize what task was involved.
  • the data link processor makes a transition to one of the following message level interface states:
  • this state transition indicates that the data link processor 20 ⁇ is returning a result descriptor immediately without -disconnection from the host computer 10. For example, this transition is used when the DLP detects an error in the I/O descriptor.
  • DISCONNECT This state transition indicates that the Magnetic Tape-Data Link Processor (MT-DLP) cannot accept ( . any more operations at this time and that the I/O descriptor and the descriptor link were received without errors. This state also indicates that data transfers or result descriptor transfers can occur.
  • MT-DLP Magnetic Tape-Data Link Processor
  • the DLP 20t When the operation is completed, the DLP 20t returns a result descriptor indicating the status of the operation in the main host system. If the DLP detects a parity error on the I/O descriptor or the descriptor link, or if the DLP cannot recognize the I/O descriptor it received, then the DLP
  • the data link processor 20 t is a multiple-descriptor data link processor capable of queuing one I/O descriptor for each magnetic tape unit to which it is connected. There are certain descriptors (Test/Cancel; Test/Discontinue; and Test/ID) which are not queued, but which can be accepted at any time by the DLP.
  • Test/Cancel and Test/Discontinue OPs are issued against a single magnetic tape unit in a queue dedicated to that peripheral unit, and require that an I/O descriptor for that particular magnetic tape unit already be present within the DLP. If an I/O descriptor is received and violates this rule, the DLP immediately returns a result descriptor to the host. This result descriptor indicates "descriptor error” and "incorrect state”.
  • the MT-DLP utilizes the following status states (STC) transitions when "disconnected" from the host:
  • the data link processor forms and sends the result descriptor to the host system.
  • This descriptor contains information sent by the tape control unit 50 tc to the DLP in the result status word, and also information generated within the DLP.
  • the result descriptor describes the results of the attempt to execute the operation desired.
  • All communications between the DLP 20 t and the host system 10 are controlled by standard DLP status states as described in the previously referenced patents. These status states enable information to be transferred in an orderly manner.
  • the DLP can be in one of two distinct states: (a) ready to receive a new descriptor, or (b) busy.
  • the DLP can accept, a new I/O descriptor.
  • the DLP is busy performing a previously transferred operation.
  • the DLP receives an I/O descriptor and descriptor link that does not require immediate attention
  • the DLP stores the descriptor in its descriptor queue.
  • the DLP is then able to receive another I/O descriptor from the host system.
  • the host system 10 "Disconnects" from the DLP 20 t after issuing one or more queued I/O descriptors, then the DLP initiates a search of its descriptor queue.
  • the DLP searches its descriptor queue on a rotational basis.
  • the order for search is not disturbed by the receipt of one or more new I/O descriptors, nor by the execution of operations. This means that all queued entries are taken in turn regardless of DLP activity and all units have equal priority.
  • the data buffer 22 (FIG. 1) of the DLP provides storage for six blocks of data which are used in a "cyclic" manner. Each of the six blocks holds a maximum of 512 bytes of data. Data is transferred to or transferred from the host system one block at a time, via the buffer 22, followed by a longitudinal parity word (LPW) . Data is always transferred . in full blocks (512 bytes) except for the final block of data for a particular operation. This last block can be less than the 512 bytes, as may be required by the particular operation.
  • LPF longitudinal parity word
  • logic circuitry is used to feed information to a block counter 34 c which will register the number of blocks of data residing in buffer 22 at any given moment.
  • the counter 34 c can set to trigger a flip-flop 34 e which will signal the common control circuit unit 10 c to start routines necessary to either transfer data- to the host 10 (after reconnecting to the host) or to get data from the host 10 to transfer to the buffer 22; or else the unit 10 c can arrange to connect the DLP 20 ⁇ to the peripheral (as tape control unit 50 tc ) for receipt of data or for transmission of data.
  • the block counter 34 c counts the number of blocks of data received from the host system 10.
  • the data link processor "disconnects" from the host system once the DLP has received six buffers; or it will disconnect upon receipt of the "Terminate" command from the host system (a Terminate indicates the "end” of the Write data for that entire I/O operation) . After disconnecting from the host, the data link processor connects to the peripheral tape control unit (TCU 50 tc ). Once proper
  • the data link processor activates logic which allows the tape control unit 50t c a direct access to the DLP RAM buffer 22 for use in data transfers.
  • the data link processor attempts to "reconnect" to the host system by means of a "poll request" (as long as the host 10 has not “terminated” the operation). Once this reconnection is established, the host transfers additional data to the data link processor. This transfer continues until either the six blocks of RAM buffer memory 22 are again full (a buffer which is in the process of being transferred to the tape control unit is considered full during this procedure), or until the host 10 sends a "Terminate" command.
  • Data transfer operations between the data link processor 20t and the tape control unit 50t c continue simultaneously with the host data transfers occurring between host 10 and DLP 20 t (via the buffer 22). If the data link processor has not successfully reconnected to the host before the DLP has transmitted, for example, three blocks of data to the tape control unit 50 tc , the data link processor sets "emergency request" on the data link interface 20 ⁇ , FIG. 1. If the "emergency request" is not successfully serviced before the DLP has only one block of data remaining for transmission to the tape control unit, the data link processor sets a "Block Error" condition by signal from flip-flop 34 e to circuit 10 c . This is reported to the host system as a "host access error" in the result descriptor.
  • the last block of data for any given I/O operation is transferred to the tape control unit 50 tc directly under micro-code control.
  • the data link processor first attempts to connect to the tape control unit 50
  • the data link processor sets "emergency request” on the data link interface 20 ⁇ . If no connection to the host system is effectuated before all of the six RAM buffers are filled, then the data link processor sets "host access error” in the result descriptor.
  • the data link processor 20t starts to send data to the host system 10 while at the same time continuing to receive data from the tape control unit 50 tc .
  • the data link processor checks whether or not two full blocks of data remain to be transferred to the host. If this is so, the DLP uses a
  • break enable If a "break enable" request is granted, then transmission of the next data buffer to the host continues to occur. If there are less than two full blocks of data in the RAM buffer 22 (or if the "break enable” is refused), the data link processor disconnects from the host and waits for two full blocks of data to be present. If a "break enable" is refused, the data link processor initiates another "poll request" immediately after disconnection.
  • the tape control unit 50 c enters the result phase and sends two words of result status to the data link ' processor 20 t .
  • the DLP then incorporates this information, plus any internal result flags, into the result descriptor which the DLP then sends to the host.
  • the overall system diagram is shown whereby a host computer 10 is connected through an I/O subsystem to a peripheral unit, here, for illustrative purposes, shown as a tape control unit 50 tc .
  • This tape control unit (TCU) is used to manage connection to a plurality of Magnetic Tape Unit (MTU) peripherals.
  • MTU Magnetic Tape Unit
  • the I/O subsystem may consist of a base module which supports one or more peripheral-controllers, in addition to other connection and distribution circuitry such as the distribution control circuit 20 o ⁇ 3 and the data link interface 20J; .
  • the peripheral-controller 20t is shown in modular form as being composed of a common front end circuit 10 c and a peripheral dependent circuit shown, in this case, as being composed of two peripheral dependent boards designated 80p ⁇ and 80p2 «
  • a peripheral unit such as a magnetic tape unit
  • TCU peripheral tape control unit
  • data from the magnetic tape unit be passed through the tape control unit to be read out by the host computer.
  • data is transferred in a bidirectional sense, that is, in two directions at various times in the activities of the network.
  • the key monitoring and control unit is the data link processor 20 t which when initiated by specific commands of the host computer will arrange for the transfer of the desired data in the desired direction.
  • the RAM buffer 22 is used for temporary storage of data being transferred between peripherals and the main host computer.
  • this RAM buffer has the capability of storing at least six "blocks" of data, each block of which consists of 256 words.
  • a block counter logic unit 33 c is used to receive input from two address registers designated as the peripheral address register, P a , and the system address register, S a .
  • the peripheral address register, P a handles addresses required when data is retrieved from the peripheral tape unit or when data is being sent to the peripheral tape unit.
  • the system address register, S a is used when data is being received from the host system into the buffer 22 when data is being sent to the host system from the buffer 22.
  • the address data outputs from P a and S a are fed to the RAM buffer 22 in order to address the desired location in the buffer memory.
  • the block counter logic unit 33 c receives one input designated "P Carry" from the peripheral address register and another input "S Carry” from the system address register, in addition to a Read/Write control signal from read-write flip-flop 33f.
  • the flip-flop 33f is controlled by microcode signals from the peripheral-controller common front end unit 10 c .
  • the block counter logic unit 33 c provides a first logic signal S j and a second logic signal LSg which are fed to OR gates G ⁇ and G Q .
  • the OR gates provide two output signals designated S j _ and Sg which are fed to the block counter 34 c .
  • the output signals S_ and Sg are combined at certain times on occurrence of rising clock signals in order to provide conditions which will make the block counter either "shift up” or "shift down”- or "no shift".
  • FIG. 3 there is seen a schematic drawing which illustrates the use of the block counter 34 c of FIG. 1.
  • FIG. 3 there is seen, schematically, an eight bit shift register which will be affected at selected points in time where the clock signal is in its "rising" state as illustrated by the arrows shown in FIG. 3.
  • FIG. 4 there is seen a chart whereby the block counter logic unit 33 c is organized to show overall operating conditions.
  • the conditions of the S Carry and P Carry during the "Read" condition show that there is a no shift or no change when S Carry and P Carry are the same, that is to say they are both 0 or they are both 1.
  • the block counter 34 c will reflect the situation that when data is being taken out of the magnetic tape unit in order to be fed to RAM buffer 22 ("Read" operation), the block counter will shift up unless at the same time there is data being removed from buffer 22 for transfer to the main
  • the block counter will shift down.
  • the condition of the block counter's numerical status will indicate the "balance" between what data has gone out of and what data has come into the buffer 22.
  • H e (Read * 6 BLKFUL) + (Write * 1 BLKFUL) .
  • FIG. 5A a schematic drawing of the block counter 34 c is shown to indicate that when a "1" resides in a series of bit positions, it is an indication of how many blocks of data reside in the RAM buffer 22 (FIG. 1).
  • Each "block” consists of 256 words (512 bytes of eight bits each).
  • FIG. 5B the chart illustrates that during "Read” operations: (a) As the P Carry increases (data being transferred from peripheral tape to buffer memory 22), the block counter 34 c will “shift up” indicating the buffer is being “loaded”.
  • a flip-flop circuit 34 e (FIG. 1) is “set” and provides a signal to the common front end circuit 10 c which will inform the main system of an "access-error” condition. This signifies that the buffer memory 22 was “overfilled” in that the main host system did not accept data quickly enough.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Communication Control (AREA)

Abstract

Un contrôleur de périphériques à bande magnétique (processeur de transmission de données 20t) est utilisé pour le transfert de données entre un dérouleur de bande magnétique de périphériques (contrôleur de dérouleur 50t) et un ordinateur principal (10). Une mémoire intermédiaire (22) dans le contrôleur de périphériques (20t) est dotée d'une unité de compteur d'état (34c) afin de contrôler la quantité de données en transit qui résident momentanément dans la mémoire intermédiaire (22). L'unité de compteur d'état (34c) envoie des signaux de sorties au contrôleur de périphériques (20t) afin de provoquer une intervention demandant plus de données au dérouleur de bande magnétique de périphérique (50tc) ou de l'ordinateur principal (22), ou d'indiquer que la quantité de données dans la mémoire intermédiaire était chargée avant que l'ordinateur principal réponde pour permettre son acceptation.
PCT/US1983/001915 1982-12-07 1983-12-07 Systeme de regulation d'operations de transfert de donnees WO1984002411A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59500263A JPH0644259B2 (ja) 1982-12-07 1983-12-07 デ−タ転送動作を調整するためのシステム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US44738982A 1982-12-07 1982-12-07

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WO1984002411A1 true WO1984002411A1 (fr) 1984-06-21

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PCT/US1983/001915 WO1984002411A1 (fr) 1982-12-07 1983-12-07 Systeme de regulation d'operations de transfert de donnees

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EP (1) EP0128204A4 (fr)
JP (1) JPH0644259B2 (fr)
CA (1) CA1211573A (fr)
WO (1) WO1984002411A1 (fr)

Cited By (1)

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Publication number Priority date Publication date Assignee Title
EP0176976A2 (fr) * 1984-10-04 1986-04-09 Bull HN Information Systems Inc. Appareil de commande de disque à registre d'adresse partagé

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US4357681A (en) * 1980-05-07 1982-11-02 Burroughs Corporation Line turn circuit for data link
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US4407016A (en) * 1981-02-18 1983-09-27 Intel Corporation Microprocessor providing an interface between a peripheral subsystem and an object-oriented data processor
US4423480A (en) * 1981-03-06 1983-12-27 International Business Machines Corporation Buffered peripheral system with priority queue and preparation for signal transfer in overlapped operations

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US4040037A (en) * 1976-06-01 1977-08-02 International Business Machines Corporation Buffer chaining
US4177515A (en) * 1977-12-23 1979-12-04 Ncr Corporation Interrupt adapter for data processing systems
US4246637A (en) * 1978-06-26 1981-01-20 International Business Machines Corporation Data processor input/output controller
US4357681A (en) * 1980-05-07 1982-11-02 Burroughs Corporation Line turn circuit for data link
US4407016A (en) * 1981-02-18 1983-09-27 Intel Corporation Microprocessor providing an interface between a peripheral subsystem and an object-oriented data processor
US4393445A (en) * 1981-03-06 1983-07-12 International Business Machines Corporation Information-signal recording apparatus employing record volume oriented identification signals
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0176976A2 (fr) * 1984-10-04 1986-04-09 Bull HN Information Systems Inc. Appareil de commande de disque à registre d'adresse partagé
EP0176976A3 (en) * 1984-10-04 1989-01-11 Honeywell Information Systems Inc. Disk controller with shared address register

Also Published As

Publication number Publication date
CA1211573A (fr) 1986-09-16
JPH0644259B2 (ja) 1994-06-08
EP0128204A4 (fr) 1986-10-14
EP0128204A1 (fr) 1984-12-19
JPS59502156A (ja) 1984-12-27

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