WO1983004466A1 - Circuit de tables imprimees a trois dimensions en plans et rattachees orthogonalement - Google Patents

Circuit de tables imprimees a trois dimensions en plans et rattachees orthogonalement Download PDF

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Publication number
WO1983004466A1
WO1983004466A1 PCT/US1982/000776 US8200776W WO8304466A1 WO 1983004466 A1 WO1983004466 A1 WO 1983004466A1 US 8200776 W US8200776 W US 8200776W WO 8304466 A1 WO8304466 A1 WO 8304466A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
mother
board
connectors
cards
Prior art date
Application number
PCT/US1982/000776
Other languages
English (en)
Inventor
Peter Frank Hughes
Original Assignee
Transpath, Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Transpath, Limited filed Critical Transpath, Limited
Priority to PCT/US1982/000776 priority Critical patent/WO1983004466A1/fr
Priority to GB08402267A priority patent/GB2133223B/en
Priority to DE19823249507 priority patent/DE3249507T1/de
Priority to JP57502196A priority patent/JPS59501031A/ja
Priority to CA000409603A priority patent/CA1193350A/fr
Publication of WO1983004466A1 publication Critical patent/WO1983004466A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/14—Mounting supporting structure in casing or on frame or rack
    • H05K7/1438—Back panels or connecting means therefor; Terminals; Coding means to avoid wrong insertion
    • H05K7/1439—Back panel mother boards
    • H05K7/1444—Complex or three-dimensional-arrangements; Stepped or dual mother boards

Definitions

  • This invention pertains to the mechanical arrangement of related multiple electrical circuits. BACKGROUND- ART
  • U.S. patent No. 3,206,643 discloses a quasi-three- 5 dimensional structure in which electronic components are connected between metallic X and Z axis combs and Y axis buses in spaced relation.
  • U.S. patent No. 3,377,515 discloses a two-tier cage for holding a plurality of circuit cards and making connections thereto. A plurality of finger pairs (30) on the cage make contact to each circuit card. The circuit arrangement is two-dimensional and there is no mention of any scheme for connecting the finger pairs, one to another.
  • a three-dimensional mechanical disposition of an electrical circuit having plural inputs and plural outputs The structure is arranged in tiers. It is comprised of circuit-carrying cards disposed on edge between intervening mother-boards. Zero-insertion-force (ZIF) connectors upon the mother-boards accept the circuit-carrying cards, making selected contacts with the circuits thereof. Conductive pins of the ZIF connectors make common point electrical connections through the mother-boards. ZIF connectors of alternate tiers are orthogonally arranged.
  • ZIF Zero-insertion-force
  • the structure eliminates wire connections between tiers.
  • FIG. 1 is a perspective elevation view of a three-tier three-dimensional circuit structure.
  • Fig. 2 is a simplified diagram of the structure of Fig. 1 showing how the connection scheme is implemented.
  • Fig. 3 is an enlarged exploded detail of the three-dimen- sional circuit structure, illustrating the orthogonal aspect.
  • Fig. 4 is a plan view of pin connection intersections.
  • Figs. 5, 6 and 7 are plan views of alternate modes of intersection connections.
  • Fig. 8 is a schematic diagram of a routing type switcher that can be embodied in the three-dimensional circuit structure of this invention.
  • Fig. 4 The essential aspect of the invention is shown in Fig. 4 where the pin connections through a mother-board are shown as black diamond shapes. These are electrically conductive areas that connect plural pins.
  • FIG. 1 An illustrative complete structure is shown in Fig. 1.
  • numeral 1 identifies the top or primary tier of plural circuit cards.
  • numeral 2 identifies a middle or secondary tier of plural circuit cards. Note that these are orthog- nally (at right angles) arranged with respect to the disposition of the primary cards.
  • numeral 3 identifies the lower or tertiary tier of plural circuit cards. These are orthogonally arranged with respect to the disposition of the secondary cards. This results in a parallel arrangement with respect to the primary cards.
  • Mother-board 4 is disposed between the primary and secondary tiers, and mother-board 5 between the secondary and tertiary tiers. These two mother-boards are spaced apart in parallel relation by mechanical support 6, which may also be reproduced at the front and- back sides of these mother-boards for mechanical regidity. This has not been shown in -Fig. 1 for sake of clarity.
  • Atop mother-board 4 are first plural, spaced, parallel- related zero-insertion-force (ZIF) elongated electrical connectors 7, 7 1 , 7", 7 ; for example, eight of them. These each support and make electrical contact to an equal number of printed circuit cards 8, 8', 8", 8 .
  • the circuit cards are supported mechanically by elongated guides 9, 9' , 9", 9 n .
  • a top planar frame-piece 12 is rigidly attached to wall 11, and may be similarly attached to sides at the left and the right as well, for mechanical strength. These sides are not shown for sake of clarity; being of only ministerial significance.
  • the secondary tier 2 is inherently the same as tier 1, save that the whole tier is orthogonally related to tier 1.
  • the several parallel-disposed ZIF connectors 17, - 17 hold the several circuit cards 18, - 18 , which cards are also supported by ZIF connectors 27, - 27 n .
  • the number of circuit cards in the second tier is governed by the requirements of the over-all circuit of the structure.
  • Plural edge connectors 20 are provided.
  • the third, or tertiary, tier 3 is inherently the same as an inverted tier 1.
  • mother-board 5 On the underside of mother-board 5 are located plural, spaced, parallel-related ZIF elongated connectors 23, 23', 23", 23 . These are aligned with the prior series of such connectors 7, - 7 atop mother-board 4. Connectors 23, - 23 each engage and make electrical contact with an equal number of printed circuit cards 28, 28', 28", 28 . These circuit cards are supported mechan ⁇ ically by elongated guides 29, 29', 29", 29 n that are attached to a bottom planar frame-piece 22. The latter is the inverted equivalent of frame-piece 12.
  • circuit-cards 28,- 28 are made to the same plurality of edge connectors 30 as there are circuit cards. These connectors are mounted upon rear vertical wall 31, in individual alignment with each ZIF connector 23, - 23 n .
  • Frame-piece 22 is rigidly attached to wall 31, which is also rigidly attached to mother-board 5.
  • _E may also be used to connect to wall 31, which is also rigidly attached to mother-board 5.
  • 0MP1 be attached to sides at the left and the right as well, for mechanical strength. These sides are not shown, being of only ministerial significance.
  • Each ZIF connector such as 7 in Fig. 3, carries a large number of adjacent, but electrically separate, contacts 33 along both inner vertical surfaces. These mate with contacts upon a circuit card, such as contacts 34 (Fig.1) upon card 8, Each contact 33 has a pin 35 that is mechanically and elect ⁇ rically mutually attached, one to the other; the pin extend- ing through the insulating material of the body of the connector.
  • pins also pass through mother-board in a pattern that is shown at 4 in Fig. 4, at 37 and 37A, for example, for ZIF connector 7.
  • Items 37 and 37A are plated-through holes; that is, the inner white area of each is a hole and the surrounding black area is electroplating within the hole and at a larger area on each side of mother-board 4.
  • Each pin 35 is forced into a hole 37, as in an arbor press, so that there is firm mechanical and electrical contact between the electroplating within the hole and the pin.
  • pins Only certain pins are employed for connecting circuits on one circuit card, as 8, to another circuit on another card, as 18. These are the pins that are pressed into the holes in the diamond-shaped conductive areas 40.
  • the two horizontally related holes are aligned with holes 37 and 37A, and so accept certain of pins 35.
  • the two vertically rel ⁇ ated holes are alig-ned with holes 41 and 41A, and so accept certain pins 39. Accordingly, four pins are connected together electrically from one ZIF connector to the one adjacent to it on the opposite side of a mother-board, giving electrical contact redundancy.
  • connection 50 is relatively long in Fig. 8 because of the normal drafting layout. However, the same connection in Fig. 4 is only a few millimeters (mm) long, from one pin to an adjacent pin in area 40.
  • Fig. 4 there are eight dotted "holes" surrounding conductive area 40A. These holes are absent around other areas, such as 40. This indicates that pins such as some of 35 and 39 are removed from the corresponding ZIF con ⁇ nectors to allow desired working room with respect to the desired pins that enter area 40A, and other areas, such as 40.
  • a suitable bus connects the thus formed conductive plane to ground; as to the frame at 6, 11, 22, etc.
  • Fig. 5 shows an alternate arrangement of the conductive area 40 of Fig. 4.
  • Two different types of ZIF connectors are predicated in Fig. 5, particularly as to having differ- ent spacing between companion rows.
  • the rows of holes identified as 55 are more widely spaced than the orthogonally disposed rows of holes identified as 56.
  • Conductive areas 57, 58, 59 and 60 typically connect rows 55 and 56 in groups of three pins. This permits dual paths to be established, as for switching balanced audio signals or bidirectional streams of .data.
  • Fig. 6 shows another alternate conductive area arrange ⁇ ment.
  • OM connect two pins each, one for each row 55 and 56. This permits four paths to be established.
  • the cross outline depicts an area that is not conductive; but areas 62 are.
  • Fig. 7 shows still a further arrangement.
  • In the four central conductive holes 65 oifepin from each of rows 66 and 67 occupies one hole. Adjacent pins are not removed.
  • a typical electrical application of the circuit struct ⁇ ure of this invention is for a routing switcher.
  • This is a device in which a number of inputs, say 100, can be connect- ed to any of 100 outputs by manipulating a push-button switchboard.
  • the great many rectangular elements 70 are solid-state cross-points; that is, plural transistor dev ⁇ ices that accomplish signal transmission when "on” and blocking signal transmission when “off”.
  • Integrated circuit elements suitable for the gigahertz frequency range are suitable, such as the RCA type CA3127E, which has very low inter-junction capacitances.
  • RCA type CA3127E which has very low inter-junction capacitances.
  • three transistors are used for each cross-point, with an emitter-follower output.
  • the routing switcher is suited for either audio frequency or video frequency signals.
  • the schematic circuit of Fig. 8 details how the elect ⁇ rical paths for switching are arranged.
  • An input 71 to tier 1 enters a cross-point connection 70 at "x". It proceeds therethrough and passes out of tier 1 on conductor 50.
  • Conductor 50 in actuality is conductive area 40 of Fig. 3, as has been previously explained.
  • the connection becomes input 72 in tier 2.
  • the signal output from tier 2 enters input 73 of tier 3, passes to cross-point "x" thereof and out at output terminal 74.
  • the "x" path recited above is the normal path for a signal from input 71. Should this path not be available an alternate path via conductor 76 is available. This carries on through another circuit card 77 of the secondary group to second input 81 of tertiary card group 3, thence to output 74o
  • Card 78 in Fig. 8 represents card 2 of the primary group, with an input at 79. This becomes an output of the primary tier and enters the second input 80 of the secondary tier card 2.
  • the top three cards 8, 8' and 8 n are in primary tier 1 of Fig. 1.
  • Orthogonally related, cards 18, 18' and 18 are in the secondary tier 2 of Fig. 1.
  • cards 28, 28' and 28 having the alignment of the top three cards are in the tertiary tier 3 of Fig. 1. Tracing input 1, this enters the first primary card 8 a.t 71. It progresses to output 40, which is one of the conductive areas 40 shown in Fig. 4. Thence to first sec ⁇ ondary card 18, at point 72. From there it passes through another conductive area 40 to first tertiary card 28, at point 73. The signal exits card 28 at output 74.
  • Fig.1 shows 8 circuit cards in primary tier 1, 10 cards in secondary tier 2, and 8 cards in tertiary tier 3. This
  • BU E is not the only number of cards for the tiers. The number of cards depends upon the ultimate size of the switcher in terms of the number of inputs and outputs thereof.
  • Another set of numbers embraces 10 cards in the primary tier, 19 cards in the secondary tier, and 10 cards in the tertiary tier.
  • the preferred manner of assembling the ZIF connectors is to first insert the individual contacts with the pins thereof in the holes of the mother-board. Then the housing; i.e., the sides and bottom, is assembled with an arbor press and a jig.
  • the transistor cross-points specified for the exemplary routing switcher are unidirectional in signal flow. All signal flow is from an input to an output. Bidirectional signal flow can be obtained in an alter ⁇ nate construction in which tri-state buffer integrated circuits are substituted for the transistor cross-points; such as the 74LS365 hex. 3 state buffer. Also suitable are mechanical relays or silicon controlled rectifiers (SCRs) . Because of the three stage (tier) construction and the very short inter-connections via conductive areas 40, the size of the circuit structure of this invention is about one-fourth as large as conventional equipments of this type. ' This is an important practical advantage.
  • Each of the ZIF connectors is provided with an end latch 21 (Fig.1 ) of insulating material, which hinges open to allow the circuit card to enter the connector and is manually closed over the end of the card to retain it.
  • Fig.1 the several solid-state cross-point integrated circuits 70 are shown as seven in number in each vertical row for the primary and tertiary tiers and six in number for the secondary tier. .
  • one primary card as 7 has nineteen outputs, each one of which becomes an input to a secondary card.
  • the number of "x" point integrated circuits 70 may vary according to the extent of the switching requirements; for instance, ten in each vertical row.
  • a three stage routing switcher has been described to illustrate the circuit structure of this invention. Five, seven, or even nine stage switchers can also be implemented by merely extending the technique that has been taught.
  • connections and circuit structure of this invention are suited- to carrying digital as well as analog signals.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

Structure de circuit tridimensionnelle (1, 2, 3) appropriée à une matrice de commutateur électronique du type à acheminement, (Fig. 8) pour des signaux analogiques ou numériques, dans laquelle des interconnexions par conducteurs internes ne sont pas nécessaires. Plusieurs connecteurs (7-7n, 27-27n, 17-17n, 23-23n) à force d'insertion nulle, disposés parallèlement, sont rattachés orthogonalement aux côtés opposés des plaques-mères (4, 5) qui divisent la structure en plans (1, 2, 3). Des fiches conductrices (dans les zones 40, 57 à 60, 62 et 65) sélectionnées partant des connecteurs sont connectées électriquement pour effectuer les interconnexions nécessaires. Des cartes à circuit imprimé (8-8n, 18/18n, 28-28n) introduites dans les connecteurs (7-7n, 27-27n, 17-17n, 23-23n) à force d'insertion nulle portent un grand nombre de points de croisement (70) à circuit intégré ou équivalent, et sont interconnectés par les fiches conductrices (70) sélectionnées.
PCT/US1982/000776 1982-06-07 1982-06-07 Circuit de tables imprimees a trois dimensions en plans et rattachees orthogonalement WO1983004466A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
PCT/US1982/000776 WO1983004466A1 (fr) 1982-06-07 1982-06-07 Circuit de tables imprimees a trois dimensions en plans et rattachees orthogonalement
GB08402267A GB2133223B (en) 1982-06-07 1982-06-07 Tiered orthogonal related 3-d printed boards circuit
DE19823249507 DE3249507T1 (de) 1982-06-07 1982-06-07 Reihen- oder schichtenweise angeordnete, senkrecht zueinander in Bezug stehende, drei dimensionale gedruckte Plattenschaltung
JP57502196A JPS59501031A (ja) 1982-06-07 1982-06-07 回路構造
CA000409603A CA1193350A (fr) 1982-06-07 1982-08-17 Circuit tridimensionnel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1982/000776 WO1983004466A1 (fr) 1982-06-07 1982-06-07 Circuit de tables imprimees a trois dimensions en plans et rattachees orthogonalement

Publications (1)

Publication Number Publication Date
WO1983004466A1 true WO1983004466A1 (fr) 1983-12-22

Family

ID=22168031

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1982/000776 WO1983004466A1 (fr) 1982-06-07 1982-06-07 Circuit de tables imprimees a trois dimensions en plans et rattachees orthogonalement

Country Status (5)

Country Link
JP (1) JPS59501031A (fr)
CA (1) CA1193350A (fr)
DE (1) DE3249507T1 (fr)
GB (1) GB2133223B (fr)
WO (1) WO1983004466A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0554077A1 (fr) * 1992-01-29 1993-08-04 International Business Machines Corporation Dispositif de montage
EP0574133A2 (fr) * 1992-06-08 1993-12-15 Quickturn Design Systems, Inc. Plaie de raccordement et système d'interconnexion pour interconnecter un grand nombre de signaux
WO2000069233A1 (fr) * 1999-05-05 2000-11-16 Nokia Networks Oy Dispositif, procede et carte de positionnement dans un bati d'un noeud d'interconnexion

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9100403D0 (en) * 1991-01-09 1991-02-20 Plessey Telecomm Orthogonal interconnection
GB2381955B (en) 2001-11-08 2005-06-22 Sun Microsystems Inc Electronic circuits
GB2381953B (en) * 2001-11-08 2004-04-28 Sun Microsystems Inc Rack-mountable systems

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2701346A (en) * 1953-11-05 1955-02-01 Hughes Aircraft Co Connector for circuit cards
US2799837A (en) * 1957-07-16 Connector strip and chassis for interconnecting
US2955236A (en) * 1960-10-04 Printed circuit package
US3206648A (en) * 1961-07-21 1965-09-14 Bunker Ramo Coordinate array structure
US3355722A (en) * 1965-04-20 1967-11-28 Ibm Compact semi-permanent information storage unit
US3660803A (en) * 1969-10-08 1972-05-02 Ncr Co Electrical connectors
US3668476A (en) * 1970-09-11 1972-06-06 Seeburg Corp Self-locking enclosure for electronic circuitry and method of assembling the same
DE2214678A1 (de) * 1972-03-25 1973-09-27 Stocko Metallwarenfab Henkels Steckkartenanordnung zur doppelseitigen kontaktierung mit der steckvorrichtung
US4179724A (en) * 1976-04-02 1979-12-18 Bonhomme F R Cabinets for electrical or electronic equipment
US4220382A (en) * 1978-12-15 1980-09-02 Amp Incorporated Bussing connector

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2799837A (en) * 1957-07-16 Connector strip and chassis for interconnecting
US2955236A (en) * 1960-10-04 Printed circuit package
US2701346A (en) * 1953-11-05 1955-02-01 Hughes Aircraft Co Connector for circuit cards
US3206648A (en) * 1961-07-21 1965-09-14 Bunker Ramo Coordinate array structure
US3355722A (en) * 1965-04-20 1967-11-28 Ibm Compact semi-permanent information storage unit
US3660803A (en) * 1969-10-08 1972-05-02 Ncr Co Electrical connectors
US3668476A (en) * 1970-09-11 1972-06-06 Seeburg Corp Self-locking enclosure for electronic circuitry and method of assembling the same
DE2214678A1 (de) * 1972-03-25 1973-09-27 Stocko Metallwarenfab Henkels Steckkartenanordnung zur doppelseitigen kontaktierung mit der steckvorrichtung
US4179724A (en) * 1976-04-02 1979-12-18 Bonhomme F R Cabinets for electrical or electronic equipment
US4220382A (en) * 1978-12-15 1980-09-02 Amp Incorporated Bussing connector

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0554077A1 (fr) * 1992-01-29 1993-08-04 International Business Machines Corporation Dispositif de montage
US5335146A (en) * 1992-01-29 1994-08-02 International Business Machines Corporation High density packaging for device requiring large numbers of unique signals utilizing orthogonal plugging and zero insertion force connetors
EP0574133A2 (fr) * 1992-06-08 1993-12-15 Quickturn Design Systems, Inc. Plaie de raccordement et système d'interconnexion pour interconnecter un grand nombre de signaux
EP0574133A3 (en) * 1992-06-08 1995-09-20 Quickturn Systems Inc Switching midplane and interconnection sytem for interconnecting large numbers of signals
US5887158A (en) * 1992-06-08 1999-03-23 Quickturn Design Systems, Inc. Switching midplane and interconnecting system for interconnecting large numbers of signals
WO2000069233A1 (fr) * 1999-05-05 2000-11-16 Nokia Networks Oy Dispositif, procede et carte de positionnement dans un bati d'un noeud d'interconnexion

Also Published As

Publication number Publication date
JPH023559B2 (fr) 1990-01-24
JPS59501031A (ja) 1984-06-07
GB8402267D0 (en) 1984-02-29
GB2133223B (en) 1985-10-23
GB2133223A (en) 1984-07-18
CA1193350A (fr) 1985-09-10
DE3249507T1 (de) 1984-09-06

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