Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N17/00—Diagnosis, testing or measuring for television systems or their details
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/02—Details
  • H04J3/14—Monitoring arrangements

Definitions

• the present invention relates to equipment for measuring packet multiplexed digital channels in an analog or digital signal.
• Certain constant time intervals of the signal may randomly include packets at the rate of one packet per time interval.
• Each packet is conventionally constituted by a header including the address of. the respective digital channel and by a data block composed of words having a predetermined number of bits; the numbers of words in the data blocks differ from packet to packet.
• Such a signal can be the video signal of a television channel in which the digital channels are intended for transmitting magazines relating to different services.
• the packets are generally inserted at the line period at least in the active parts of the free lines of the frame synchronization signal, which free lines define time intervals having a constant duration.
• This multiplex signal through the various pieces of equipment of the transmission means between the transmitter connected to the studio of the television channel and for example the television receiver of a subscriber or of a video transmission relay generate certain anomalies. which can result in modifications of the data words or in packet losses which is more annoying.
• the exploitation of multiplex signals therefore requires equipment to control the good reception of the data packets, for example by comparing at the transmitting studio level, the packets transmitted and the packets received through the transmission means. The interpretation of these comparisons will help guide technicians on certain devices that are probably failing in the means of transmission.
• the object of the present invention is therefore to provide equipment for measuring packet multiplexed digital channels. in an analog or digital signal in order to detect in particular the number of packets received from each digital channel through the transmission means during a predetermined measurement time.
• the measuring equipment is characterized in that it comprises, in combination for a respective digital channel, means for detecting the address of the respective digital channel in the signal packets, such as an analog video signal or digital and means for counting the number of received packets included in the respective digital channel in response to the detected addresses of the respective digital channel for a predetermined period, control means for assigning each of the address detection means to the one of the digital channels, and means for displaying said number of packets received after said predetermined duration.
• the measuring equipment can also display for each digital channel selected in the signal after said predetermined cyclical duration:
• the display means comprise a conventional television receiver provided with a scart socket and a known decoder of alphanumeric messages to convert the results of the measurements into characters that can be displayed on the screen of the television receiver.
• These display means thus make it possible to reduce the cost of the control equipment since it does not use specific display means.
• the measurement equipment can control time-sharing different digital channels multiplexed into several analog or digital signals. These signals can be video signals from different TV channels. if we .
• FIG. 1 shows a line of a television signal in which a data packet is included
• - Fig. 2 is a schematic block diagram of the measurement equipment
• - Fig. 3 is a detailed block diagram of a sensor of the measurement equipment relating to a digital channel
• - Fig. 4 is a table of the various parameters measured and calculated by the measuring equipment, which table is displayed on the screen of the television receiver included in the equipment.
• the embodiment of the measurement equipment relates to the reception of digital channels conveying data and multiple packets xed with the image signal in a television channel at standards L.
• the image signal is a video signal comprising 625 lines per image and having a line frequency equal to 15.625 Hz and a frame frequency equal to 50 Hz.
• One line of this video signal is shown in FIG. 1. and represents a constant time interval having a line period T L equal to 64 ⁇ s.
• the start of the line is defined by the mid-amplitude point of the front edge of the line synchronization pulse and, after this point, are in the line suppression signal having a duration of 12 us, the synchronization pulse having a duration of 4.7 ⁇ s and the rear bearing of the line suppression signal having a duration of 5.8 ⁇ s.
• the end of the rear landing delimits the front edge of the active part of the image having a duration of approximately 52 ⁇ s.
• the structure of the data packets and their multiplexing in the image signal according to this preferred embodiment comply with the standards of the French DATA broadcasting system DIDON (registered trademark). The characteristics of this system implemented by the present invention are briefly recalled with reference in particular to the special number of the "Radio-Television" review, December 1980, Paris.
• the data to be transmitted is supplied in the form of sequences of bytes by each of different sources.
• a source can be a data terminal and: particularly a teletext terminal such as the coder of the French system ANTIOPE (registered trademark), or system of Digital Acquisition and Television of Images Organized in Pages of Writings.
• the teletext coder transmits a message or magazine in the form of a series of bytes in a digital voice at a real speed of 6,203,125 bits / s.
• each sequence of bytes is split into BD data blocks.
• An AND header is added to each data block, the whole header and data block constituting a packet P, as shown in FIG. 1.
• the coder of the data broadcasting system receives different digital channels conveying each of the data packets and multiplexes them packet by packet by inserting the packets at the rate of one packet per active part of free line.
• a free line is a line whose active part is not occupied by the image signal, which is generally the case of the lines of the synchronization interval in the frame having the numbers 6 to 22 in the first frame or frame image odd and the numbers 318 to 335 in the second frame or even frame of the image.
• most of the other lines can be occupied by packets which corresponds to full channel use.
• the encoder of the data broadcasting system multiplexes the packets with the video signal, that is to say "modulates" the luminance signal, of the free lines by the packets.
• the first byte B 1 of a packet is always inserted at the start of the active part of a line, 10.5 ⁇ s after the falling edge before the line synchronization pulse
• a packet contains at most 40 bytes, which corresponds to the total occupation of the (40x8) / 6203125 - 52 ⁇ s of the active part of the line.
• the header of each packet comprises according to this embodiment 8 bytes which are, according to their order of transmission:
• a third byte 0 forming a byte synchronization word which is identical for all the packets whatever the digital channel and which makes it possible to find the start of a packet on reception and to reconstruct the following bytes there;
• a byte IC constituting a continuity index which is incremented by 1 modulo 16 for each packet transmitted on the same digital channel and which allows the "reception to detect possible packet losses in a set of sixteen packets transmitted successively on the same digital channel;
• byte F constituting a packet format indicator which indicates the number of data bytes contained in the data block BD of the packet P.
• the last five bytes I 1 , I 2 , I 3 , IC and F of the header constitute the "prefice" part of the packet and each include four useful bits of information then four bits of redundancy.
• the redundancy bits are deduced from the information bits according to the same Hamming code and thus allow reception to correct simple binary errors in the information bits.
• 1 measuring equipment can. receive ten channels simultaneously TV CT 1 to CT 10 and simultaneously control at most twenty digital channels VN 1 to VN 20 .
• the ten television channels CT 1 to CT 1 0 are associated in pairs corresponding to the video channel directly delivered by the control of a television channel and to this same video channel after having passed through one or more video frequency relays.
• the equipment will be able to control the loss or error of information between the digital channels of the same video channel respectively transmitted and as received by a subscriber.
• the control equipment essentially comprises a switching video grid 1, twenty identical sets each formed by a digital channel decoder
• the switching gate 1 receives the ten television channels CT 1 to CT 10 . It completely reproduces the analog video signal of one of the television channels on one or more of its twenty output video channels SV 1 to SV 20 each time the control unit 4 selects, via an addressing bus 40, one or more digital channels multiplexed in this television channel.
• this preliminary selection is obtained by means of a specialized keyboard 50 and of a decoder 51 specific to a particular type of writing characters to be displayed which are contained in the display device 5.
• the operator assigns to each set formed by a digital channel decoder 2 1 to 2 20 and a sensor 3 1 to 3 20 , a digital channel to be controlled from one of the television channels CT 1 to CT 10 .
• the pairs of the addresses of the sets 2 1 to 2 20 and 3 1 to 3 20 and of the corresponding incoming television channels CT 1 to CT 10 are stored in a reprogrammable read-only memory included in the control unit 4 and can be modified by l keyboard 50 during measurement, while retaining the option to resume selection at any time initial .
• the video switching grid 1 can be of the type described in the article by SURJON C., entitled “Large capacity switching grids for television centers", published in the journal Radiodiffusion-Telecommunicationvision, N ° 67, pages 1 to 7, 1981, Paris (FR).
• the control unit 4 comprises a microprocessor of the INTEL 8085 type for example.
• the decoder 2 of a corresponding digital channel VN of an incoming television channel SV selected by the grill is a decoder of the DIDON type which is an integrated circuit manufactured by TEXAS-FRANCE and of which the demodulator 20 and the demultiplexer 21 are respectively SN 93 and TMS 3534 AN circuits.
• the principle will be briefly recalled.
• the demodulator 20 of the decoder 2 receives at its video input 200 the corresponding video signal SV in which is multiplexed, inter alia, the digital data channel VN to be processed.
• the function of the demodulator 20 is to extract the digital data channels from the incoming analog video signal SV and to deliver them in series in digital form to the demultiplexer 21, via a wire 201.
• the demodulator 20 also extracts the online composite synchronization signal and frame which is transmitted to the demultiplexer 21 and to the sensor 3 via a wire 202.
• the demodulator 20 searches for the two bit synchronization bytes B 1 and B 2 in each line of the video signal to deduce therefrom a validation pulse corresponding to the start of a packet found.
• Such packet validation pulses are transmitted to the demultiplexer 21 via a wire 203 and have their slots corresponding to the third byte 0 of each packet found.
• the demultiplexer 21 of the decoder 2 has the function of extracting packets transmitted on the wire 201 the packets of the digital channel VN for which the set of decoder 2 and sensor 3 has been selected.
• an addressing bus 210 of the demultiplexer 21 receives, via a bidirec data bus 41 of the control unit 4 and a programming interface 30 of the sensor 3,1 'address. the digital channel VN to be checked which is stored in a reprogrammable read-only memory of the demultiplexer 21.
• the demultiplexer receives a packet validation pulse on the wire 203, it compares the stored address and the address contained in the word d 'identification I 1 to I 3 of the package.
• the packet belongs to the digital channel to be checked.
• the bytes IC, F and of the data block BD of this packet can be transmitted to the sensor 3 on an 8-wire output bus 211, simultaneously with the delivery of a detection pulse of the packet on an output wire 212. the sensor 3.
• the demultiplexer 31 supplies a byte detection pulse on a wire 213 to the sensor 3 each time that a byte IC, F and of the data block BD of the packet is transmitted on the output bus 211 of the demultiplexer , until the last byte of the BD data block is detected, depending on the format indicator byte F.
• the demultiplexer 21 performs other functions and in particular decodes the continuity index byte IC in order to possibly correct the four bits of this byte according to the tables of the Hamming code which have been previously recorded by programming in the demultiplexer.
• the Hamming correcting circuit included in the demultiplexer 21 can only correct certain predetermined errors. For example when the error relates to two useful bits, the correction is not possible, and the corrector indicates it by the insertion of a bit at state 1 at the last position of least significant bit of the IC byte. Otherwise, a bit at state 0 at the same position indicates that the continuity index byte is valid as regards its coding.
• the IC byte with its error indication bit is transmitted on the bus 211.
• the sensor 3 as shown in FIG. 3 comprises, in addition to the programming interface 30, a time base 31 and a programmable timer 32 which supply all the clock signals necessary for controlling the packets found from the digital channel.
• the time base 31 receives on the wire 202 the pulses of the composite synchronization as well as on a wire 301 a pulse which indicates the start order of a measurement cycle and which is supplied by the control unit 4 via the bus 41 and the interface 30.
• the start of the measurement cycle is determined by the control unit 4 which works on a time-sharing basis with regard to the exchange of information, addresses and commands with the various selected sensors 3 1 to 3 20 .
• the duration of a cycle is normally fixed at a second.
• the time base 31 synchronizes the start order of a cycle indicated by the unit 4 on the wire 301 with the start of the blanking interval which corresponds at line 6 for an odd frame and at line 318 for an odd frame.
• the start of the measurement cycle corresponds to the start of the frame blanking interval which is detected in the composite synchronization signal on wire 202 by the time base 31, which indicates this via a wire 310 to the timer 32
• the timer 32 receives the composite synchronization signal on the wire 202 so that a word representative of the predefined duration of a measurement cycle via the bus 41 of the control unit 4 before receiving the order to start of cycle by time base 31.
• An output 320 of the timer then provides a cycle pulse whose rising edge is synchronous with the cycle start pulse on wire 310 and whose width is equal to the duration of the cycle.
• the cycle pulse is transmitted to the control unit 4 via the interface 30 and the bus 41 which unit will decide the start of a new cycle as a function of its availability relative to the treatments, in the course of information from the other sensors.
• the time base 31 also delivers a line synchronization presence signal on a wire 311 to the unit 4, via the interface 30 and the bus 41, which is in the permanent state 1 as long as a synchronization pulse suitable line is detected by the time base every 64 ⁇ s. If line synchronization is not detected, unit 4 will report that the measurements taken are incorrect.
• sensor 3 The essential functions of sensor 3 are performed by a byte control circuit 33 and a circuit packet control 34.
• Each of these circuits 33, 34 includes two programmable counters, one 330, 340 counting the number of bytes or packets detected during the cycle time, the other 331, 341 counting the number of 'wrong bytes or packets lost and wrong during the cycle time.
• the counters 330, 331, 340 and 341, as well as the programming interface 30 are addressed successively by the control unit 4 via an addressing bus 42 specific to the sensor considered 3.
• the unit 4 controls the resetting of the counters and the writing of memories internal to the timer 32 and the interface 30.
• the timer 32 receives the word representative of the predetermined duration of the cycle while that the interface 30 transmits to the demultiplexer 21 of the decoder 2, via the bus 210, information useful for programming the demultiplexer; this information is transmitted by the unit 4 on its bus 41 before the cycle start order.
• the cycle pulse on the output wire 320 of the timer 32 is applied to the inputs C for triggering counting of the counters 330, 331, 340 and 341 as well as at the interface 30 so that the latter delivers to the control unit 4 an end of cycle signal through the bus 41.
• the control unit 4 After the end of the control cycle, the control unit 4 successively addresses the counters, via the address bus 42 and a read control wire 44 , so that their accounts are processed according to the program of unit 4 and displayed by the device 5 as will be seen below.
• the byte control circuit 33 also includes a two pulse suppression circuit 332 and a parity check circuit 333.
• the pulses on wire 213 which respectively indicate the detections of bytes IC and F and bytes of the data block, and the composite synchronization signal on wire 202 are applied to the input of circuit 332.
• This latter circuit removes the two first pulses indicating the detection of bytes IC and F and restore on an output wire 334 only the pulses indicating the detection of oc headers of the BD data block of each packet found in the digital channel.
• the wire 334 is connected to the clock input H of the byte counter 330 and to an input of the parity check circuit 333.
• the counter 330 thus counts the number of data bytes on the digital channel transmitted during the cycle time.
• All the bytes in the data block of a packet can have a predetermined parity imposed on the transmission, or else each byte has a respective parity which is indicated * e by the state of a parity bit, the seven other bits of the byte constituting the information.
• the parity check circuit 333 is adapted to the parity mode chosen on transmission. It receives the IC, F and data bytes on the output bus 211 of the demultiplexer 21 and checks only for each of the data bytes indicated by the pulses on the wire 334 if the received byte has the corresponding parity.
• the counter 340 receives on its clock input H the pulses delivered by the wire 212 and therefore counts the detected packets of the digital channel and received during the duration of the cycle.
• the packet control circuit 34 also includes a circuit for detecting lost and erroneous packets 342.
• the bytes IC, F of the packet data block of the digital channel on the bus 211 as well as the frame synchronization signal which is delivered on an output wire 312 of the time base 31, are applied to inputs of the circuit 342. Only the first byte of each packet on the bus 211 which normally corresponds to the continuity index IC is used in the circuit 342 The presence of the continuity index byte IC on the bus 211 is signaled by the first pulse applied to the wire 213 following a pulse. applied to wire 212 indicating the detection of a packet. For these reasons, the output wires 212 and 213 of the demultiplexer 21 are connected to two other inputs of the circuit 342.
• the circuit 342 For each packet found by the demultiplexer 21, that is to say with each pulse transmitted on the wire 212, the circuit 342 memorizes the IC byte of this packet and detects the least significant bit of the IC byte on the bus 211. If this bit is at state 1, the transmitted packet is erroneous. Then, in, the case where the least significant bit is in the state "0.” which indicates that the packet has been validated by the demultiplexer 21, the circuit 342 compares the useful bits of. the IC byte of the received packet and the stored IC byte of the previously received packet. If the continuity index IC of the received packet is greater than that of the previously received packet increased by the modulo 16 unit, the difference of these two continuity indices minus the unit is equal to the number of packets lost in the digital channel between the transmission of the two received packets.
• An output wire 343 of the circuit 342 delivers a pulse for each erroneous packet and as many pulses as there are packets lost at the clock input H of the counter 341.
• the counter 341 thus counts the erroneous and lost packets in the digital channel.
• the predetermined duration of the control cycle of each sensor can be chosen independently of those of the other sensors by programming the unit 4 by means of the keyboard 50. But the duration of the cycle can be modified automatically by the unit 4 when , during the last control cycle, one of the counters 330 and 340 has reached its maximum count; this means that all bytes or packets received during the cycle could not be counted. For example, if the cycle duration is initially equal to one second, the unit 4 delivers via the bus 41 to the programmable timer 32 a new cycle duration equal to an integer multiple of the initial duration, ie for example a duration of 20 seconds equal to the frame period.
• the display device 5 also comprises means for viewing the results obtained in each of the sensors 3 1 to 3 20 .
• the display means are in the form of a television receiver 52 fitted with a scart socket 53.
• the display of the results is controlled by the damage unit 4 through the teletext decoder 51 which decodes characters d writing according to the language ANTIOPE.
• the keyboard 50 has 13 keys and issues instructions in particular to match the number of each sensor to a digital channel number included in a video channel, through a 9-wire bus 54 to the decoder 51 and then through a standardized digital channel bidirectional 55 to 19200 bit / s at unit 4, the decoder being transparent to the instructions in this case.
• the unit 4 transmits these results in a form compatible with the ANTIOPE language to the decoder 51 through the digital channel 55, and from there to the receiver 52 through a standard link 57 serving the scart socket 53.
• the ANTIOPE decoder 51 is used in interactive mode, that is to say that this decoder can not only receive information from the unit 4 but also transmit instructions thereto.
• This table is entered in the center of the screen 56 at the frame frequency of a television signal, that is to say 50 times per second. It has 25 rows horizontally, each having 40 elementary locations (or columns) each corresponding to an alphanumeric character. The rows are numbered 0 to 24 from top to bottom. The following abbreviations are permanently entered in row No. 2:
• VIDEO name of the video channel
• NPAQ number of packets received
• NOCT number of bytes received
• TEOC byte error rate
• TPPA packet loss rate
• NPAQ to TPPA can vary from one measurement cycle to another.
• the display In normal operation, the display consists of white or yellow characters, on a black background, except for the name of the video channels which have different colors respectively to facilitate reading.
• the three numbers CR, VIDEO and NVOI do not vary, except in the case of an assignment for a new American channel obtained by means of the keyboard 50.
• the six parameters NPAQ and TPPA are transmitted by the unit 4 to the decoder 51, which translates them for display on the screen 56, at the end of each sensor control cycle.
• the parameters NPAQ, NOCT and PPAQ are the accounts of the packet counters 340, bytes 330 and packet loss 341.
• the parameter TEOC is equal to the ratio: count of the counter of erroneous bytes 331 / NOCT, and the parameter TPPA is equal to the ratio (PPAQ / NPAQ) . These two ratios are calculated by unit 4.
• the unit 4 stores the five parameters NPAQ to TPPA and compares them respectively with those previously stored. If at least one of these parameters is modified, the entire row corresponding to the sensor is rewritten on the screen 56, or according to a preferred embodiment, the only modified parameters are transmitted on the digital channel 55 which allows not to clutter the traffic on this channel 55 and the standard link 57. For each cycle time, predetermined thresholds not to be exceeded are compared with the TEOC and TPPA parameters. For example, for a cycle time equal to one second, if TEOC and TPPA are respectively greater than 10 -4 and 10 -2 , an alarm signal is generated by unit 4.
• This alarm signal is transformed in the decoder 51 on the one hand into a visual alarm signal on the screen and, on the other hand, into an audible alarm signal by means of the loudspeaker 58 of the television receiver 52, for a predetermined period.
• the visual alarm signal results in a flashing of the parameter and a predetermined color change.
• the audible alarm signal is triggered by an audio-frequency signal which is supplied by a low-frequency hoot generator 510 included in the decoder 51, through a low-frequency link 59 connected to the audio circuit 580 of the loudspeaker. 58 of the television receiver.
• alarms can also be controlled by the unit 4, for example when the video signal or the digital channel associated with the sensor is absent.
• the generation of alarms is also planned when the count of one of the counters 330, 331, 340 and 341 of the sensor exceeds its maximum count, which indicates to the operator that the next control cycle has a longer duration. , for example equal to 20 ms.
• the count of one of the counters 330, 331, 340 and 341 of the sensor exceeds its maximum count, which indicates to the operator that the next control cycle has a longer duration. , for example equal to 20 ms.
• the decoder 2 can be replaced by a decoder which decodes digital channels multiplexed into a digital signal, such as a digital video signal.

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• Engineering & Computer Science (AREA)
• Signal Processing (AREA)
• Multimedia (AREA)
• Health & Medical Sciences (AREA)
• Biomedical Technology (AREA)
• General Health & Medical Sciences (AREA)
• Computer Networks & Wireless Communication (AREA)
• Time-Division Multiplex Systems (AREA)
• Data Exchanges In Wide-Area Networks (AREA)
• Television Systems (AREA)
• Arrangements For Transmission Of Measured Signals (AREA)
• Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
• Road Repair (AREA)
• Synchronisation In Digital Transmission Systems (AREA)

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• 1982
  • 1982-03-29 FR FR8205326A patent/FR2524239A1/fr active Granted
• 1983
  • 1983-03-28 ES ES521057A patent/ES8402133A1/es not_active Expired
  • 1983-03-28 CA CA000424662A patent/CA1194589A/fr not_active Expired
  • 1983-03-28 MX MX196760A patent/MX152574A/es unknown
  • 1983-03-29 PT PT76477A patent/PT76477B/pt unknown
  • 1983-03-29 WO PCT/FR1983/000060 patent/WO1983003515A1/fr not_active Ceased
  • 1983-03-29 EP EP83400656A patent/EP0091364B1/fr not_active Expired
  • 1983-03-29 AU AU13740/83A patent/AU558068B2/en not_active Ceased
  • 1983-03-29 DE DE8383400656T patent/DE3366386D1/de not_active Expired
  • 1983-03-29 US US06/567,863 patent/US4630266A/en not_active Expired - Fee Related
  • 1983-03-29 JP JP58501211A patent/JPS59501339A/ja active Pending
  • 1983-03-29 AT AT83400656T patent/ATE22516T1/de not_active IP Right Cessation

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