WO1983000782A1 - Amplitude modulation circuit - Google Patents
Amplitude modulation circuit Download PDFInfo
- Publication number
- WO1983000782A1 WO1983000782A1 PCT/JP1982/000321 JP8200321W WO8300782A1 WO 1983000782 A1 WO1983000782 A1 WO 1983000782A1 JP 8200321 W JP8200321 W JP 8200321W WO 8300782 A1 WO8300782 A1 WO 8300782A1
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- WIPO (PCT)
- Prior art keywords
- differential pair
- circuit
- modulation
- amplitude modulation
- modulation circuit
- Prior art date
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C1/00—Amplitude modulation
- H03C1/36—Amplitude modulation by means of semiconductor device having at least three electrodes
Definitions
- the present invention relates to an amplitude modulation circuit
- radio frequency converters Radio Frequency Converters
- video equipment such as video tape recorders and ordinary television receivers It has a built-in “AM modulator” under an amplitude modulator that amplitude-modulates RF waves (VHF or UHF) of a predetermined channel with a video signal.
- AM modulator an amplitude modulator that amplitude-modulates RF waves (VHF or UHF) of a predetermined channel with a video signal.
- Such an AM modulation circuit has recently been often incorporated into an integrated circuit (hereinafter, referred to as an “IC”).
- the first differential pair and the differential pair are connected to each other.
- an AM modulation circuit suitable for integration into an IC having a second differential pair using one of the transistors to be formed as a common emitter current source Specifically, as a prior art suitable for this kind of IC, a circuit shown in FIG. 1 or FIG. 2 can be given.
- These AM modulation circuits basically consist of a constant current source (Si)
- the modulated input signal is input to the base of one of the transistor pairs ( ⁇ 2) forming the first differential pair having the second differential pair (D2) as an unbalanced load, and Is input to the base of one of the transistors (T3 :) forming the second differential ⁇ (D 2) with the resistor ( Rl ) as an unbalanced load (and each transistor In an AM modulation circuit in which a predetermined DC bias voltage is individually applied to the other ten transistors (Tl) and (T4) of the star pair, the transistors and : 4 )
- the maximum and minimum peak-to-peak values of the modulated wave (Fig. 3) output from the collector (Fig. 3) are A and B, respectively.
- Fig. 4 shows the input / output characteristics (Cl) of this differential amplifier circuit.
- the horizontal axis represents the voltage value (Vi) obtained by subtracting the modulation signal input voltage from the fixed bias applied to the base of the transistor (Tl), and the vertical axis represents the vertical axis.
- Vi voltage value obtained by subtracting the modulation signal input voltage from the fixed bias applied to the base of the transistor (Tl)
- the vertical axis represents the vertical axis.
- I 0) is the current flowing through the constant current source (Si).
- the emitter current of the transistor (Tl) is equal to the collector current
- the collector current is equal to the current flowing through the second differential pair (D2).
- circuit configuration shown in Fig. 1 is selected by selecting a predetermined circuit constant
- the linear region (L) of the input / output characteristics- (Cl) is uniquely determined in the range (0.310 to 0.710 :).
- the upper limit of the modulation rate (M) at which the A / M modulation can be performed within this linear region (L) is naturally determined from the power that is uniquely determined.
- the modulation rate is to be kept above the upper limit with this circuit configuration, it is necessary to use the non-linear regions (SH) and (SL) of the differential amplifier circuit to avoid modulation distortion. You won't get it.
- the modulation center is set to 0.510 and it is attempted to achieve a modulation rate of 75, then 0.12510 ⁇ 0.8
- the present invention is to solve such problems of the prior art, that is, to maintain the suitability for IC conversion as in the prior art, and to set the modulation distortion even if the modulation is set to a high modulation rate.
- the purpose is to provide an AM modulation circuit.
- This invention is characterized by adding a new improvement to the prior art circuit configuration. That is, a first differential pair having a constant current source and a second differential pair having one of the transistors forming the first differential pair as a common emitter current source are provided.
- the AM modulation circuit configured to apply a modulation signal as one of the differential pair inputs and apply a carrier as the other differential pair input, the carrier is used as an input.
- a constant of a ratio corresponding to the current of the constant current source is set.
- OMPI WIPO It features a bypass circuit for passing current. This is J? , The starting point of the differential pair input with the carrier can be raised to near the low end of the linear region of AM modulation, thus achieving high modulation rate AM modulation in the linear region. be able to.
- the AM modulation circuit according to the present invention is preferably implemented as an IC. Rather than combining discrete components, differential pairs can be easily equalized. The characteristics of the transistor can be equalized, and the force ⁇ can be configured to be very high. .
- the bypass circuit has a constant current source.
- the linear characteristics can be stabilized as compared with flowing a constant current in correlation with other circuit parts.
- the AM modulation circuit formed as an IC it is preferable to connect a resistor in series to the constant current source of the bypass circuit, and the carrier is connected via a collector layer of the c- transistor. A can be effectively prevented from leaking.
- Fig. 1 shows AM modulation as a prior art suitable for IC implementation.
- OMPI It is a circuit diagram of a circuit.
- Fig. 2 is a circuit diagram of another AM modulation circuit as a prior art suitable for IC implementation. '
- FIG. 3 is a diagram for explaining an amplitude modulation rate.
- Fig. 4 is a characteristic diagram of the AM modulation circuit shown in Fig. 2.
- FIG. 5 is a circuit diagram of an embodiment of an AM modulation circuit according to the present invention.
- FIG. 6 is an operation characteristic diagram showing the characteristics of the circuit of FIG. 5.
- FIG. 0- FIG. 7 is a circuit diagram of an embodiment of the AM modulation circuit according to the present invention, which is specifically implemented as an IC.
- FIG. 5 shows an embodiment of the AM modulation circuit of the present invention, and the same reference numerals are given to the same components as those in the prior art in FIG. 1 or FIG.
- AM modulation circuit of the present invention also basically Chi I 3 ⁇ 4 including the first differential pair and (Dl) a second differential pair (D 2), the first differential pair and (Dl)
- the collector of the NPN transistor (T2) to be formed is connected to the common power supply line (+ Vc C), and the emitter forms the first differential pair (Di).
- the collector of the transistor (Ti :) forming the first differential pair (Dl) includes two NPN-type transistors forming the second differential pair (D2). (T3), 3 ⁇ 4 a common E Mi jitter that is connected is connected to, this door run-g is te (Ti) is E Mi jitter current source of the second differential pair (D 2) of (T4) You.
- the collector of the transistor (T 3) forming the second differential pair (D 2) is connected to the power supply line (+ Vcc), while the other transistor is connected to the power supply line (+ Vcc).
- the collector of the star (T4) is connected to the power supply line (+ Vcc) via the load resistor (R1).
- the bypass circuit (B) is a series connection of a constant current source (52) and a resistor (2).
- the resistor (R2) is an essential component, and is provided from the viewpoint of IC fabrication.
- Door run-g is te (T3), (T 4), so to scan I Tsu Chi in g at high frequency, door run-g is te of Collector power layer Canon re-A and through the capacity of Li Work
- the constant current (II) flowing through the bypass circuit (B) is supplied from the constant current source (S2).
- the value of the constant current (II) is
- the base of the modulation signal is collected by run-g is te forming the first Sado ⁇ (Dl) (T2), calibration Li A forming a second differential 3 ⁇ 4f (D 2) It is applied as an input to the base of the transistor (T3).
- the base of another transistor (T4) forming the first differential pair (Dl) has a first fixed bias rejecting at the center level of the carrier.
- the source of another transistor (Ti :) forming the second differential pair (D2) has an intermediate level between the peak and peak of the modulated signal.
- a fixed bias of 2 is provided.
- the output is the second differential pair.
- the transistors (Ti) and (T2) forming the first differential pair (Dl) are always on, and the carrier is driven by the second differential pair (Dl).
- OMPI WIPO M max is changed by the force set as above. Therefore, (Ic) is reduced to (Ic-Ii), that is, qualitatively based on the characteristic diagram, the operation start point of the second differential pair is set in the linear region of the AM modulation.
- new modulation rate M ⁇ ma x that substantially rather than size and bulk up to it is Ru Kemah. If the desired modulation index and M (M ⁇ M 'max),
- the current ( ⁇ ,) flowing through the bypass circuit (B), which is a feature of the present invention is determined.
- the circuit shown in Fig. 7 is an IC-based AM modulator specifically designed based on the above guidelines.
- the same reference numerals as in Fig. 5 indicate the same or corresponding ones.
- the base is given a fixed bias.
- the constant current source (S 2) provided in the bypass circuit (B) includes transistors (T 6), (T 7), (T 8), ( ⁇ 9) and a resistor
- the constant current source (S 2) may have the same configuration as the constant current source (S i). 3 ⁇ 4 you, resistance (ri), (r 2) , which is (r 3) is provided, et al or on the creation of the IC resistance.
- Tic is the terminal of the IC, and the modulated wave power is output from here. This output is, for example, a modulated wave with a modulation rate of 75%, which is obtained by modulating a 92.15 MHz carrier generated by an oscillator circuit with a 04.2 MHz video signal. is there.
- the modulated wave is mixed with the audio signal and supplied to the antenna terminal of the TV receiver.
- the AM modulation circuit having such a configuration is used, for example, in data transmission using a telephone line. It can also be built into MODEM.
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- Amplitude Modulation (AREA)
Abstract
An amplitude modulation circuit which has no modulation distortion even at high modulation factors while still maintaining its ability of high integration. In an amplitude modulation circuit having a first differential pair (D1) with a constant-current source (S1) and a second differential pair (D2) using one (T1) of the transistors forming the first differential pair (D1) as a common emitter current source, in which a modulation signal is input to one differential pair (D1) and a carrier is input to the other differential pair (D2), a bypass circuit (B) which passes a constant current in proportion to the current of the source(S1) is connected in parallel to the second differential pair (D2) receiving the carrier, so that the operation start point of the second differential pair (D2) is advantageously increased to the vicinity of the starting end of the low frequency band side of the linear range of the AM modulation. Such an amplitude modulation circuit can be used for an RF converter which constitutes the interface between video equipment and a television receiver.
Description
明 細 Details
発明の名称 Title of invention
振幅変調回路 Amplitude modulation circuit
技術分野 Technical field
この発明は振幅変調回路に関する The present invention relates to an amplitude modulation circuit
背景技術 Background art
たとえば、 ビデオ テー プ レ コ ーダ等の ビデオ機器と 通常のテ レ ビ ジ ョ ン受像機とのィ ン タ 一 フ ェ ー ス をな す R F コ ン ノ ー タ (Rad i o Frequency Convert e r ) には、 所定チ ャ ネ ルの R F波 ( V H F又は U H F ) を ビデオ信号で振幅変調する振幅変調回路 下、 「 A M変調回路」 と い う ) が内蔵されている。 For example, radio frequency converters (Radio Frequency Converters) that interface with video equipment such as video tape recorders and ordinary television receivers It has a built-in “AM modulator” under an amplitude modulator that amplitude-modulates RF waves (VHF or UHF) of a predetermined channel with a video signal.
この よ う な A M変調回路は、 最近では、 集積回路 ( ¾下、 「 I C」 と い う ) に組込まれる こ とが多 く 、 た とえば第 1 差動対と、 こ の差動対を形成する ト ラ ン ジ ス タ の一方を共通のヱ ミ ッ タ 電流源とする第 2 差動対 を備える I C 化に適 した A M変調回路が提案されてい る。 具体的に、 この種 I C 化に適 した先行技術と して 、 第 1 図 も し く は第 2 図に示す回路を あげる こ と がで き る。 Such an AM modulation circuit has recently been often incorporated into an integrated circuit (hereinafter, referred to as an “IC”). For example, the first differential pair and the differential pair are connected to each other. There has been proposed an AM modulation circuit suitable for integration into an IC having a second differential pair using one of the transistors to be formed as a common emitter current source. Specifically, as a prior art suitable for this kind of IC, a circuit shown in FIG. 1 or FIG. 2 can be given.
これらの A M変調回路は、 基本的に、 定電流源(Si) These AM modulation circuits basically consist of a constant current source (Si)
' O PI
を一対の ト ラ ン ジ ス タ (Tl ), (T2:) の共通ェ ミ ッ タ 電 流源とする第 1 差動対 (Dl ) と、 前記 ト ラ ン ジ ス タ 対 の一方 (Tl ) を一対の ト ラ ン ジ ス タ (T3 ),(T4 )の共 通のェ ミ ッ タ 電流源とする第 2 差動対 (D2 ) と で構成 される。 変調入力信号は、 前記第 2 差動対 (D2 ) を不 平衡負荷とする第 1 差動対を形成する ト ラ ン ジ ス タ 対 の一方 (Τ2 ) のベ ー ス に入力され、 キャ リ ア は抵抗 ( Rl )を不平衡負荷とする上記第 2 差動对 (D 2 ) を形成 する一方の ト ラ ン ジ ス タ (T3:) のベース に入力される( そして各 ト ラ ン ジ ス タ 対の他方の十 ラ ン ジ ス タ (Tl ) , (T4 ) には個々 に所定の直流バ イ ア ス電圧が印加さ れる の様な A M変調回路において、 ト ラ ン ジ ス タお:4) のコ レ ク タ か ら と ] 3 出される被変調波 (第 3 図 ) の ピ — ク · ビー ク 値の最大値と最少値をそれぞれ A , B と する と、 変調率 Mは、 '' O PI Differential pair (Dl) using a pair of transistor (Tl) and (T2 :) as a common emitter current source, and one of the transistor pair (Tl) ) a pair of bets run-g is te (T3), is constructed out (second differential pair to common E Mi jitter current source of T 4) (D2). The modulated input signal is input to the base of one of the transistor pairs (の 2) forming the first differential pair having the second differential pair (D2) as an unbalanced load, and Is input to the base of one of the transistors (T3 :) forming the second differential 对 (D 2) with the resistor ( Rl ) as an unbalanced load (and each transistor In an AM modulation circuit in which a predetermined DC bias voltage is individually applied to the other ten transistors (Tl) and (T4) of the star pair, the transistors and : 4 ) The maximum and minimum peak-to-peak values of the modulated wave (Fig. 3) output from the collector (Fig. 3) are A and B, respectively. ,
A B A B
M = X 1 0 0 C^) M = X 1 0 0 C ^)
A + B と表わされる Expressed as A + B
と ころで第 1 図の回路で、 変調率 Mが小さい間は In the circuit of Fig. 1, while the modulation factor M is small,
差動对 (Dl ) と定電流源 (S i ) と で構成される差 The difference between the differential 对 (Dl) and the constant current source (S i)
' OMPI
動増幅回路が リ ニア領域で動作する。 第 4 図に この差 動増幅回路の入出力特性 (Cl ) を示す。 特性図におい て、 横軸は ト ラ ン ジ ス タ (Tl ) のベー ス に印加される 固定バイ ァスか ら変調信号入力電圧を差 し引いた電圧 値 (Vi ) を示 し、 縦軸は ト ラ ン ジ ス タ (Ti ) の コ レ ク タ 電流 ( I ) を示す。 るお、 (I 0 ) は 定電流源 (Si) に流れる電流である。 ま た、 ト ラ ン ジ ス タ (Tl ) の ェ ミ ッ タ 電流はコ レ ク タ 電流と等 し く 、 コ レ ク タ 電流は 第 2 差動対 (D2 ) に流れる電流と等 しい ものとする。 '' OMPI The dynamic amplifier operates in the linear region. Fig. 4 shows the input / output characteristics (Cl) of this differential amplifier circuit. In the characteristic diagram, the horizontal axis represents the voltage value (Vi) obtained by subtracting the modulation signal input voltage from the fixed bias applied to the base of the transistor (Tl), and the vertical axis represents the vertical axis. Indicates the collector current (I) of the transistor (Ti). (I 0) is the current flowing through the constant current source (Si). In addition, the emitter current of the transistor (Tl) is equal to the collector current, and the collector current is equal to the current flowing through the second differential pair (D2). And
所定の回路定数を選んで第 1 図の回路構成とする と If the circuit configuration shown in Fig. 1 is selected by selecting a predetermined circuit constant,
、 入出力特性- (Cl ) の リ ニア領域 ( L ) は一義的に ( 0. 3 10 ~ 0. 7 10 :) の範囲に定ま る。 一義的に定ま る こと力ゝ ら、 変調歪 ¾ く この リ ニア領域 ( L ) 内で A M変調 しう る変調率 ( M ) の上限が自'ずと決まる。 こ こで、 この回路構成のま ま で変調率を上限 上にと ろ う とする と差動増幅回路のノ ン リ ニア 領域 (SH) , (SL) を使わざるを得ず変調歪を避け得ない こと に る。 ち ¾みに、 変調の中心を 0. 5 10 に設定 し、 7 5 の変調率を達成 しょ う とする と、 0. 1 2 5 10 〜 0.8In addition, the linear region (L) of the input / output characteristics- (Cl) is uniquely determined in the range (0.310 to 0.710 :). The upper limit of the modulation rate (M) at which the A / M modulation can be performed within this linear region (L) is naturally determined from the power that is uniquely determined. Here, if the modulation rate is to be kept above the upper limit with this circuit configuration, it is necessary to use the non-linear regions (SH) and (SL) of the differential amplifier circuit to avoid modulation distortion. You won't get it. Incidentally, if the modulation center is set to 0.510 and it is attempted to achieve a modulation rate of 75, then 0.12510 ~ 0.8
7 5 I 0 の範囲が使用 される。 これでは、 明 らかに リ ァ領域 L ( 0. 3 I 0 0. 7 10 :) か らはずれる A range of 75 I 0 is used. This clearly deviates from the rear area L (0.3 I 0 0.710 :).
, OMPI
第 1 図の回路の改善策と して、 第 2 図の様に、 第 1 差動対 (Dl ) を形成する各 ト ラ ン ジ ス タ (Ti ) , (T2 ) のェ ミ ッ タ に各々 帰還抵抗 (r ) , (r ) を 挿入 し、 この 差動増幅回路の リ ニア動作領域を実質的に拡大する こ とが考え られる (第 4 図の特性 (C2 ) )。 しか し、 それ でも 尚変調度を大き く と ]9たい場合、 例えば M = 7 5 , OMPI As a measure to improve the circuit in Fig. 1, as shown in Fig. 2, the emitters of the transistors (Ti) and (T2) forming the first differential pair (Dl) must be each feedback resistor (r), to insert the (r), and the this conceivable to substantially expand the Linear operation region of the differential amplifier circuit (characteristic of FIG. 4 (C 2)). However, if you still want to increase the modulation depth] 9, for example, M = 7 5
に設定する よ う な場合には、 必要 リ ニア領域を確 保する こ とは困難である。 In such a case, it is difficult to secure a necessary linear area.
本発明は、 この よ う な先行技術の持つ課題を解決す る こと、 すなわち先行技術と同 じ く I C化への適性を そのま ま維持 し が ら高変調率に設定 しても変調歪の ない A M変調回路を提供する ことを 目的とする。 The present invention is to solve such problems of the prior art, that is, to maintain the suitability for IC conversion as in the prior art, and to set the modulation distortion even if the modulation is set to a high modulation rate. The purpose is to provide an AM modulation circuit.
発明の開示 Disclosure of the invention
こ の発明は先行技術の έι路構成に新規な改良を加え たこ とを特徵とする。 即ち、 定電流源を備える第 1 差 動対と , この第 1 差動対を形成する ト ラ ン ジ ス タ の一 方を共通のェ ミ ッ タ 電流源とする第 2差動対を備え、 —方の差動対入力と して変調信号を印加 し , 他方の差 動対入力と してキヤ リ ァを印加する よ う に構成 した A M変調回路において、 前記キャ リ アを入力とする差動 対に並列に , 前記定電流源の電流に对 しある比率の定 This invention is characterized by adding a new improvement to the prior art circuit configuration. That is, a first differential pair having a constant current source and a second differential pair having one of the transistors forming the first differential pair as a common emitter current source are provided. In the AM modulation circuit configured to apply a modulation signal as one of the differential pair inputs and apply a carrier as the other differential pair input, the carrier is used as an input. In parallel with the differential pair, a constant of a ratio corresponding to the current of the constant current source is set.
OMPI WIPO
電流を流す側路回路を設けた こ と を特徵と している。 これに よ J?、 キャ リ ア を入力とする差動対の動作開 始点を A M変調の リ ニア領域の低域側始端近傍ま でか さ上げでき、 したがって、 リ ニア領域で高い変調率の A M変調を達成する こと'ができ る。 OMPI WIPO It features a bypass circuit for passing current. This is J? , The starting point of the differential pair input with the carrier can be raised to near the low end of the linear region of AM modulation, thus achieving high modulation rate AM modulation in the linear region. be able to.
そ して、 この発明に係る A M変調回路は I C化され る こ とが好ま しい。 ディ ス ク リ ー ト 部品を結合構成す る よ は容易に差動対を す ト ン ジ ス タ の特性を均 等化でき、 し力 ^ も極めてコ ン ノ、°ク ト に構成でき る。 The AM modulation circuit according to the present invention is preferably implemented as an IC. Rather than combining discrete components, differential pairs can be easily equalized.The characteristics of the transistor can be equalized, and the force ^ can be configured to be very high. .
よ ]?好ま し ぐは、 側路回路に定電流源を備える。 他 の回路部分と相関を も たせて定電流を流す こ と に比べ 、 リ ニア特性を安定化でき る。 Preferably, the bypass circuit has a constant current source. The linear characteristics can be stabilized as compared with flowing a constant current in correlation with other circuit parts.
ま た、 I C 化 した A M変調回路においては前記側路 回路の定電流源に直列に抵抗を接続するのが好ま しい c ト ラ ン ジ ス タ の コ レ ク タ 層を介 してキ ャ リ ア が漏れる のを有効に防止する こ と ができ る。 Further, in the AM modulation circuit formed as an IC, it is preferable to connect a resistor in series to the constant current source of the bypass circuit, and the carrier is connected via a collector layer of the c- transistor. A can be effectively prevented from leaking.
この よ う に して I C 化への適性をそのま ま 維持 し が ら高変調率でも変調歪の い A M変.調回路が実現さ れる o In this way, an A / M modulation circuit with low modulation distortion even at a high modulation rate can be realized while maintaining the suitability for IC conversion as it is.o
図面の簡単な説明 BRIEF DESCRIPTION OF THE FIGURES
第 1 図は I C 化に適 した先行技術と しての A M変調 Fig. 1 shows AM modulation as a prior art suitable for IC implementation.
, OMPI
回路の回路図である , OMPI It is a circuit diagram of a circuit.
第 2 図は I C化に適 した先行技術と しての他の A M 変調回路の回路図である。 ' Fig. 2 is a circuit diagram of another AM modulation circuit as a prior art suitable for IC implementation. '
第 3 図は振幅変調率を説明するための図である。 FIG. 3 is a diagram for explaining an amplitude modulation rate.
第 4 図は第 2 図に示 した A M変調回路の特 性図である Fig. 4 is a characteristic diagram of the AM modulation circuit shown in Fig. 2.
5 図は本発明に係る A M変調回路の一実施例の回 路図である FIG. 5 is a circuit diagram of an embodiment of an AM modulation circuit according to the present invention.
第 6 図は第 5 図の回路の特性を示す動作特性図であ ¾ 0 - 第 7 図は具体的に I C化 した本発明に係る A M変調 回路の実施例の回路図である。 FIG. 6 is an operation characteristic diagram showing the characteristics of the circuit of FIG. 5. FIG. 0- FIG. 7 is a circuit diagram of an embodiment of the AM modulation circuit according to the present invention, which is specifically implemented as an IC.
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
第 5 図は本発明の A M変調回路の一実施例を示すも ので、 第 1 図若 し く は第 2 図の先行技術と 同 じ構成要 素については同 じ参照符号を付 してある。 FIG. 5 shows an embodiment of the AM modulation circuit of the present invention, and the same reference numerals are given to the same components as those in the prior art in FIG. 1 or FIG.
本発明の A M変調回路も、 基本的には、 第 1 の差動 対 (Dl ) と第 2 の差動対 (D 2 ) で構成される ¾わ ち、 第 1 差動対 (Dl ) を形成する N P N型 ト ラ ン ジ ス タ (T2 ) のコ レク タ が共通の電源ラ イ ン (+Vc C )に接 続され , そのェ ミ ッ タ は第 1 差動対 (Di ) を形成する AM modulation circuit of the present invention also basically Chi I ¾ including the first differential pair and (Dl) a second differential pair (D 2), the first differential pair and (Dl) The collector of the NPN transistor (T2) to be formed is connected to the common power supply line (+ Vc C), and the emitter forms the first differential pair (Di). Do
OMPI OMPI
' ' - WIPO
いま一つの N P N型 ト ラ ン ジ ス タ (Ti ) のェ ミ ッ タ と 接続される。 共通接続 したエ ミ ッ タ は定電流 (10 ) を 流す定電流源 (S i ) を介 して接地される。 第 1 差動対 (Dl ) を形成する ト ラ ン ジ ス タ (Ti:) の コ レ ク タ には 、 第 2 差動対 (D2 ) を形成する二つの N P N型 ト ラ ン ジ ス タ (T3 ),(T4 ) の共通に接続 したェ ミ ッ タ が接続 され、 こ の ト ラ ン ジ ス タ (Ti ) が第 2 差動対 (D2 ) の ェ ミ ッ タ 電流源と ¾る。 第 2 差動対 (D 2 ) を形成する ト ラ ン ジ ス タ (T 3 ) の コ レ ク タ は電源ラ イ ン (+Vc c ) に接続される 一方、 いま一つの ト ラ ン ジ ス タ (T4 ) の コ レ ク タ は負荷抵抗 (R1 ) を介 して電源ラ イ ン (+Vcc) に接続される。 ''-WIPO It is connected to another NPN-type transistor (Ti) emitter. The commonly connected emitter is grounded via a constant current source (S i) through which a constant current (10) flows. The collector of the transistor (Ti :) forming the first differential pair (Dl) includes two NPN-type transistors forming the second differential pair (D2). (T3), ¾ a common E Mi jitter that is connected is connected to, this door run-g is te (Ti) is E Mi jitter current source of the second differential pair (D 2) of (T4) You. The collector of the transistor (T 3) forming the second differential pair (D 2) is connected to the power supply line (+ Vcc), while the other transistor is connected to the power supply line (+ Vcc). The collector of the star (T4) is connected to the power supply line (+ Vcc) via the load resistor (R1).
そ して、 第 2 差動対 (D2 ) と並列に、 こ の発明の最 も特铵を ¾す , 定電流 〔11 ) を流す側路回路 ( B :) が 接続される。 側路回路 ( B ) は、 この例では定電流源 (52 ) と抵抗 ( 2 ) の直列接続カ ら ¾ る。 も っと も、 抵抗 (R2 ) は本質的 ¾構成要素で ¾ く 、 I C作成上の 観点か ら設け られる。 ト ラ ン ジ ス タ (T3 ) , (T4 )は高 周波でス ィ ツ チ ン グさせるので、 ト ラ ン ジ ス タ の コ レ ク タ 層の容量を介 してキヤ リ アが リ ー ク する こ とがあThen, in parallel with the second differential pair (D2), a bypass circuit (B :) for flowing a constant current [11], which is the most particular feature of the present invention, is connected. In this example, the bypass circuit (B) is a series connection of a constant current source (52) and a resistor (2). Most of all, the resistor (R2) is an essential component, and is provided from the viewpoint of IC fabrication. Door run-g is te (T3), (T 4), so to scan I Tsu Chi in g at high frequency, door run-g is te of Collector power layer Canon re-A and through the capacity of Li Work
]9、 これを有効に防止するためである ] 9, to prevent this effectively
ΟΜΡΙ ΟΜΡΙ
/ 0 _
側路回路 ( B ) を流れる定電流 (I I ) は定電流源 ( S2 )か ら供給される。 定電流 (I I ) の値は、 定電流源 / 0 _ The constant current (II) flowing through the bypass circuit (B) is supplied from the constant current source (S2). The value of the constant current (II) is
(S i ) の定電流 (10 ) に対 しある比率に設定される。 It is set to a certain ratio to the constant current (10) of (S i).
設定値は、 第 4 図の特性曲線 (Ci ) における リ ニア領 域 ( L ) の低域側の始端近傍に相当する電流値である, ノ ン リ ニア領域 (SL) のと ころの値で も よ く 、 また リ ニァ領域 ( L ) にわずかに入る値で も よい。 この例で は 11= 0.3 10 、 すなわち リ ニア領域 ( L ) の低域側 の始端と丁度等 し く 設定する よ う に している。 The set value is the current value corresponding to the vicinity of the lower end of the linear region (L) in the characteristic curve (Ci) in Fig. 4, that is, the value in the non-linear region (S L ). However, it may be a value slightly in the linear area (L). In this example, 11 = 0.310, that is, it is set so as to be exactly equal to the low frequency side starting end of the linear region (L).
入出力の構成において; 変調信号は第 1 差動对 ·(Dl) を形成する ト ラ ン ジ ス タ (T2 ) のベー ス に、 キャ リ ア は第 2 差動 ¾f (D2 ) を形成する ト ラ ン ジ ス タ (T3 ) の ベー ス に各々 入力と して印加される。 そ して、 第 1 差 動対 (Dl ) を形成するいま一つの ト ラ ン ジ ス タ (T4 ) のベ ー ス にはキ ャ リ ア の中心 レベル に拒当する第 1 の 固定バ イ ア ス が与えられ、 第 2 の差動対 (D2 ) を形成 するいま 一つの ト ラ ン ジ ス タ (Ti :) の ー ス には変調 信号の ピ ー ク · ピ ー ク のほぼ中間 レベルに相当する第 In the configuration of the input and output; the base of the modulation signal is collected by run-g is te forming the first Sado对· (Dl) (T2), calibration Li A forming a second differential ¾f (D 2) It is applied as an input to the base of the transistor (T3). Then, the base of another transistor (T4) forming the first differential pair (Dl) has a first fixed bias rejecting at the center level of the carrier. And the source of another transistor (Ti :) forming the second differential pair (D2) has an intermediate level between the peak and peak of the modulated signal. The equivalent of
2 の固定バイ ア ス が与え られる。 出力は、 第 2 差動対 A fixed bias of 2 is provided. The output is the second differential pair.
(D2 ) を形成する ト ラ ン ジ ス タ (T4 ) のコ レク タ か ら 取 ]? 出される From the collector of the transistor (T4) forming (D2)]?
OMPIOMPI
WIPO ,ν
基本的動作においては、 第 1 差動対 (Dl ) を形成す る ト ラ ン ジ ス タ (Ti ), (T2 ) の^方が常時オ ン して、 キヤ リ ァが , 前記第 2 の固定バイ ァ ス を挾んで上下に 振れる変調信号に よ その電流を変化させる こ とで A M変調される。 これは先行技術と 同様である。 しか し ト ラ ン ジ ス タ (Tl ) に定電流源 ( S 2 ) か ら常に I 1 = 0. 3 10 の電流が供給されているので、 ト ラ ン ジ ス タ (Ti ) の コ レ ク タ 電流が 0. 3 I 0 上と ¾ ら い限 ]) 、 第 2 差動対 (D2 ) を構成する ト ラ ン ジ ス タ (T3 ) , (T4 ) に電流が流れない。 この ことは換言すれば、 第WIPO, ν In the basic operation, the transistors (Ti) and (T2) forming the first differential pair (Dl) are always on, and the carrier is driven by the second differential pair (Dl). AM modulation is performed by changing the current with a modulation signal that swings up and down across a fixed bias. This is similar to the prior art. However, since the transistor (Tl) is always supplied with the current of I 1 = 0.310 from the constant current source (S2), the collector of the transistor (Ti) is The current does not flow through the transistors (T3) and (T4) that make up the second differential pair (D2). This is, in other words,
4 図の特性図における ノ ン リ ニ ァ領域 (SL) では第 2 差動対 (D2 ) には全 く 電流が流れず、 特性と しては、 第 6 図の よ う に 1 = 0. 3 10 と , も との特性カ ー ブ ( C1 )と を 成 した特性 (C3 ) と なる。 In the non-linear region (SL) in the characteristic diagram of Fig. 4, no current flows through the second differential pair (D2), and the characteristic is 1 = 0 as shown in Fig. 6. 310 and the characteristic curve (C3) that formed the original characteristic curve (C1).
この よ う に、 第 4 図の特性図において、 ノ ン リ ニア 領域 (SL) では第 2 差動対 (D2 ) は何等作動 し ¾い 様に第 1 差動対 (Dl ) のバ イ ア ス 及び硕路回路 ( B ) の各定数を設定 しているか ら、 第 4 , 6 図において Vi — I 特性曲線上の 0. 3 I 0 の点 Οか ら、 即ち第 6 図に 示すよ う に v i— i を新座標と考える こ とが出来る。 こ こで vi は ト ラ ン ジ ス タ (Ti ) のぺ ス 位か ら変
0一 調信号が入力される ト ラ ン ジ ス タ (T2 ) のベ ー ス電位 を引いた入力電圧値であ ])、 i は第 2 差動対 (D 2 ) を 形成するいずれか一方の ト ラ ン ジ ス タ に流れる電流で ある Ni will this Yo, second in 4 view of the characteristic diagram, Roh emissions Linear area (SL) In the second differential pair (D 2) Ba Yi of the first differential pair (Dl) is in any way actuated ¾ physician like Since the constants of the grounding circuit and the circuit (B) are set, it can be seen from the point 0 at 0.3 I 0 on the Vi-I characteristic curve in FIGS. 4 and 6, that is, as shown in FIG. Thus, vi-i can be considered as new coordinates. Here, vi changes from the negative position of the transistor (Ti). 0 This is the input voltage value obtained by subtracting the base potential of the transistor (T2) to which the monotone signal is input]], and i is one of the two that forms the second differential pair (D2) Current flowing through the transistor
こ の新座標 v i— i に基づき、 第 1 、 第 2 図に よ る先 行技術においては変調歪を避け得なかった変調率 M = Based on these new coordinates v i- i, the modulation rate M = 1 which could not avoid modulation distortion in the prior art shown in Figs. 1 and 2
7 5 %の A M変調信号を得るために必要と される電流 を試算 してみる。 Calculate the current required to obtain a 75% AM signal.
第 2 差動对 (D2 ) の動作中心を新座標で 0. 2 10 ( 旧座標で 0. 5 I 0 )と し、 X を との動作中心か ら上下に とる電流の大き さ とする。 この と き、 の最大値を IM 最小値を であ らわすと、 lM = C 0. 2 + x ) I o Im = ( 0· 2 — x I o なる電流が リ ニァ領域で確保される ことが必要であ る。 これか ら X を算出する と、 Let the operating center of the second differential 对 (D2) be 0.210 in the new coordinates (0.5 I 0 in the old coordinates), and let X be the magnitude of the current taken up and down from the operating center with and. In this case, if the maximum value of is expressed by the minimum value of IM, then a current of lM = C 0.2 + x) I o Im = (0.2 · xI o) is secured in the linear region. From this, when X is calculated,
IM- Ιπα 2 x I 0 IM- Ιπα 2 x I 0
M = 0. 7 5 M = 0.75
lM+ Im 0. 10 lM + Im 0.10
よ ]?、 x = 0. 1 5 と なる Yo] ?, x = 0.15
従って IM = 0. 3 5 I 0 m. = 0. 0 5 I 0
の範囲で直線性が確保されれば変調歪を防止でき る こと と ¾ る。 リ ニア領域 ( L ) は旧座標 Vi で 0. 3 Therefore IM = 0.35 I0 m. = 0.05 I0 If linearity is ensured in the range, modulation distortion can be prevented. The linear area (L) is 0.3 in the old coordinate Vi.
I Q〜 7 0 10 であ ]?、 新座標 Vi— i では 0 〜 0.410 であるか ら、 M = 7 5 %の変調率であって も全 く 変調 歪が生 じない こ とが判る。 IQ ~ 7010] ?, and the new coordinate Vi-i is 0 ~ 0.410, indicating that no modulation distortion occurs even at a modulation rate of M = 75%.
一般的に考えて、 具体的な設計指針を与えてみ ょ う まず、 第 1 図で示される よ う ¾回路構成を設計する と 、 第 4 図の特性曲線 (Ci ) が得 られる。 通 は、 リ ニ ァ領域 ( L ) の中心 ( 電流値を 〔I c ) とする ) に動作 中心が設定される。 この動作中心か ら リ ニア領域 (L ) の上限界点 (又は下限界点 .) ま での電流値の大き さを ( IL) とすると、 この (IL) も決め られる。 リ ニア領 域 ( L ) で第 2 差動対 (D2 ) に流れる最大電流 (IM) , 最小電流 (Im) は、 IM = C 1 c+I L) In general, let's give specific design guidelines. First, when the circuit configuration is designed as shown in Fig. 1, the characteristic curve (Ci) in Fig. 4 is obtained. Usually, the operation center is set at the center of the linear region (L) (current value is [Ic]). Assuming that the magnitude of the current value from this operation center to the upper limit (or lower limit) in the linear region (L) is (IL), this (IL) is also determined. Linear area maximum current flowing through the second differential pair (D2) with (L) (IM), the minimum current (Im) is, IM = C 1 c + IL )
Im = (I C- I L ) Im = (I C- I L)
と なる。 リ ニア領域 ( L ) でと ) う る変調率 Mの上限 を Mma X と する と、 And When the upper limit of the modulation factor M between) woo Ru Linear region (L) and M ma X,
I — Im ( I c + II - C I c— II ) II I — Im (I c + II-C I c— II) II
M m ― M m ―
IM+Im ( I c + IL )+ ( I c-IL ) I c 電流値の範囲 ( I L )は一定であるか ら、 ( I c ) を どの IM + Im (I c + I L) + (I cI L) I c current value range (IL) is found either constant, which the (I c)
OMPI WIPO
よ う に設定する力 で Mma x がかわる。 したがって、 ( I c )を (I c一 I i ) に减 らす、 す ¾わち特性図に基づい て定性的に言えば第 2 差動対の動作開始点を A M変調 の リ ニァ領域の方へかさ上げする と実質的に大き く る新た 変調率 M^ma x が決ま る。 所望の変調率を M ( M≤ M'max ) とすれば、 OMPI WIPO M max is changed by the force set as above. Therefore, (Ic) is reduced to (Ic-Ii), that is, qualitatively based on the characteristic diagram, the operation start point of the second differential pair is set in the linear region of the AM modulation. new modulation rate M ^ ma x that substantially rather than size and bulk up to it is Ru Kemah. If the desired modulation index and M (M≤ M 'max),
IL IL
M ^ の条件に よ ]?、 この発明の特徵を す側路回路 ( B ) に流す電流 (Ι ι、) が決め られる こと と なる。 According to the condition of M ^], the current (Ιι,) flowing through the bypass circuit (B), which is a feature of the present invention, is determined.
第 7 図に示す回路は、 上の指針に基づいて具体的 に設計 した I C化 した A M変調回路である。 第 5 図と 同一の参照符号は同一ない し相当の も のを示す。 第 1 差動対 (Di ) に接続する定電流源 (Si ) は、 ト ラ ン ジ ス タ (T5 ) , 抵抗 (R3:) よ ]? ])、 ト ラ ン ジ ス タ(T5) のベ ー ス に固定バ イ ア ス が与え られる も のである。 一 方、 前記 した側路回路 ( B ) に設ける定電流源 (S 2 ) は、 ト ラ ン ジ ス タ (T6 ),(T 7 ),(T8 ), (Τ9 ) と抵抗The circuit shown in Fig. 7 is an IC-based AM modulator specifically designed based on the above guidelines. The same reference numerals as in Fig. 5 indicate the same or corresponding ones. A constant current source connected to the first differential pair (Di) (Si), the door run-g is te (T 5), resistance (R3 by :)?]), Door run-g is te (T5) The base is given a fixed bias. On the other hand, the constant current source (S 2) provided in the bypass circuit (B) includes transistors (T 6), (T 7), (T 8), (Τ9) and a resistor
(R4 ) , (R5 ), (I )で形成される 力 レ ン ト 回路 に よって構成される。 もっと も、 共通の電源ラ イ ン ( It consists of a power-rent circuit formed by (R4), (R5), and (I). Even more, the common power line (
+Vc c ) に比較的大き な電圧 ( たとえば + 9 V ) を供
3 給する と き はカ レ ン ト ミ 回路が適するが、 + 5 V 程度な ら定電流源 (S 2 ) を定電流源 (S i ) と 同様 構成 と して も よ い。 ¾お、 抵抗 (r i ) , ( r 2 ) , ( r 3 )は I C の作成上か ら設け られる抵抗である。 ま た、 Ti cは I Cの端子であ j?、 こ こか ら被変調波力 出力される。 こ の出力は、 たと えば、 発振回路で生成された周波 数 9 1. 2 5 MHzのキ ャ リ アを 0 4. 2 MHzの ビデオ信 号で変調 した変調率 7 5 %の被変調波である。 被変調 波は音声信号と 混合されて T V受像機のァ ンテナ端子 に供給される。 + Vcc) to a relatively large voltage (for example, +9 V). When supplying power, a current mitigation circuit is suitable, but if the voltage is about +5 V, the constant current source (S 2) may have the same configuration as the constant current source (S i). ¾ you, resistance (ri), (r 2) , which is (r 3) is provided, et al or on the creation of the IC resistance. Tic is the terminal of the IC, and the modulated wave power is output from here. This output is, for example, a modulated wave with a modulation rate of 75%, which is obtained by modulating a 92.15 MHz carrier generated by an oscillator circuit with a 04.2 MHz video signal. is there. The modulated wave is mixed with the audio signal and supplied to the antenna terminal of the TV receiver.
上述の実施例は、 コ ン バータ に内蔵される A M 変調回路に好適な も のであるけれど も、 この よ う ¾構 成の A M変調回路は、 たとえば、 電話回線を用いるデ —タ 伝送において使用 される MODEM に内蔵される こ と も でき る。 Although the above-described embodiment is suitable for an AM modulation circuit built in a converter, the AM modulation circuit having such a configuration is used, for example, in data transmission using a telephone line. It can also be built into MODEM.
以上の説明において本発明の基本的 ¾実施例につい て説明 したが、 本発明は上記実施例に限定される も の ではな く 、 当業者 ¾ ら添付の請求の範囲内で種々 の檮 成とする こ とができ る In the above description, the basic embodiment of the present invention has been described. However, the present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the appended claims by those skilled in the art. can do
ΟΙ,ίΡΙ WIPO ^ t
ΟΙ, ίΡΙ WIPO ^ t
Claims
1. 定電流源を備える第 1 差動对と、 この差動对を 形成する ト ラ ン ジ ス タ の一方を共通のェ ミ ッ タ 電流源 とする第 2 差動封を備え、 一方の差動対に変調信号を 入力 し , 他方の差動対にキャ リ アを入力する よ う に構 成 した振幅変調回路において、 前記定電流源の電流に 対 しある比率の定電流を流す側铬回路を前記キヤ リ ァ を入力とする差動対に並列 'に接続 した ことを特徴とす る振幅変調回路。 1. A first differential amplifier having a constant current source, and a second differential seal having one of the transistors forming the differential amplifier as a common emitter current source. In an amplitude modulation circuit configured to input a modulation signal to a differential pair and to input a carrier to the other differential pair, a side on which a constant current having a certain ratio to a current of the constant current source flows.振幅 An amplitude modulation circuit, wherein the circuit is connected in parallel with a differential pair having the carrier as an input.
2. 前記振幅変調回路は集積回路に組み込まれる も 2. The amplitude modulation circuit is incorporated in an integrated circuit.
' のである請求の範囲第 1 項記載の振幅変調回路。 The amplitude modulation circuit according to claim 1, wherein:
3. 前記側路面路には定電流葸を含む請求の範囲第 1 項又は第 2 項記載の振幅変調回路。 3. The amplitude modulation circuit according to claim 1, wherein the side road surface includes a constant current 葸.
4. 前記側路回路は、 定電流葸と抵抗との直列接続 か らな る請求の範囲第 3 項記載の振幅変調回路。 4. The amplitude modulation circuit according to claim 3, wherein said bypass circuit is formed of a series connection of a constant current 葸 and a resistor.
5. 前記側路回路の定電流源は、 カ レ ン ト ミ ラ 一回 路か ら ¾る請求の範囲第 3 項又は第 4項記載の振幅変 調回路。
5. The amplitude modulation circuit according to claim 3, wherein the constant current source of the bypass circuit is a current mirror single circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU87669/82A AU8766982A (en) | 1981-08-19 | 1982-08-17 | Amplitude modulation circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56129821A JPS5831601A (en) | 1981-08-19 | 1981-08-19 | Am modulation circuit |
JP56/129821810819 | 1981-08-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1983000782A1 true WO1983000782A1 (en) | 1983-03-03 |
Family
ID=15019049
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1982/000321 WO1983000782A1 (en) | 1981-08-19 | 1982-08-17 | Amplitude modulation circuit |
Country Status (3)
Country | Link |
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JP (1) | JPS5831601A (en) |
KR (1) | KR860000896Y1 (en) |
WO (1) | WO1983000782A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2572564B2 (en) * | 1983-08-22 | 1997-01-16 | 株式会社 エスジー | Electric motor positioning controller |
JP2011228946A (en) * | 2010-04-20 | 2011-11-10 | Sumitomo Electric Ind Ltd | Pulse modulation circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50153854A (en) * | 1974-05-30 | 1975-12-11 |
-
1981
- 1981-08-19 JP JP56129821A patent/JPS5831601A/en active Pending
-
1982
- 1982-08-17 WO PCT/JP1982/000321 patent/WO1983000782A1/en unknown
- 1982-08-17 KR KR2019820006525U patent/KR860000896Y1/en active
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JPS50153854A (en) * | 1974-05-30 | 1975-12-11 |
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JPS5831601A (en) | 1983-02-24 |
KR840001491U (en) | 1984-04-30 |
KR860000896Y1 (en) | 1986-05-14 |
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