KR0154598B1 - Strong input compensation circuit of the tuner - Google Patents

Abstract

The present invention relates to a steel input reinforcement circuit of a tuner, and an object of the present invention is to provide a steel input reinforcement circuit of a tuner capable of obtaining a constant output by increasing the degree of attenuation regardless of the input field strength induced by the antenna. The tuner's strong input reinforcement circuit according to the present invention for reducing the current flowing through the transistor by reducing the AGC voltage when the signal of the strong electric field is induced at the input terminal to increase the impedance of the third diode and at the same time The impedance of the first and second diodes is increased to interrupt the flow of signals between the second capacitor and the third diode, and the signal flowing to ground through the first and third capacitors, the second diode and the third capacitor, When the weak electric field signal is induced at the input terminal, the attenuation effect is increased and the AGC voltage is increased to increase the current flowing through the transistor to attenuate the impedance of the third diode and reduce the impedance of the first and second diodes. The signal flows between the two capacitors and the third diode, and passes through the first diode, the third capacitor, and the second diode and the third capacitor. To block the flowing signals to a base that does not happen that attenuation.

Description

Steel input reinforcement circuit of tuner

1 is a block diagram showing a general double conversion tuner.

2 is a steel input reinforcement circuit diagram of a conventional tuner.

(a) is a detailed circuit diagram.

(b) is an equivalent circuit diagram of (a).

3 is a strong input reinforcement circuit diagram of a tuner according to the present invention.

(a) is a detailed circuit diagram.

(b) is an equivalent circuit diagram of (a).

4 is a graph showing an impedance characteristic curve of attenuation diode.

* Explanation of symbols for main parts of the drawings

D1, D2, D3: diodes C1, C2, C3, C4: capacitors,

R1, R2, R3, R4, R5: Resistor L1: Coil

Tr: Transistor

The present invention relates to a strong input reinforcement circuit of a tuner of the present invention, and more particularly, to a strong input reinforcement circuit of a tuner which obtains a constant output regardless of the strength of a signal input when a high frequency signal of a strong electric field is induced to an antenna.

Referring to the accompanying drawings, a conventional cooler used for a satellite broadcasting receiver, a television, a radio, a cable TV, a VTR, and the like is as follows.

1 is a block diagram illustrating a general double conversion tuner.

First, the RF signal induced by the antenna 1 is input to the strong input reinforcement circuit 3 after the noise signal is removed from the band pass filter 2.

In addition, the RF signal input to the strong input reinforcing circuit (3) is attenuated into a signal of a predetermined level required, amplified by the RF amplifier (4) and input to the first mixer (5).

The RF signal input to the first mixer 5 is mixed with the first local oscillation signal input from the first local oscillator 6 to be converted into a first IF signal and input to the first IF filter 8. do.

The first IF signal input to the first IF filter 8 is amplified by the first IF amplifier 9 after the signal other than the first IF band is removed from the first IF filter 8, and the second mixer 10 is amplified. Is entered.

The first IF signal input to the second mixer 10 is mixed with the second local oscillation signal input from the second local oscillator 11, converted into a second IF signal, and then a second IF amplifier 12 Is entered.

The second IF signal amplified by the second IF amplifier 12 is input to a SAW (surface acoustic wave) filter stage of the set SET.

On the other hand, the first local oscillation signal of the first local oscillator 6 is supplied to a PLL (PHASE-LOCKED LOOP) 7 to be compared with the PLL data of the frequency to be tuned in the set (SET) frequency to be tuned. The second local oscillator 11 oscillates by receiving the AFC (AUTOMATIC FREQUENCY CONTROL) signal supplied from the set, and supplies a second local oscillation signal to the second mixer 10.

Referring to the accompanying drawings the strong input reinforcement circuit of the double conversion tuner made as described above in more detail as follows.

Fig. 2 is a steel input reinforcement circuit diagram of a conventional tuner, in which (a) shows a detailed circuit diagram and (b) shows the registered circuit diagram of (a) diagram above.

First, as shown in (a), one end of the capacitor C1 is connected to an input terminal, and an anode end of the attenuation diode D3 is connected to the other end of the capacitor C2, and a cathode end of the attenuation diode D3 is connected to the input terminal. The output terminal is connected by a capacitor C3.

In addition, one end of the resistor (R1) is connected between the capacitor (C1) and the anode end of the damping diode (D3), the grounded capacitor (C2) is connected to the other end of the resistor (R1), the resistor (R1) ) And the capacitor C2 are connected with an AGC voltage V _AGC terminal.

In addition, a grounded resistor R2 is connected between the attenuation diode D3 and the capacitor C3.

The operation of the strong input reinforcement circuit of the double conversion tuner configured as described above is as follows.

First, when the RF signal of the strong electric field is induced from the antenna 1 and supplied to the strong input reinforcing circuit 3, the set SET lowers the AGC voltage V _AGC , thereby causing the attenuation diode D3 to be lowered. ), The current flowing in the circuit is reduced and the impedance of the attenuation diode D3 is increased.

That is, the attenuation of the RF signal by the attenuation diode D3 is increased so that the attenuation of the output signal with respect to the input signal is large.

On the other hand, when the RF signal of the weak electric field is induced from the antenna 1 and supplied to the strong input reinforcement circuit 3, the set SET increases the AGC voltage V _AGC , thereby causing the attenuation diode D3 to be increased. ) And the current flowing in the) increases and the impedance of the attenuation diode D3 decreases.

That is, there is almost no attenuation of the RF signal by the attenuation diode D3 so that the signal input to the input terminal is transmitted as it is to the output terminal.

Referring to the configuration of an equivalent circuit diagram as shown in the accompanying drawings (b) as described above the steel input reinforcement circuit as follows.

First, it is assumed that the impedances of the AGC bias resistors R1 and R2 shown in (a) are sufficiently large and the impedances of the DC blocking capacitors C1 and C2 are sufficiently low.

When the input signal voltage is V _i , the output signal voltage is V _o , the input impedance is Z _i , the output impedance is Z _o , and the impedance of the attenuation diode is Z ₃ ,

Forward voltage transfer ratio A is

It becomes the same formula as the above formula (1).

Therefore, when the signal of the strong electric field is input to the antenna 1, the value of the impedance Z ₃ of the attenuation diode D3 is increased.

If the input and output impedances Z _i and Z _o are equal,

It becomes an expression similar to the said Formula (2).

Further, when the impedance Z ₃ of the attenuation diode D3 is significantly larger than the input impedance Z _i , that is, Z ₃ > 2.Z _i ,

Expression (3) is the same as the forward voltage transfer ratio A is attenuated to 1 / Z ₃ .

On the other hand, when the signal of the weak electric field is input from the antenna 1, the value of the impedance Z ₃ of the attenuation diode D3 is lowered.

That is, when Z ₃ <Z _{i, the} forward voltage transfer ratio A ≒ 1/2 is obtained and the output signal voltage becomes about 1/2 of the input signal voltage.

However, the conventional steel input reinforcing circuit as described above has a problem that it is difficult to obtain a large attenuation characteristic because the input and output impedance is usually about 50 ~ 75 (Ω).

In addition, there is a limit in lowering the input and output impedance, which has a disadvantage in that the attenuation characteristics are not obtained large.

In addition, due to the physical or electrical properties of the attenuation diode, there is a problem in preventing signal induction at high frequencies.

In addition, the characteristic change of the attenuation diode, that is, the impedance change, is controlled by the amount of current flowing through the attenuation diode, so the strong input reinforcement circuit of the tuner operates when the AGC driving current of the SET is not sufficiently supplied (several tens of mA). Resulted in a problem.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a tuner strong input reinforcement circuit that can obtain a constant output by increasing the degree of attenuation regardless of the input field strength induced by the antenna. have. The steel input reinforcement circuit of the tuner according to the present invention for achieving the above object is connected in series between the first and second capacitors, the third diode and the fourth capacitor from the input terminal to the output terminal, and between the first and second capacitors. An anode terminal of a first diode is connected and an anode end of a second diode connected between the third diode and a fourth capacitor is connected to a cathode end of the first diode and a grounded first terminal is connected between the first and second diodes. A grounded fifth resistor is connected to a contact between the cathode terminal of the third diode and the fourth capacitor, to which a three capacitor is connected, and the cathode terminal of the second diode is connected, to form a common contact, and to form an anode terminal of the first diode. One end of a first resistor is connected at the contact point between the connected first and second capacitors, and a second grounded resistor is connected to the other end of the first resistor, and a third resistor is connected between the first and second resistors. The other end of the third resistor is connected between the power supply terminal and the collector terminal of the transistor, and the first coil connected between the second capacitor and the anode terminal of the third diode is connected to the emitter terminal of the transistor. A fourth resistor for applying the AGC voltage is connected to the base terminal of the transistor,

When a signal of a strong electric field is induced at the input terminal, the AGC voltage is dropped to decrease the current flowing through the transistor, thereby increasing the impedance of the third diode and simultaneously increasing the impedance of the first and second diodes. The signal flow between the capacitor and the third diode is interrupted, the signal flowing to ground is passed through the first diode, the third capacitor, the second diode, and the third capacitor, and a weak electric field signal is induced at the input terminal. In this case, the AGC voltage is increased to increase the current flowing through the transistor, thereby reducing the impedance of the third diode and reducing the impedance of the first and second diodes, thereby reducing the impedance of the signal flowing between the second capacitor and the third diode. Pass the flow and difference the signal flowing through the first diode and the third capacitor and the second diode and the third capacitor Including those which is characterized in that formed.

The steel input reinforcement circuit of the tuner according to the present invention will be described with reference to the accompanying drawings.

In the drawings, the same components as those in the prior art will be denoted by the same reference numerals and the same names.

4 is a steel input reinforcing circuit diagram according to the present invention, (a) shows a detailed circuit diagram and (b) shows an equivalent circuit diagram of the (a) diagram.

First, in the strong input reinforcement circuit of the tuner according to the present invention, the AGC voltage V _AGC is applied to the base terminal of the transistor Tr through the first resistor R1, and the power supply voltage is applied to the collector terminal of the transistor Tr. (b +) is applied and one end of the coil L1 is connected to the emitter end of the transistor Tr.

In addition, the first and second capacitors C1 and C2 are connected in series, and the anode terminal of the third attenuation diode D3 is connected to the second capacitor C2, and the third attenuation diode D3 is connected. The output terminal is connected to the cathode terminal by the fourth capacitor C4.

An anode end of the first attenuation diode D1 is connected between the first and second capacitors C1 and C2, and a cathode end of the second attenuation diode D2 is connected to the cathode end of the first attenuation diode D1. An anode end is connected and the cathode end of the second attenuation diode D2 is connected between the third attenuation diode D3 and the fourth capacitor C4, but has a common contact with the grounded fifth resistor R5. Are connected.

In addition, a grounded third capacitor C3 is connected between the first attenuation diode D1 and the second attenuation diode D2.

In addition, the other end of the coil L1 connected to the emitter terminal of the transistor Tr is connected between the second capacitor C2 and the third attenuation diode D3.

Further, at a contact point where the anode end of the first attenuation diode D1 is connected between the first and second capacitors C1 and C2, one end of the first resistor R1 is connected to form a common contact point. The other end of the first resistor R1 is connected to the grounded second resistor R2, and the other end of the third resistor R3 is connected between the power supply voltage b + and the collector terminal of the transistor Tr.

The operation of the steel input reinforcement circuit of the tuner according to the present invention configured as described above will be described in more detail with reference to a block diagram illustrating the double conversion tuner of FIG. 1.

First, when the RF signal of the strong electric field is induced in the antenna 1 and supplied to the strong input reinforcing circuit 3, the set lowers the AGC voltage V _AGC , which causes the collector and emitter of the transistor Tr. As the voltage applied between them increases, the amount of current flowing through the transistor Tr decreases.

Therefore, the voltage applied to the third attenuation diode D3 decreases and the internal impedance Z ₃ increases.

In addition, while the voltage applied to the anode of the third attenuation diode D3 decreases due to a decrease in the current flowing in the first loop LOOP1, the first and second attenuation diodes D1 and D2 of the second loop LOOP2 are reduced. The voltage on) becomes large.

Therefore, the amount of current flowing through the first and second attenuation diodes D1 and D2 of the second loop LOOP2 increases, so that the internal impedance Z ₁ of the first and second attenuation diodes D1 and D2 is increased. Z ₂ ) decreases.

That is, as shown in the equivalent circuit diagram of FIG. 2 (b), the impedance Z3 of the signal line becomes large and the impedance Z ₁ and Z ₂ bypassed to GROUND decreases while the signal attenuation becomes large. You lose.

On the other hand, when the signal of the weak electric field is induced in the antenna 1 and supplied to the strong input reinforcement circuit 3, the set increases the AGC voltage V _AGC , which causes the collector and emitter of the transistor Tr. As the voltage applied between them decreases, the amount of current flowing through the transistor Tr increases, and the voltage applied to the third attenuation diode D3 increases, while the impedance Z3 decreases.

In addition, as the voltage applied to the anode of the third attenuation diode D3 increases due to the increase of the current flowing in the first loop, the voltage applied to the first and second attenuation diodes D1 and D2 of the second loop is Will be less.

Therefore, the amount of current flowing through the first and second attenuation diodes D1 and D2 of the first and second loops of the second loop is decreased, so that the internal impedance of the first and second attenuation diodes D1 and D2 is reduced. (Z ₁ · Z ₂ ) is decreased.

That is, as shown in the equivalent circuit diagram of FIG. 2 (b), the impedance Z ₃ of the signal line decreases and the impedance Z ₁ · Z ₂ , which is bypassed to ground, increases, and the attenuation of the signal decreases.

The steel input reinforcing circuit according to the present invention as described above in more detail with reference to the equivalent circuit diagram of the accompanying drawings (b) as follows.

First, the impedance value of the first, second, third, fourth, and fifth resistors (R1, R2, R3, R4, R5) for AGC bias shown in (a) and the AC impedance value of the coil L1 are sufficiently large and DC blocking and Assume that the impedance values of the bypass first, second, third, fourth, and fifth capacitors (C1, C2, C3, C4, C5, C6) are sufficiently low.

In addition, the input signal voltage is V _i , the output signal voltage is V _o , the input impedance is Z _i , the output impedance is Z _o , and the impedance of the first, second, and third attenuation diodes D1, D2, D3. When Z ₁ , Z ₂ and Z ₃ , respectively,

Forward voltage transfer ratio A is

here,

Expressions (4), (5) and (6) are obtained.

For reference, the symbol // in the formula Z ₂ // Z _o represents the parallel synthesis impedance value of the impedances Z ₂ and Z _o .

Therefore, when a signal of a strong electric field is input to the antenna 1, the value of the impedance Z ₁ · Z _{2 of} the first and second attenuation diodes D1 and D2 is lowered and the third attenuation diode D3 is reduced. ) 'S impedance Z ₂ becomes high.

At this time, the impedance Z ₃ value of the third attenuation diode D3 is sufficiently large (a few kΩ), and the impedance Z ₁ Z ₂ value of the first and second attenuation diodes D1 and D2 is sufficiently large. (Less),

In the above formulas (5) and (6)

a = Z ₃ + Z ₂ // Z _o ≒ Z ₃

b = Z ₁ // a ≒ Z ₁ // Z ₃ ≒ Z ₁

In the above formula (4)

It becomes an expression similar to the said Formula (7).

In addition, if the characteristics of the first and second attenuation diodes D1 and D2 are the same, Z ₁ = Z _{2. If} the input and output impedances Z _i and Z _o are designed to be equal, Z _i = Can be set to Z _o .

Therefore, equation (7)

Equation (8) is the same as the forward voltage transfer ratio is very small, the signal attenuation becomes very large.

On the other hand, when a signal of a weak electric field is input to the antenna 1, the value of the impedance Z ₁ · Z 2 of the first and second attenuation diodes D1 and D2 is increased and the third attenuation diode D3 is The value of impedance Z ₃ is lowered.

At this time, the value of the impedance Z ₃ of the third attenuation diode D3 is sufficiently small (a few ohms), and the value of the impedance Z ₁ · Z _{2 of the first} Ω 2 attenuation diodes D1 and D2 is large. If large enough (a few kΩ), the equations (5) and (6)

a = Z ₃ + Z ₂ // Z _o ≒ Z ₃ + Z _o

b = Z ₁ // a ≒ Z ₃ + Z _o ,

In the above formula (4)

Equation (9) is the same, and if the input and output impedance (Z _i · Z _o ) is designed to be equal to Z _i = Z _o can be set to the equation (9)

Equation (10) is obtained as in Equation ( ₂ ) of the conventional forward voltage transfer ratio.

The characteristics of the attenuation diode as described above are shown graphically as a relation between the forward bias current and the RF resistance, as shown in FIG. 4.

As an example, the numerical values of the conventional attenuation characteristic (2) and the attenuation characteristic (8) of the present invention are substituted and compared as follows.

If the diode current at cutoff is 0.001 (mA) and the diode current at conduction is 10 (mA) and each resistance value is substituted by 700 (Ω) and 0.7 (Ω),

In the above formula (2)

In the above formula (8)

Ratio of A ₂ to A ₁ ;

The magnitude of the formula (11) is very large difference.

As described above, according to the steel input reinforcing circuit according to the present invention, the ratio of the conventional damping characteristic and the damping characteristic of the present invention has a very excellent damping characteristic as shown in Equation (11).

In addition, the steel input reinforcement circuit according to the present invention has a useful effect of not being affected by the AGC driving current of the SET by using the power supply current of the tuner in driving the attenuation diode.

In addition, the conventional steel input reinforcement circuit has obtained the attenuation characteristics only by the attenuation diode of the signal line, and is greatly dependent on the physical and electrical characteristics of the attenuation diode. Bypassing to ground by the attenuation diode has an effect that is hardly affected by the physical and electrical properties of the third attenuation diode.

Claims (1)

A first and second capacitors, a third diode and a fourth capacitor are connected in series from an input terminal to an output terminal, and an anode terminal of the first diode is connected between the first and second capacitors, and the third terminal is connected to the cathode terminal of the first diode. An anode end of a second diode connected between a diode and a fourth capacitor is connected, and a grounded third capacitor is connected between the first and second diodes, and a cathode end of the second diode is connected. A grounded fifth resistor is connected to the contact between the cathode terminal and the fourth capacitor to form a common contact, and one end of the first resistor is connected to the contact between the first and second capacitors to which the anode terminal of the first diode is connected. A second grounded resistor is connected to the other end of the first resistor, and one end of a third resistor is connected between the first and second resistors, and the other end of the third resistor is a power supply terminal and a collector terminal of the transistor. A first coil connected between the second capacitor and the anode terminal of the third diode is connected to the emitter terminal of the transistor, and a fourth resistor for applying an AGC voltage is connected to the base terminal of the transistor. When a signal of a strong electric field is induced at the input terminal, the AGC voltage is dropped to decrease the current flowing through the transistor, thereby increasing the impedance of the third diode and simultaneously increasing the impedance of the first and second diodes. The signal flow between the capacitor and the third diode is interrupted, the signal flowing to ground is passed through the first diode, the third capacitor, the second diode, and the third capacitor, and a weak electric field signal is induced at the input terminal. In this case, the AGC voltage is increased to increase the current flowing through the transistor, thereby reducing the impedance of the third diode. At the same time, the impedance of the first and second diodes is reduced to pass a signal flow between the second capacitor and the third diode, and the signal flowing through the first diode and the third capacitor and the second diode and the third capacitor is reduced. Strong input reinforcement circuit of the tuner, characterized in that the cut off.