WO1982003513A1

WO1982003513A1 - Sense amplifier comparator circuit

Info

Publication number: WO1982003513A1
Application number: PCT/US1982/000368
Authority: WO
Inventors: Corp Ncr; James Frank Patella; Donald Gregory Craycraft
Original assignee: Ncr Co
Priority date: 1981-03-26
Filing date: 1982-03-25
Publication date: 1982-10-14
Also published as: EP0076832B1; EP0076832A1; EP0076832A4; DE3272248D1; JPH0335751B2; CA1170729A; US4412143A; JPS58500426A; ZA822090B

Abstract

A comparator circuit suitable for use as a sense amplifier for a memory array is adapted to distinguish between the levels of two input signals and to provide an output signal in binary form in dependence on the relative values of the input signals. A symmetrically organized circuit in the form of a bistable multivibrator is initially operated in a differential mode and subsequently transitioned to a latch mode. Constant current source biasing (28, 32) optimizes amplifier gain characteristics for the levels of input signals received. The amplified difference between the two input signals is stored within various capacitance elements of the circuit output stages. During the differential mode, the cross-coupling elements (9, 11) of the bistable multivibrator are disabled. At the termination of the differential mode, the amplified difference between the two input signals provides the initial conditions for the regenerative dynamics associated with the enabling of the cross-coupling elements (9, 11) and the transition to the latched state.

Description

SENSE AMPLIFIER COMPARATOR CIRCUIT

Technical Field

This invention relates to comparator circuits of the kind including: a multivibrator of substantially symmetric organization having first and second conduc¬ tive paths, each path containing series connected load elements and amplification elements joined through an intermediate node; coupling means adapted to selectively couple said node in said first path with said amplifi- cation element in said second path and to selectively couple said node in said second path with said amplifi¬ cation element in said first path; input means adapted to selectively apply first and second input signals to said amplification elements in said first and second paths; and control means connected to said coupling means and to said input means and arranged in operation to disable said coupling means concurrently with an enabling of said input means and to enable said coupling means in timed sequence thereafter. Such comparator circuits find application as sense amplifiers for memory arrays.

This invention also relates to a method of operating a symmetrically organized comparator circuit.

Background Art Generally recognized techniques of storing data in memory arrays provide for one data bit per memory cell. The information in each cell is detected externally as a voltage having either a zero level or a high level, respectively corresponding to the binary states of 0 and 1. Effects such as time, temperature, and read-write cycling of the memory array, tend to degrade the window between the voltages associated with each of the two binary states. For these and numerous other reasons, little prior effort has been directed toward subdividing the voltage window and thereby increasing the data stored in each cell. Recently, however, the continued emphasis on ' greater data storage has led to the development of some novel techniques for increasing the data stored in a given area of memory. A specific example of one approach is described in U.S. Patent No. 4,192,014, entitled "ROM Memory Cell With 2ⁿ FET Channel Widths." The subject matter of that patent provides a succinct description of the manner in which the present invention would be utilized. In one embodiment, the memory system taught therein is configured so that each memory cell stores two binary bits of information, and requires memory output signals at four distinct voltage levels to dis¬ tinguish therebetween. As described, each of the binary states (00, 01, 10, and 11) corresponds to a substan- tially equal segment of the voltage window between the outer bounds of ground potential and the power supply.

One of the critical elements in such a memory system is the level detector circuit. Each such circuit must compare the memory voltage read from the array with a segmented level of the operating window to determine which is greater. Furthermore, since speed is an impor¬ tant consideration in obtaining data from large memory arrays, the comparator circuits, otherwise known as sense amplifiers, must have a short settling time. Specifically, distinguishing between voltages in the manner suggested does not appear particularly onerous. However, the difficulties begin to take form when one recognizes some fundamental constraints. For instance, since the output data must be binary in form, each sense amplifier circuit must latch or otherwise select either extreme of the two binary format output states. Further¬ more, the sense amplifier must exhibit adequate differ¬ ential gain to distinguish relatively small voltage differences between two relatively large voltages. No less important is the pursuit of good common mode rejection and fabrication with minimum device count or chip area. For instance, to optimize the speed and gain characteristics of such sense amplifiers, one would normally prefer to operate the input stage field effect transistors so that the gate-to-source voltages are at or very near the threshold level of the transistor. However, the two-bit-per-cell •concept requires three sense amplifier circuits, each operating at substantially different levels over the range between ground potential and the supply voltage. Consequently, the voltages provided to the input stage field effect transistors of at least two sense amplifiers will not be near their threshold voltages. Selective* alteration of transistor threshold voltages during integrated circuit fabrication is not an economically practical solution. Consider another constraint. The ideal sense amplifier would accomplish the above-noted objectives in a single amplification stage. Generally, it is readily feasible to obtain the gain and binary output objectives sought herein by using two cascaded differential a pli- fiers, with the first serving as a level shifter pre¬ amplifier and the second producing an acceptable binary output state. However, the chip area consumed by such duplication of amplifier stages detracts from the re¬ maining objective. Naturally, the potential for in- creased data storage is not fully realized if the binary data stored per unit cell is doubled, but total cell count is reduced as an offset to the area consumed by large sense amplifier circuits.

A comparator circuit of the kind specified is known from U.S. Patent Specification No. 3,982,140. The known comparator circuit has the disadvantage of an unduly limited ability to compare signal levels over a range of voltages.

Disclosure of the Invention It is an object of the present invention to provide a comparator circuit of the kind specified having the capability of comparing signals over a broad ^* range of voltages.

Therefore, according to the present invention, there is provided a comparator circuit of the kind specified, characterized by selectively operable biasing means coupled to said amplification elements and to said control means, said control means being further arranged in operation to enable said biasing means concurrently with the enabling of said input means and to disable said biasing means concurrently with the disabling of said coupling means.

It will be appreciated that in apparatus according to the immediately preceding paragraph the provision of selectively operable biasing means provides a capability for optimising gain and speed. The comparator type sense amplifier according to the invention alleviates the aforementioned disad¬ vantage while retaining excellent speed, -common mode rejection and gain characteristics. Chip area is ^'-minimized and outputs are presented as distinct binary levels. As embodied, the sense amplifier circuit oper¬ ates in two modes, a DIFFERENTIAL MODE for high gain comparison and a LATCH MODE for a stable and fixed binary format output. The transitional dynamics between the DIFFERENTIAL and the LATCH MODES serve to define the latched binary state in direct correspondence to the amplified relative differences obtained during the DIFFERENTIAL MODE. These and other structural and functional features will become apparent from the ensu¬ ing description. According to another aspect of the invention, there is provided a method of operating a symmetrically organized comparator circuit including a pair of ampli¬ fication elements to distinguish between two input signals of similar magnitude and generate a binary form output signal, characterized by the steps of: operating the circuit in a differential mode with respect to said input signals while biasing said amplification elements; and disabling the bias applied to said amplification -,elements in substantial time correspondence with a transition of the circuit from a differential mode to a latch mode, while maintaining impedance symmetry during the dynamics of transition between the differ- - ential mode and the latch mode.

Brief Description of the Drawings

One embodiment of the invention will now be described by way of example with reference to the accom¬ panying drawings, in which: Fig. 1 is a circuit diagram depicting one embodiment of the comparator circuit taking the form of an MOS sense amplifier; and

Fig. 2 illustrates the time-related voltage waveforms at -seven locations within the circuit of Fig. 1.

Best Mode for Carrying Out the Invention

Refer first to Fig. 1 of the drawings, where a representative embodiment- of the circuit is schematically depicted. For present purposes, the field effect trans¬ istors are p-channel, enhancement mode MOS type inte- grated circuit devices. The capacitors shown symboli¬ cally by way of dotted lines are intrinsic gate-to- source parameters in the immediately adjacent transis¬ tors. For purposes of the embodiment, supply voltage V _ is at a nominal level of -17 volts. In the overview, the individual functional groups comprising the overall circuit have been dis¬ tinguished by dashed lines. Circuit section 1, enclosed within the dashed perimeter line, is very similar to the bistable multivibrator circuit disclosed in the last- noted patent. A push-pull operated output driver cir¬ cuit, with a series connected disable transistor, is enclosed within circuit section 2. Circuit section 3 contains a constant current source, regulated by a voltage divider and connected in parallel with a dis- abling transistor. Bifurcated circuit sections 4a and

4b are shown to contain individual precharge transistors. Commence the analysis of circuit and its operation by considering the circuit in segment 1. The voltage signals on the MEMORY COLUMN line and the REFER¬ ENCE line enter the bistable multivibrator whenever the voltage on the commonly connected gate electrodes places respective transistors 6 and 7 into conductive states.

The gate signal corresponds to a LATCH command, being merely an inversion by inverter 8 of the signal on the LATCH line. The same LATCH line signal is shown to be connected to the gate terminals of cross-coupling trans¬ istors 9 and 11. These transistors cross-couple the drain and gate terminals of driver transistors 12 and 13 in the manner of the cited art. Outputs from circuit section 1 are accessible at node V, , common with the drain terminal of transistor 12, and node V„, common with the drain terminal of transistor 13.

The upper region of circuit section 1 is shown to contain substantially identical booted load circuits, serving as load elements for amplifying driver trans- istors 12 and 13 in the two symmetrically arranged arms of the multivibrator circuit. With more specificity, the booted load circuits contain substantially identical load transistors 14 and 16 driven by transistors 17 and 18 from common supply voltage V . The booted load circuits also contain capacitive elements, 19 and 21, between the gate and source terminals of load transis¬ tors 14 and 16, respectively. The unique functional contributions of the two booted inverter circuits will become apparent when the multivibrator circuit dynamics are described at a point hereinafter.

The circuit section designated by reference numeral 2 comprises the output coupling stage, including a set of oppositely driven push-pull transistors, 24 and 26, connected in series with the disabling transistor, 27. The purpose of this circuit segment is twofold.-

First, push-pull transistors 24 and 26 form substantially identical load impedances for multivibrator nodes V, and V , decoupling and thereby insuring that the effects of output loads will not alter the circuit^' dynamics- during the transition between DIFFERENTIAL and LATCH MODES of the operating sequence. The remaining transistor, 27, is present to prevent the formation of a short circuit path from V to ground through transistors 24 and 26 during the DIFFERENTIAL MODE of the .operation. During that mode, the voltages at both nodes, V, and V^" ₂, lie be¬ tween V _ and ground, effectively placing series connec¬ ted transistors 24 and 26 into full conduction. Upon entering the LATCH MODE, the node voltages are driven to opposite extremes, placing one of the two push-pull transistors into a nonconducting state and thereby avoid¬ ing a short circuit between the power supply and ground. The circuit segment designated by reference numeral 3 establishes a differential organization of the circuit and biases the voltage appearing at. the source terminals of driver transistors 12 and 13. In this way, ^' the voltage levels on the MEMORY COLUMN line and REFER¬ ENCE line differ from the biased source voltage V_ς in an amount approximating the threshold of the driver trans¬ istors. Using Fig. 2 to illustrate, if the REFERENCE voltage is at a level of -9 volts, the MEMORY COLUMN voltage is of a similar magnitude, and the threshold volt¬ ages of transistors 12 and 13 are approximately -3 volts, node V will be approximately -6 volts during the DIFFER¬ ENTIAL MODE of operation. Undoubtedly, one now recog¬ nizes that the voltage at node is the greater of two . voltage combinations, i.e., the MEMORY COLUMN voltage less the threshold of transistor 12 or the REFERENCE voltage less the threshold of transistor 13. However, care must be exercised during the design of interacting FΞTs 12, 13, 14, 16 and 28 to insure that voltage on node V_g can reach the levels sought.

The embodying bias circuit -is shown to contain transistor 28, connected between node V_g and ground po¬ tential, and operated in the manner of a constant current source. Transistors 29 and 31 form a voltage divider which regulates the current flow through transistor 28. PI Consequently, transistor 28 provides not only a commen¬ surate level of source terminal biasing, but also common mode rejection for the input signals connected to the gate terminals of driver transistors 12 and 13. No less important is the increased differential gain as perceived at nodes V, and V-.

A disabling transistor, 32, suitably function¬ ing as an electrical short for constant current source transistor 28, is shown connected in electrical parallel with transistor 28. In the depicted embodiment, the gate electrode of transistor 32 is energized by an appropriate signal on the LATCH line. In this way, a LATCH signal shorts the constant current source and allows the output voltages at nodes V, and V~ to approach the opposite ex- tremes of the voltage supply. The OUTPUT signal during the LATCH MODE follows in ordered sequence, assuming a binary format suitable to prevent the shorting of push- pull output transistors 24 and 26. . .

Circuit sections 4a and 4b are shown to contain transistors 33 and 34, serving to selectively connect output nodes V- and V„ with ground potential. When appropriately energized with a signal on the PRECHARGE line, transistors 33 and 34 short nodes V, and V_ to ground. Booted inverter capacitors 19 and 21 are thereby charged to a voltage approaching the level of V minus a FET threshold. The existence of the voltage on capa¬ citors 19 and 21 temporarily increases the gate voltage on transistors 14 and 16 at the onset of the transient period between the DIFFERENTIAL MODE and the LATCH MODE, briefly, but significantly, increasing the current through these transistors. Recognizing that nodes V, and V^" ₂ are capacitively loaded by the various elements attached thereto, it becomes apparent that the transient overdrive of the load transistors is directed toward increasing the circuit's switching speed. Furthermore, the booting action allows for the binary "1" output level of either node V. or V₂ to approach V _D during cyclic operation,

- TREAT instead of the ^v _Dn~^Vthreshold ^that would otherwise be attained.

With an understanding of the constituent circuits at hand, the operation of the composite circuit will be considered next. Generally, it may be said that the regenerative dynamics coupled with the circuit symmetry ensure appropriate latching in the course of the transition from the DIFFERENTIAL MODE to the LATCH MODE. During this transient period, the multivibrator circuit must operate with substantial symmetry if the nominal voltage difference between nodes V, and V₂ is to consistently define the final binary state of the circuit. For this reason, the embodiment in Fig. 1 contains supplemental capacitors 36 and 37, respectively connecting nodes V, and V- to ground potential. The two capacitors are substantially identical in size relative to each other, yet significant in comparison to the intrinsic capacitive loads coupled to nodes V, and V-. Thereby, minor unbalances are effectively suppressed. Furthermore, since the differential voltages are stored on these supplemental capacitors, they also drive the proper selection of binary output state without sig¬ nificantly degrading circuit speed. Undoubtedly, if the impedance loads on nodes V, and V₂ are substantially identical without capacitors 36 and 37, their contribu¬ tion is superfluous. In similar context, intrinsic gate-to-source capacitors 22 and 23 should also be con¬ sidered for their influence on the transition dynamics. With an understanding of the circuit constitu- ents and their interactive functions at hand, it is appropriate to describe the circuit operation with reference to the group of voltage-time plots depicted in Fig. 2. At the outset, it should be noted that the plots depict only that segment of the overall operating period which illustrates the circuit dynamics. The node and line labels correspond to those appearing in Fig. 1. The important time events are shown by dashed lines projecting vertically, with appropriate labels at the top and bottom of the figure. Consistent with the concept that Fig. 2 merely depicts one embodiment of the invention, those skilled in the art will recognize that some of the events are amenable to variations in time without affecting circuit function. Where such permu¬ tations of events affect circuit operation, they will be specifically noted. For purposes of illustrating circuit principles, the PRECHARGE, LATCH, REFERENCE and MEMORY COLUMN waveforms are illustrated as being ideal signals. The PRECHARGE MODE, designated at the top of

Fig. 2, corresponds to a period when a precharge command signal energizes transistors 33 and 34 to effect a ^■grounding of nodes V, and V₂. V_g is also brought to ground potential. In the manner described previously, capacitors 19 and 21 are precharged through transistors 17 and 18, with the minimum duration constrained by the component time constants. Note from the voltage plots that during the PRECHARGE MODE, the signal on the LATCH line is zero, disabling the path through transistors 9, 11, 27 and 32, while enabling conduction through trans¬ istors 6 and 7.

The plots in Fig. 2 show that the REFERENCE line signal attains -9 volts and the MEMORY COLUMN line signal attains -8.8 volts at time t_Q. These two signals serve as the inputs to the sense amplifier circuit.

Reflecting back upon the description in the last-cited U.S. Patent, the amplitude of the REFERENCE signal corresponds to the voltage level distinguishing between a binary 01 state and a 10 state. From this, the -8.8 volts on the MEMORY COLUMN line illustrates memory data corresponding to the binary 01 state. Proceeding with the analysis of Fig. 2, it is apparent that immediately after time t_Q the PRECHARGE and LATCH line signals inhibit any circuit reaction to the MEMORY COLUMN and REFERENCE line signals noted. The latter effect shows that the REFERENCE and MEMORY COLUMN signals may, as shown, coincide in time, but are not so constrained. The two signals may also commence individually, at points in time between events t, and t₂ shown in the plots. However, any associated DIFFERENTIAL MODE dynamics must cease before time t₂. In like manner, either of the two signals may also terminate at any time after the onset of the LATCH MODE at time t₂.

Continuing again with the time analysis of the various signals plotted, it is shown that the PRECHARGE line signal ceases at time t,. Since transistors 9 and 11 in the cross-coupling arms of the multivibrator con- tinue to remain off, the circuit then assumes a differ¬ ential amplifier mode of operation. Node V_g shifts to approximately -6 volt by virtue of the -9 volt REFERENCE signal and 3 volt threshold of FET 13 as nodes V. and V₂ fall to -15 and -14 volts, respectively. The one volt differential between nodes V.. and V₂ represents a voltage gain of 5 over the difference of 0.2 volts separating the MEMORY COLUMN voltage (8.8 volts) and the REFERENCE voltage (9 volts). The exponential shape of the voltages on nodes V- and V^* ₂, immediately following time t. , are attributable to the σapacitive loads on each of the nodes, and particularly supplemental capacitors 36 and 37.

Time t₂ prescribes the entry into the LATCH MODE of the operating sequence. Commencement of the mode is evidenced by the presence of a LATCH line signal, culminating soon thereafter in the latching of the bistable multivibrator into one of two^' states. Opera- tively, the onset of the LATCH signal energizes trans¬ istors 9, 11, 27 and 32, as it de-energizes data entry transistors 6 and 7. In the embodiment, the voltages at nodes V_s and V₂ fall to ground potential as node V. rises to V _D of the power supply.. The push-pull output transistors, 24 and 26, follow in prescribed manner. The interval between the conclusion of the t_ transient and the onset of time t^,-provides a suit- able period for sampling the multivibrator output to determine which of the two input signals, REFERENCE or MEMORY COLUMN, were greater in absolute magnitude. In the context of this particular embodiment, -17 volts ^ at V. and an OUTPUT line voltage of ^"v^*__D indicates that the REFERENCE line signal was greater than the signal on the MEMORY COLUMN line. Therefore, the stored data must be either 00 or 01, depending on the response of the next adjacent sense amplifier in the manner taught by the previously noted U.S. Patent. Consistent with the teaching in U.S. Patent 4,192,014, the composite of the three sensor amplifiers is necessary to ascertain the exact binary state in each memory cell. The dynamics of the circuit at time t₂, as well as the initial conditions on the circuit elements immediately preceding time t₂ are important in under¬ standing the transition between the DIFFERENTIAL MODE and the LATCH MODE. The dominant operative considera- tions are symmetry in the circuit and asymmetry in the initial conditions stored- on the capacitive elements. Using the embodiment as an example, analysis of the voltage levels at nodes V, and V₂ shows that the capa- citively loaded nodes differ by one volt at time t_. The appearance of a LATCH line signal at that time simultaneously energizes shorting transistor 32 and cross-coupling transistors 9 and 11. The initial levels of conductivity in driver transistors 12 and 13 are retained by the charge stored on the intrinsic capacitors 22 and 23. Immediately thereafter, however, the cross- coupled voltages, with an unbalance of one volt, begin to distinctly affect transistors 12 and 13. Recalling the symmetry in the active and passive circuit elements, one recognizes that the additional volt on terminal V. drives transistor 13 greater than transistor 12. Since voltage V₂ is lower in absolute magnitude to begin with, the regeneration immediately following time t« pulls node V₂ to ground potential as V, is elevated to a level approaching V_DD. _ _. To briefly summarize the operative events in time proximity to t₂, note that in the time preceding t₂ slightly unequal voltages are compared, amplified and stored as asymmetric initial conditions on passive circuit elements. Thereafter, reversion to the bistable multivibrator configuration combines circuit symmetry and regenerative dynamics to allow a nominal difference in initial conditions to drive the circuit to one of two stable states.

The LATCH MODE terminates with time t-. As . embodied, and shown in the plots of Fig. 2, the onset of the PRECHARGE MODE coincides with the end of the LATCH MODE. If precharging commences prior to t^, the sampling period would merely be shortened accordingly. Were it to commence after time t~, however, the circuit would temporarily revert to the DIFFERENTIAL MODE for the interim therebetween.

The voltage plots of the embodying circuit show that the MEMORY COLUMN line and the REFERENCE line signals fall to ground potential at time t.. Since the entry of these signals into the circuit is controlled by a signal inverse to the LATCH line signal, coupled to transistors 6 and 7, the MEMORY COLUMN and REFERENCE signals may remain at all times without affecting cir¬ cuit operation.

In brief summary, it will be appreciated that the described embodiment is operatively characterized by a sequence commencing with a DIFFERENTIAL MODE and followed in time by a LATCH MODE. The output signal during the LATCH MODE is in binary format with the state representing the relative standing of two input signal levels compared during the DIFFERENTIAL MODE_* Substan¬ tially identical load and amplifier elements in the two conductive paths of the circuit are biased during the DIFFERENTIAL MODE to optimize gain by operating the driver FETs near their threshold voltages. The ampli¬ fied difference between the two input signals being compared during the DIFFERENTIAL MODE provides the initial conditions on the capacitive elements in the circuit for the succeeding transition to the LATCH MODE. Thereby, the regenerative dynamics associated with the transition to the LATCH MODE consistently latches the circuit into the appropriate binary^"state. Upon entering the LATCH MODE, the circuit bias and input signals may be decoupled from the comparator circuit.

The described embodiment of the comparator circuit comprises a symmetrically arranged bistable multivibrator, cross—coupled through commonly actuated devices suitably operable to disconnect the cross- coupling paths. The amplification devices in the two respective arms of the multivibrator circuit are common- ly connected at one end to a constant current source during the DIFFERENTIAL MODE; the source being adjusted to bias the amplification devices into regions of high gain. A shorting device in electrical parallel with the current source, and actuated in synchronism with the devices in the cross-coupling paths, disables the cur¬ rent source during the LATCH MODE. - - --

In the described embodiment, individual de¬ coupling FETs are connected in the path of each input signal to the comparator. The FETs operatively decouple the input signals to the bistable multivibrator when appropriately driven with command signals synchronized to the LATCH MODE. The multivibrator inverters contain booted load FETs. The inverter circuits are then pre- charged before the onset of the DIFFERENTIAL MODE, to ensure proper booting operation and to decrease the settling time attributable to that mode.

The comparator as taught herein is particularly suited for fabrication using integrated circuit tech¬ nology and insulated gate field effect transistors (IGFETs) as the active elements. As embodied, the

DIFFERENTIAL MODE bias circuit shifts the source voltages of the driver FETs into a threshold voltage proximity with the input voltages. Thereby, the highest gain is attained from the differentially operated driver FETs. Precise control of the structural symmetry, in conjunc¬ tion with the capacitive storage of the amplified dif¬ ferences, ensures that the correct binary state is obtained at the conclusion of the dynamic transition between the DIFFERENTIAL MODE and the LATCH MODE. Reflecting back upon the description of the circuit elements and their combined operative character¬ istics, it becomes apparent that speed and consistent level differentiation comprise inherent attributes of the present invention. Furthermore, the timing sequence shown and described clearly evinces the degree of synch¬ ronism necessary without imposing onerous burdens, such as transistor gain, input signal level restrictions or response time constraints, on internal devices and external data. With a recognition of these attributes at hand, alternative arrangements of the embodiment by those skilled in the art are feasible without departing from the scope of the claimed invention.

Claims

CLAI S :

1. A comparator circuit, including: a multivibrator of substantially symmetric organization having first and second conductive paths, each path containing series connected load elements (14, 16} and amplification elements (12, 13) joined through an inter¬ mediate node? coupling means (9, 11) adapted to selec¬ tively couple said node in said first path with said amplification element (13) in said second path and to selectively couple said node in said second path with said amplification element (12) in said first path; input means (6, 7) adapted to selectively apply first and second input signals to said amplification elements (12, 13) in said first and second paths; and control means connected to said coupling means (9, 11) and to said input means (6, 7) and arranged in operation to disable said coupling means (9, 11) concurrently with an enabling of said input means (6, 7) and to enable said coupling means .(9, 11) in timed sequence thereafter, characterized by selectively operable biasing means (28, 32) coupled to said amplification elements (12, 13) and to said control means, said control means being further arranged in operation to enable said biasing means (28, 32) concurrently with the enabling of said input means (6, 7) and to disable said biasing means (28, 32) con- currently with the enabling of .said coupling means (9, 11).

2. A comparator circuit according to claim 1, characterized in that said control means is further arranged in operation to effect a disabling of said input means (6, 7) concurrently with an enabling of said coupling means (9, 11). - -

3. A comparator circuit according to claim 2, characterized by a pair of output amplification elements (24, 26) of substantially equal load impedance coupled 3 . ( concluded ) respectively to said nodes and to said control means, 5 said control means being further arranged in operation to disable said output amplification elements (24, 26) for an interval of time coincident with the disabling of said coupling means (9, 11).

4. A comparator circuit according to claim 3, characterized in that said load elements include substantially identical booted load circuits (14, 17, 19; 16, 18, 21), and further characterized by pre-

5 charging means (33, 34) coupled to said booted load circuits (14, 17, 19; 16, 18, 21) and adapted, to pre- charge said booted load circuits (14, 17, 19; 16, 18, 21).

5. A comparator circuit according to claim 1, characterized in that said selectively operable biasing means includes a constant current source (29, 31, 28) coupled between a source of potential and a

5 common connection of said first and second conductive paths and a selectively operable switch (32) coupled in parallel with said constant current source (29, 31, 28).

6. A comparator circuit according to claim 1, characterized by supplemental impedance loading (36, 37) coupled to each of said loads whereby the impedance loads at each of said nodes are substantially balanced.

7. A comparator circuit according to claim 1, characterized in that said coupling means includes a first coupling device (9) connected between said node in said first path and said amplification element (13) i in said second path and a second coupling device (11) connected between said node in said second path and said amplification element (12) in said first path.

8. A comparator circuit according to any one of the preceding claims, characterized in that said 8. ( concluded ) amplification elements (12, 13), load elements (14, 16), coupling means (9, 11) and biasing means (28, 32) are fabricated as integrated circuits with field effect type transistors.

9. A method of operating a symmetrically organized comparator circuit including a pair of ampli¬ fication elements (12, 13), to distinguish between two input signals of similar magnitude and generate a binary form output signal, characterized by the steps of: operating the circuit in a differential mode with respect to said input signals while biasing said ampli¬ fication elements (12, 13); and disabling the bias applied to said amplification elements (12, 13) in sub- stantial time correspondence with a transition of the circuit from a differential mode to a latch mode, while maintaining impedance symmetry during the dynamics of transition between the differential mode and the latch mode.

10. A method according to claim 9, character¬ ized in that the transition of the comparator circuit from a differential mode to the latch mode is performed by enabling cross coupling paths (9, 11) in a bistable multivibrator section of said circuit.

11. A method according to claim 10, charac¬ terized by the step of decoupling said input signals in time correspondence with the transition between the differential mode and the latch mode.

12. A method according to any one of claims

9, 10 or 11, characterized by the step-of precharging said comparator circuit prior to operating the circuit in a differential mode.