JPH07244995A - Sense circuit for read only memory - Google Patents

Abstract

PURPOSE:To obtain a sense circuit reading out massive information in an ROW with a low power consumption and also at high speed. CONSTITUTION:A PMOS 13 and a PMOS 16 charge respectively a bit line 14 and a reference potential line 17 to the Level of a power source potential VCC based on a precharging signal PC/. After the completion of a charging period, PMOSs 13, 16 become off-states and the bit line 14 begins a discharge or a charge according to the data of a selected memory cell 1a. Simultaneously, the reference potential line 17 begins a discharge via an NMOS 18, however, the internal impedance 19b of a reference potential generating circuit 19 is adjusted so that the discharging time becomes longer than that of the bit line 14. Thus, significant data are outputted as an output signal S15A from the point of time when a minute potential difference is generated in the first and second input terminals of a sense amplifier 15A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read only memory (Read Only Memory) which realizes low power consumption and high speed reading.
y, hereinafter referred to as ROM), and particularly satisfies the requirement of simplicity in designing an LSI such as a one-chip microcomputer or a consumer custom IC.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there was the following. FIG. 2 shows a conventional ROM
3 is a schematic circuit diagram showing a configuration example of a memory cell array and a sense circuit of FIG. In this memory cell array 1, memory cells are connected at respective intersections of a plurality of word lines and bit lines, the memory cells are arranged in a matrix, and each bit line is driven by output signals Y0 to Yi of a bit selector (not shown). N-channel type MOS transistors (hereinafter referred to as NMOS) 2-0 to 2-i are connected. A word selector (not shown) is connected to each word line, and the word line is selected by the output signals W0 to Wi of the word selector. Sense circuit 10
Is a P-channel MO that is the first MOS transistor
An S transistor (hereinafter referred to as PMOS) 13 is provided. The source of the PMOS 13 is connected to the power supply potential VCC, and the drain is connected to the input side of the inverter 15 via the bit line 14. PMOS 13 is a bit line 14
And the power supply potential VCC are electrically connected based on the precharge signal PC /. The inverter 15 has a bit line 1
4 is a sense amplifier that determines data according to the potential on the upper side.

FIG. 3 is a circuit diagram showing one configuration example of the memory cell array 1 in FIG. 2 and NMOS 2-0 to 2-i.
This memory cell array 1 has a plurality of word lines w0 to wi.
The memory cells 1a are connected to the intersections of the bit lines y0 to yi, and the memory cells 1a are arranged in a matrix. NMOS 2-0 to 2 are connected to the bit lines y0 to yi.
-I sources are each connected. NMOS2-
0 to 2-i are output signals Y of a bit line selector (not shown)
It is an element that selects the bit lines y0 to yi based on 0 to Yi. Next, the operation of the sense circuit of the ROM shown in FIG. 2 will be described. Output signal W of a word line selector not shown
0 to Wi and the output signal Y0 of the bit line selector (not shown)
When the memory cell 1a in the memory cell array 1 is selected and activated by ~ Yi, data starts to be output to the bit line 14. At this time, the bit line 14 holds the charge level or is discharged depending on the presence or absence of ROM data. An output signal S15 of "L" or "H" is output from the output side of the inverter 15 depending on the state of the potential of the bit line 14 with respect to the logical threshold voltage of the inverter 15 which is a sense amplifier. As described above, the signals for controlling the ROM are only the address input signal including the output signals Y0 to Yi of the bit line selector and the output signals W0 to Wi of the word line selector and the precharge signal PC /, and the sense circuit 10 is controlled. It was a simple one that did not require extra timing to operate.

[0004]

However, the conventional sense circuit has the following problems. Figure 2
Since the ROM provided with the conventional sense circuit is a voltage-sensing type, the power consumption is mainly limited to charging and discharging of the bit line 14, which is advantageous as a low power consumption ROM. Since the mutual conductance gm is reduced and the parasitic capacitance of the bit line 14 is increased due to the miniaturization of the transistor, the discharge time of the charges charged in the bit line 14 becomes long. Cause delay. As a means for avoiding this, the sense circuit 10 is provided with a voltage comparator, a reference voltage source is further incorporated, and the potential of the bit line by the memory cell selected by comparing the potentials of the bit line and the dummy bit line. There was a technique for amplifying minute changes to increase the speed, but on the other hand, control of internal circuits and internal timing tended to be complicated. The present invention provides a sense circuit for a voltage-sensing ROM capable of high-capacity and high-speed reading while having the advantages of low power consumption and circuit simplicity of the conventional technology described above.

[0005]

In order to solve the above-mentioned problems, a first invention has first and second input terminals, and a bit line potential inputted to the first input terminal and A sense amplifier for detecting a potential difference between reference potentials input to the second input terminal and a sense amplifier which conducts on the basis of a precharge signal, and when in a conductive state, connects the first input terminal to a power supply potential to precharge Read-only memory sense circuit for determining data held in a selected memory cell in a memory cell array having a plurality of word lines and bit lines based on a change in the potential of an activated bit line. In, the following measures are taken. That is, the conduction state is controlled based on the precharge signal,
A second MOS transistor that conducts the second input terminal and the power supply potential when in the conductive state, a reference potential generating means that generates a reference potential, and a second MOS transistor that operates complementarily and conducts. There is provided a third MOS transistor which electrically connects the second input terminal and the reference potential generating means in the state. Further, the reference potential generating means is the second MO.
It has an internal impedance that makes the drop of the potential of the second input terminal due to the discharge slower than the drop of the potential of the bit line when the S transistor is turned off.

According to a second aspect of the invention, the potential difference between the bit line potential input to the first input terminal and the reference potential input to the second input terminal is provided. A sense amplifier for detection and a first MOS transistor which conducts on the basis of a precharge signal and which precharges by connecting the first input terminal to the power supply potential when in the conductive state are provided. The following measures are taken in the sense circuit of the read-only memory that determines the data held in the selected memory cell in the memory cell array having a plurality of word lines and bit lines based on the potential change. That is, the conduction state is controlled based on the precharge signal, the second MOS transistor conducting the second input terminal and the power supply potential in the conduction state, the reference potential generating means for generating the reference potential, and a plurality of Of the word lines of which the conduction state is controlled based on the potential of one of the word lines which is selectively activated, operates in a complementary manner to the second MOS transistor. A third MOS transistor is provided which is electrically connected to the reference potential generating means. The reference potential generating means is the second MOS.
Second due to discharge when the transistor is turned off
Has an internal impedance that makes the drop of the potential of the input terminal of the input terminal slower than the drop of the potential of the bit line.

In the third invention, the first and second MOS transistors of the first invention are formed by NMOS.
According to a fourth aspect of the present invention, the first and second input terminals are provided, and the potential of the bit line input to the first input terminal and the common reference potential input to the second input terminal are input. A plurality of sense circuits that have a plurality of word lines and bit lines and that determine the data held in a selected memory cell in a memory cell array group that is connected in common with the plurality of word lines. An amplifier is provided. Further, a plurality of first N-channel type MOS transistors which conducts on the basis of the precharge signal and precharges by connecting the first input terminal to the power supply potential when in the conductive state, and a conductive state on the basis of the precharge signal Is controlled and is in a conductive state, a second NMOS that conducts a plurality of second input terminals and the power supply potential, a reference potential generating means that generates a reference potential, and a plurality of word lines are selectively activated. The conduction state is controlled based on the potential of the converted word line to operate complementarily to the second NMOS, and when in the conduction state, the plurality of second input terminals and the reference potential generating means are conducted respectively. And a third MOS transistor. Further, the reference potential generating means has an internal impedance that makes the potential drop of the plurality of second input terminals due to the discharge slower than the potential drop of the plurality of bit lines when the second NMOS is turned off. is doing.

[0008]

According to the first aspect of the invention, since the sense circuit is configured as described above, the first MOS transistor precharges the first input terminal based on the precharge signal. On the other hand, the second MOS transistor precharges the second input terminal based on the precharge signal. Further, the sense amplifier detects the potential difference between the potential of the bit line input to the first input terminal and the reference potential input to the second input terminal, and based on the potential change of the activated bit line. The data held in the memory cell is determined. Third M
The OS transistor operates complementarily to the second MOS transistor, and electrically connects the second input terminal and the reference potential generating means. Further, the internal impedance of the reference potential generating means functions to make the potential drop of the second input terminal due to the discharge slower than the potential drop of the bit line when the second MOS transistor is turned off. According to the second invention, the first MOS transistor is the first MOS transistor.
The transistor precharges the first input terminal based on the precharge signal. On the other hand, the second MOS transistor precharges the second input terminal based on the precharge signal. Further, the sense amplifier detects the potential difference between the potential of the first input terminal and the potential of the second input terminal to determine the data held in the memory cell. Third M
The OS transistor operates complementarily to the second MOS transistor, and electrically connects the second input terminal and the reference potential generating means. Further, the internal impedance of the reference potential generating means functions to make the potential drop of the second input terminal due to the discharge slower than the potential drop of the bit line when the second MOS transistor is turned off.

According to the third invention, in the first and second MOS transistors composed of NMOS, the charge level of the first and second input terminals of the sense amplifier is lower than the power supply potential by the threshold value of the NMOS. There is a function to do. According to the fourth invention, the plurality of sense amplifiers respectively input the potential of the bit line input to the first input terminal and the common reference potential input to the second input terminal, and calculate the potential difference between them. Then, the data held in the selected memory cell in the memory cell array group is determined. Further, the plurality of first N-channel type MOS transistors precharge the first input terminal based on the precharge signal. On the other hand, the second N
The MOS precharges the plurality of second input terminals based on the precharge signal. The third MOS transistor, whose conduction state is controlled based on the potential of the word line, operates in a complementary manner with the second NMOS, and electrically connects the plurality of second input terminals to the reference potential generating means. Further, the internal impedance of the reference potential generating means works to make the potential drop of the plurality of second input terminals due to the discharge slower than the potential drop of the plurality of bit lines when the second NMOS is turned off. do. Therefore, the above problem can be solved.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a schematic circuit diagram showing a configuration example of a memory cell array and a sense circuit of a ROM according to a first embodiment of the present invention. Common elements are given common reference numerals. The memory cell array 1 is the same as that of the conventional FIG. The sense circuit 10A includes a PMOS 13, which is a first MOS transistor, as in the conventional case. The source of the PMOS 13 is connected to the power supply potential VCC, and the drain is connected to the sense amplifier 15 via the bit line 14.
It is connected to the first input terminal of A. PMOS 13
Is an element for electrically connecting the first input terminal of the sense amplifier 15A and the power supply potential VCC based on the precharge signal PC / input to its gate. In addition, the sense circuit 10A includes a PMOS1 which is a second MOS transistor.
6 is provided. The source of the PMOS 16 is the power supply potential VC
The drain is connected to C and the drain is connected to the second input terminal of the sense amplifier 15A via the reference potential line 17. P
The MOS 16 is an element for electrically connecting the reference potential line 17 and the power supply potential VCC based on the precharge signal PC / input to its gate. The sense amplifier 15A is composed of, for example, a differential amplifier, and includes the bit line 14 and the reference potential line 1.
7 is a circuit that detects a potential difference between 7 and determines data held in the memory cell array 1. Furthermore, this sense circuit 1
0A is the third MOS transistor NMOS18
have. The NMOS 18 has a drain connected to the second input terminal of the sense amplifier 15A via the reference potential line 17, and a source connected to the reference potential side of the reference potential generating circuit 19 which is the reference potential generating means. NMOS 18
Is an element that operates complementarily to the PMOS 16 based on the precharge signal PC / input to its gate and electrically connects the second input terminal of the sense amplifier 15A and the reference potential generating circuit 19 when in the conductive state. Is. The reference potential generation circuit 19 includes a reference potential generation unit 19a that generates a reference potential.
And internal impedance 19b. The internal impedance 19b is an element that makes the potential drop of the second input terminal of the sense amplifier 15A caused by discharge slower than the potential drop of the bit line 14 when the PMOS 16 is turned off.

FIG. 4 is a time chart for explaining the operation of FIG. 1, in which the horizontal axis represents time and the vertical axis represents voltage. The operation of the sense circuit of FIG. 1 will be described with reference to this figure and FIG. The PMOS 13 connects the bit line 14 to P
The MOS 16 connects the reference potential line 17 with the precharge signal PC /
The power is charged to the level of the power supply potential VCC. After the end of the precharge period, the PMOSs 13 and 16 are turned off, and the bit line 14 is discharged according to the ROM data written in the memory cell 1a selected by the word lines w0 to wi and the bit lines y0 to yi in FIG. Or start charging. At the same time, the reference potential line 17 starts discharging through the NMOS 18 which is turned on,
The internal impedance 19b of the reference potential generating circuit 19 is adjusted so that the discharging time is longer than the discharging time of the bit line 14. Therefore, from the time when a minute potential difference occurs at the first and second input terminals of the sense amplifier 15A,
Significant data is output as the output signal S15. As described above, in the first embodiment, a high-speed read of ROM data can be realized with a simple circuit configuration and low power consumption, even though it is a sense circuit for comparing the bit line potential and the reference potential.

Second Embodiment FIG. 5 is a circuit diagram showing a configuration example of a sense circuit according to a second embodiment of the present invention. Elements common to those in FIG. 1 are designated by common reference numerals. ing. The word lines w0 to wi of the memory cell array 1 are connected to the output sides of the AND gates 21-0 to 21-i. AND gate 21-0 to 21-
An output side of a word line selector (not shown) is connected to each one input side of i, and an output side of a precharge signal generation circuit (not shown) is commonly connected to each other input side. The sense circuit 10B has NMOSs 22-0 to 22-i, which are third MOS transistors, and respective gates thereof are connected to the word lines w0 to wi, respectively. Others are the same as that of FIG. Next, the operation of the sense circuit of FIG. 5 will be described. In the sense circuit 10B, the bit lines 14 and the reference potential line 17 have the same discharge start time by controlling the gates of the NMOSs 22-0 to 22-i with the potentials of the word lines w0 to wi. Others are shown in FIG.
Same operation as. As described above, in the second embodiment, word line selectors and word lines w0 to w0
The bit line 14 caused by the wiring capacitance of the wi itself and the element delay
The discharge start time between the reference potential line 17 and the reference potential line 17 is eliminated. Therefore, it is possible to prevent erroneous data output due to the potential of the reference potential line 17 being temporarily lower than the potential of the bit line 14 during discharging.

Third Embodiment FIG. 6 is a circuit diagram showing a configuration example of a sense circuit according to a third embodiment of the present invention. Elements common to those in FIG. 1 are designated by common reference numerals. ing. In the sense circuit 10C, the first and second MOS transistors are composed of NMOS 13A and 16A, and the gate of the NMOS 16A is connected to the inverter 16B.
It is connected to the gate of the NMOS 18 via. Others are the same as that of FIG. FIG. 7 is a schematic circuit diagram of the input section of the sense amplifier 15A in FIG. This input portion is provided with NMOS 15a, 1 whose sources are connected to each other.
5b differential amplifier, each drain is PMOS
It is connected to each drain of 15c and 15d. The gate and drain of the PMOS 15c are connected to each other, and the PMOS 15c and the PMOS 15d constitute a current mirror circuit. PMOS 15c, 15d
Each source of is connected to the power supply potential VCC. NMO
The sources of S15a and S15b are both connected to the drain of the NMOS 15e, and the source of the NMOS 15e is connected to the ground. A control circuit (not shown) is connected to the gate of the NMOS 15e, and the control signal co of the control circuit is
nt controls the operation / non-operation of this input section. next,
The operation of the sense circuit of FIG. 6 will be described. In the current mirror type single power supply differential amplifier having the MOS transistor configuration as shown in FIG. 7, a dead zone corresponding to the threshold voltage VT of the MOS transistor is generated from the power supply potential VCC. That is, when the charge level is set to the power supply potential VCC, the differential input voltage becomes VC
No significant data is output until the level drops to the level of C-VT. Therefore, this hinders an increase in the read speed of the ROM. In order to eliminate this, the first and second M
The OS transistor is composed of NMOS 13A and 16A,
The differential input voltage is set to VCC-VT. As described above, in the third embodiment, the charge level of the bit line 14 and the reference potential line 17 is set to VCC-VT, thereby eliminating the time required for the potential of the bit line to drop from VCC to VCC-VT. Therefore, the read time can be shortened.

Fourth Embodiment FIG. 8 is a circuit diagram showing a configuration example of a sense circuit according to a fourth embodiment of the present invention. Elements common to those in FIGS. 1, 5 and 6 are common. The reference numeral is attached. This fourth embodiment is
The second embodiment and the third embodiment are combined, and the reference potentials of a plurality of sense amplifiers are made common. That is, the memory cell array group 1A is connected with the word lines w0 to wi in common. On the other hand, the sense circuit 10D includes NMOSs 13A0 to 1A1 that are a plurality of first MOS transistors.
3Aj, and the gates to which the precharge signal PC having a phase opposite to that of the precharge signal PC / is input are commonly connected. Each drain is connected to the power supply potential VCC. In addition, each source has a plurality of sense amplifiers 15A-0 to 15A- through bit lines 14-0 to 14-j, respectively.
j is connected to each first input terminal. or,
The source of the NMOS 16A is commonly connected to each second input terminal of the sense amplifiers 15A-0 to 15A-j via the reference potential line 17. The other configurations are the same as those in FIGS. Next, the operation of the sense circuit of FIG. 8 will be described. In the sense circuit of FIG. 8, as in the second embodiment, the gates of the NMOSs 22-0 to 22-i are controlled by the potentials of the word lines w0 to wi, respectively.
The discharge start times of 4-0 to 14-j and the reference potential line 17 are the same. Further, as in the third embodiment, since the plurality of first MOS transistors and the second MOS transistors are composed of the NMOSs 13A0 to 13Aj, 16A, the reading is started from the charge level of VCC-VT.

As described above, in the fourth embodiment, similarly to the second embodiment, the bit line 14-caused by the wiring capacitance of the word line selector and the word lines w0 to wi themselves and the element delay which are not shown. The deviation of the discharge start time between 0 to 14-j and the reference potential line 17 is eliminated. Therefore, it is possible to prevent erroneous data output due to the potential of the reference potential line 17 being temporarily lower than the potential of the bit lines 14-0 to 14-j during discharging. Further, similarly to the third embodiment, the charge level of the bit lines 14-0 to 14-j and the reference potential line 17 is set to VCC-VT, so that the bit line 14-0.
Since the time for the potential of 14-j to drop from VCC to VCC-VT is eliminated, the read time can be shortened. Further, the reference potential generation circuit 19 is provided with a plurality of output ROs.
Since only one M is required, the ROM formation area can be reduced. The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) PMOS 13, 16 and NMOS 13A, 13A
0-13Aj, 16A, 18, 22-0 to 22-j are
It may be configured by an element such as a bipolar transistor. (2) NMOSs 22-0 to 22-i shown in FIGS. 5 and 8
Is an OR gate having i + 1 input terminals and one N gate.
It may be replaced with MOS. (3) The sense circuit of the present invention can be applied to a storage device other than the ROM or including the other.

[0016]

As described in detail above, according to the first aspect of the invention, the conduction state is controlled based on the precharge signal, and when the conduction state is established, the second input terminal of the sense amplifier and the power supply potential are separated from each other. A second MOS transistor which conducts, a reference potential generating means, and a third MOS which operates complementarily to the second MOS transistor and conducts the second input terminal and the reference potential generating means when in a conducting state. And a reference potential generating means for causing the reference potential generating means to make the potential drop of the second input terminal due to the discharge slower than the potential drop of the bit line when the second MOS transistor is turned off. Since it has a sense circuit that compares the bit line potential and the reference potential,
High-speed reading of ROM data can be realized with a simple circuit configuration and low power consumption. According to the second invention, the third MO whose conduction state is controlled based on the potential of one activated word line of the plurality of word lines in the memory cell array.
Since the S transistor is provided, the discharge start time difference between the bit line and the reference potential line due to the wiring capacitance of the word line selector and the word line itself and the element delay is eliminated. Therefore, erroneous data output due to the potential of the reference potential line temporarily lowering with respect to the potential of the bit line being discharged can be prevented. According to the third invention, the first and second M
Since the OS transistor is composed of NMOS, the charge level of the bit line and the reference potential line becomes VCC-VT, and there is no time for the potential of the bit line to drop from VCC to VCC-VT. Therefore, the read time of ROM data can be shortened. According to the fourth invention, even in a ROM having a plurality of outputs, since only one second MOS transistor and reference potential generating means are required, it is possible to reduce the ROM formation area.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a sense circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional sense circuit.

FIG. 3 is a circuit diagram of the memory cell array in FIG.

FIG. 4 is a time chart of FIG.

FIG. 5 is a circuit diagram showing a sense circuit according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a sense circuit according to a third embodiment of the present invention.

7 is a circuit diagram of a sense amplifier 15A in FIG.

FIG. 8 is a circuit diagram showing a sense circuit according to a fourth embodiment of the present invention.

[Explanation of symbols]

10A, 10B, 10C, 10D Sense circuit 13, 16 P
MOS 13A, 13A0 to 13Aj, 16A, 18, 22-0
22-j NMOS 15A Sense amplifier 19 Reference potential generation circuit 19a Reference potential generation section 19b Internal impedance

Claims (4)

[Claims] 1. A first input terminal and a second input terminal, the first input terminal
A sense amplifier that detects a potential difference between the potential of the bit line input to the input terminal and the reference potential input to the second input terminal; and a conductive amplifier based on a precharge signal. Selecting a memory cell array having a plurality of word lines and bit lines based on a change in the potential of the activated bit line. In the sense circuit of the read-only memory that determines the data held in the stored memory cell, the conduction state is controlled based on the precharge signal,
A second MOS transistor which conducts the second input terminal and the power supply potential in a conductive state; a reference potential generating means which generates a reference potential; and a complementary operation for the second MOS transistor. And a third MOS transistor which conducts the second input terminal and the reference potential generating means when the second MOS transistor is in an off state. A sense circuit for a read-only memory, characterized in that it has an internal impedance that makes the drop of the potential of the second input terminal due to the discharge slower than the drop of the potential of the bit line. 2. A first and a second input terminal are provided, and the first input terminal is provided.
A sense amplifier that detects a potential difference between the potential of the bit line input to the input terminal and the reference potential input to the second input terminal; and a conductive amplifier based on a precharge signal. Selecting a memory cell array having a plurality of word lines and bit lines based on a change in the potential of the activated bit line. In the sense circuit of the read-only memory that determines the data held in the stored memory cell, the conduction state is controlled based on the precharge signal,
A second MOS transistor which conducts the second input terminal and the power supply potential when in a conductive state, a reference potential generating means which generates a reference potential, and a plurality of word lines which are selectively activated. The conduction state is controlled based on the potential of one word line, and the second
A third MOS transistor that operates in a complementary manner to the MOS transistor and electrically connects the second input terminal and the reference potential generating means when the MOS transistor is conductive. A read-only memory having an internal impedance that makes the drop of the potential of the second input terminal due to discharge slower than the drop of the potential of the bit line when the second MOS transistor is turned off. Sense circuit. 3. The sense circuit of a read-only memory according to claim 1, wherein the first and second MOS transistors are N-channel MOS transistors. 4. A first input terminal and a second input terminal, respectively, and a bit line potential input to the first input terminal and a common reference potential input to the second input terminal, respectively. A plurality of word lines and a plurality of word lines and a plurality of word lines and bit lines are connected to each other in common to connect the selected memory cells in the memory cell array group. A sense amplifier, a plurality of first N-channel MOS transistors that conduct based on a precharge signal and that precharge by connecting the first input terminal to a power supply potential when in a conductive state; The conduction state is controlled based on
A second N-channel MOS transistor that conducts the plurality of second input terminals and the power supply potential when in a conductive state; a reference potential generating unit that generates a reference potential; and a selective one of the plurality of word lines. The conduction state is controlled based on the potential of the word line activated to the second N
A third MOS transistor, which operates complementarily to the channel type MOS transistor and electrically connects the plurality of second input terminals and the reference potential generating means when in a conductive state, is provided. Is an internal impedance that makes the potential drop of the plurality of second input terminals due to discharge slower than the potential drop of the plurality of bit lines when the second N-channel MOS transistor is turned off. A sense circuit of a read-only memory characterized by having.