WO1982001795A1 - Circuit tampon pour memoire a semi-conducteur - Google Patents

Circuit tampon pour memoire a semi-conducteur Download PDF

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Publication number
WO1982001795A1
WO1982001795A1 PCT/US1980/001495 US8001495W WO8201795A1 WO 1982001795 A1 WO1982001795 A1 WO 1982001795A1 US 8001495 W US8001495 W US 8001495W WO 8201795 A1 WO8201795 A1 WO 8201795A1
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WO
WIPO (PCT)
Prior art keywords
node
terminal connected
transistor
voltage
nodes
Prior art date
Application number
PCT/US1980/001495
Other languages
English (en)
Inventor
Corp Mostek
Original Assignee
Plachno Robert S
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plachno Robert S filed Critical Plachno Robert S
Priority to PCT/US1980/001495 priority Critical patent/WO1982001795A1/fr
Priority to EP19810901370 priority patent/EP0064977A1/fr
Publication of WO1982001795A1 publication Critical patent/WO1982001795A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals

Definitions

  • the present invention pertains to semiconductor memory circuits and more particularly to such a circuit which has a chip enable function to reduce the power consumption of the memory circuit.
  • An illustrative embodiment of the present invention utilizes a method and apparatus for controlling a plurality of power transfer transistors which supply power to operate semiconductor integrated circuits which can be "powered down" when not immediately needed.
  • Circuitry is provided for charging a node which is connected to control the state of the power transfer transistors, the charging of the node carried out in response to a first enable signal.
  • a second enable signal discharges the node down to a predetermined voltage.
  • Further circuitry couples a negatively going clock signal to the node to drive the node to a voltage below the predetermined voltage whereby the power transfer transistors are rendered nonconductive.
  • FIGURE 1 is a schematic illustration of a chip enable buffer circuit for use in accordance with the present invention.
  • FIGURE 2 is a illustration of wave forms at selected nodes for the circuit shown in FIGURE 1.
  • FIGURE 1 there is illustrated a chip enable circuit 10.
  • the circuit 10 supplies power to various portions of a semiconductor memory circuit (not shown) .
  • the power for the various elements in the memory circuit is transferred through a plurality of transistors such as 12 and 14.
  • the transistors 12 and 14 are fabricated to be natural field effect transistors as opposed to being either enhancement or depletion mode transistors. Therefore transistors
  • transistors 12 and 14 have essentially a zero threshold voltage and are turned off when the gate terminal is at essentially zero volts relative to the source terminal.
  • the parts of the semiconductor memory which are powered through the natural transistors 12 and 14 are deactivated whenever the gate terminals of the transistors are driven to zero voltage or below.
  • the gate terminals of transistors 12 and 14 will be driven to essentially the supply voltage cc , but when it is desired to deactivate elements of the semiconductor me ⁇ iory- the gate terminals of transistors 12 and 14 will be driven slightly negative to insure that the transistors are fully turned off and that no power is being supplied to the elements., in the semiconductor memory. This reduces the total power consumption of the integrated circuit incorporating circuit 10.
  • transistors 12 and 14 are connected to a node which is charged to selected voltages to turn transistors 12 and 14 on and off.
  • a chip enable (CE) signal is supplied through a line 16 to the gate terminal of a transistor 18.
  • the wave form for signal CE is illustrated in FIGURE 2.
  • the drain terminal of transistor 18 is connected to the voltage source V and the source terminal of transistor 18 is connected to a node 20.
  • a signal CE which is the inverse of signal CE, is supplied to the gate terminal of a transistor 22.
  • the drain terminal of transistor 22 is connected to node 20 and the source terminal of transistor 22 is connected to a node 24.
  • a transistor 26 has the drain terminal connected to node 24 and the source terminal connected to a common ground node V ⁇ The gate terminal of transistor 26 is connected to a node 28.
  • a capacitor 30 is fabricated essentially as a transistor which has the source and drain terminals connected together. The gate terminal forms a first terminal of the capacitor and this gate terminal is connected to receive a clock signal $C2. The remaining terminal of capacitor 30 is connected to node 20.
  • a dynamic keeper circuit 36 is provided for node 20.
  • Circuit 36 includes a capacitor 38 which has a gate terminal lead connected to a node 40 and the remaining lead connected to receive an oscillatory signal ⁇ .
  • Capacitor 38 is fabricated from an enhancement mode transistor. Signal ⁇ is illustrated in FIGURE 2 and is an asynchronous oscillatory signal.
  • a transistor 42 has the gate terminal connected to node 40, the drain terminal is connected to the voltage source V and the source terminal is connected to node 20.
  • a transistor 44 has the drain terminal connected to node 40, the gate terminal connected to the source administratc postalc and the source terminal connected to node 20.
  • the keeper circuit 36 holds node 20 at the full supply voltage V when the node 20 has previously been driven to a relatively high voltage state t effectively V .
  • the keeper circuit 36 When node 20 is discharged the keeper circuit 36 has essentially no effect on node 20.
  • node 20 When node 20 is at a relatively low voltage such that transistor 44 is turned on, node 40 is held at ground, V • When node 40 is grounded the signal ⁇ 6p cannot charge node 40. But when node 20 is at approximately V transistor 44 is turned off and the positive transitions at jp are coupled through capacitor 38 to turn dn transistor 42 which in turn causes node 20 to be charged to V .
  • the input terminal of a Schmidtt trigger inverter circuit 46 is connected to node 20 and the output of circuit 46 is connected to a node 48.
  • a transistor 50 has a source and drain terminals thereof connected between node 20 and a node 52 respectively.
  • the gate terminal of transistor 50 is " connected to node 48.
  • Node 52 is further connected to the gate terminal of a transistor 54 which has the drain terminal connected to v cc an ⁇ ⁇ the source terminal connected to a node 56.
  • a capacitor 58 is connected between node 52 and node 56 with the gate terminal of the capacitor connected to node 52.
  • Node 56 is connected to the drain terminal of a transistor 60 which has the gate terminal connected to node 48 and the source terminal connected to the common Node 52 is connected to the gate terminal of a transistor 62 which has the drain terminal connected to the voltage source V and the source terminal connected to a node 64.
  • a transistor 66 has the gate terminal connected to node 28, the source terminal connected to common node ss «
  • a transistor 68 has the drain and source terminals connected between node 64 and the drain terminal of transistor 66 respectively. The gate terminal of transistor 68 is connected to receive the CE signal.
  • Node 64 is provided with a keeper circuit 70 which is the same as keeper circuit 36 described above.
  • Keeper circuit 70 includes a capacitor 72, a central node 74, a transistor 76 and a transistor 78 which corresponds to capacitor 38, central node 40, transistor 42 and transistor 44 respectively.
  • a transistor 80 has the gate terminal connected to node 64, the drain terminal connected to the voltage source Vc,c ⁇ and the source terminal connected to node 28.
  • a further transistor 82 has the drain terminal connected to node 64, the source terminal connected to node 28 and the gate terminal connected to receive a clock signal jz.Cl.
  • the gate terminal of a capacitor 84 is connected to receive the clock signal ⁇ Z2 and the remaining terminal of capacitor 84 is connected to node 64.
  • Node 64 is further connected to the gate terminals of the natural transistors 12, 14 and others (not shown).
  • All of the capacitors 30, 38, 58, 72 and 84 are essentially transistors which have the source and drain terminals fixed together and serving a one capacitor terminal with the gate serving as the remaining capacitor terminal.
  • FIGURE 2 A number of significant wave forms which are utilized or occur in circuit 10 are illustrated in FIGURE 2. These wave forms include the signals CE and
  • CE together with the clock signals C1 and j_C2. Further wave forms are illustrated to show the voltage levels and transitions at nodes 20, 28, 52 and 64. The oscillatory wave form ⁇ is also illustrated. Operation of the chip enable buffer circuit of the present invention is now described in reference to FIGURES 1 and 2. As noted above it is the purpose of the circuit 10 to drive the gate terminals of transistors 12 and 14 to at least a slightly negative level, below v ss ' to insure that these transistors are fully turned off and therefore no current is being supplied to the
  • transistors 12 and 14 The gate terminals of transistors 12 and 14 are subsequently driven to a negative level when the signal CE goes to a high level.
  • the signal CE is supplied from a user to the circuit
  • the signals CE and CE * are provided by the external circuitry and may be specified to be less than the full extremes of the supply voltage. Should this be the case the signals CE and CE are conditioned to have voltages which are either at the zero voltage level or at V or above when input to circuit 10.
  • the clock signals C1 and C2 are generated in a time delayed sequence from either the signal CE or the signal CE.
  • the clock signals C1 and C2 occur only after the negative transition of the signal CE and the positive transition of signal CE. The generation of such clock signals is well known in the art.
  • the signal CE When the semiconductor memory circuit array (not shown) is fully active the signal CE is in a high state and the signal CE is in a low state. At this time the clock signal C1 is in a low state and the clock signal ⁇ Q.2 is at a high state.
  • Node 20 is primarily charged by the action of transistor 18 which is rendered conductive by the signal CE to supply charge from the voltage source V .
  • the keeper circuit 36 operates to pull the voltage on node 20 up to the full supply voltage V and hold it there. During the sequence of operation the node 52 is charged to an incremental voltage ⁇ above the voltag -* • e source Vcc as described below.
  • the high voltage state on node 52 renders transistor 62 conductive to substantially charge node 64.
  • the keeper circuit 70 further pulls the voltage of node 64 to the full supply voltage V .
  • the node 28 is connected through the transistor 80 to the voltage source V_ •
  • the charge on node 64 tends to drive transistor 80 conductive to connect node 28 to V . But since the gate terminal of transistor 80 is at V , the voltage on node 28 is held to one threshold voltage (V. ) below the voltage supply cc
  • transistor 18 When the signal CE transitions from the high level to the low level the transistor 18 is rendered non- conductive thereby isolating node 20 from the voltage source V • When the signal CE transitions from the' low level to the full supply voltage cc , transistor
  • Transistors 26 and 66 remain conductive as long as node 28 is charged. But when the clock signal -zfCl transitions from the low to the high voltage state transistor 82 is turned on thereby connecting node 28 to node 64. Since node 64 has previously been discharged and is connected to ground, node 28 will likewise be discharged and pulled to essentially a zero volt level. As node 28 is being discharged transistors 26 and 66 will be turned off.
  • nodes 20, 52, 64 and 28 have been discharged.
  • Nodes 20 and 52 are connected to- each other but isolated from the remainder of the circuit while node 64 is also isolated.
  • the clock signal ⁇ C2 makes a negative transition nodes 20 and 52 will be driven negative by capacitive coupling through capacitor 30.
  • Node 20 can be driven negative for only one V t below V ss due to the action of transistor 18. If node 20 should go any lower than one Vt. below Vs slaughters terme transistor 18 would be rendered conductive thereby pulling node 20 back up in voltage until transistor 18 is again turned off. Thus node 20 is clamped at 1 V. below zero volts, wherein V ss is defined as zero volts.
  • nodes 20 and 52 are connected because transistor 50 is rendered conductive by the output signal produced by circuit 46.
  • node 52 is driven to the same voltage state as node 20.
  • Node 64 is likewise driven negative by the operation of the clock signal ⁇ C2 working through capacitor 84.
  • Node 64 is d-riven to two voltage thresholds be-low V ss « This is a result of the gate terminal of transistor 62 being held at 1 V. •w_ below VDO.
  • Node 64 can be driven to only one more V fc below the zero voltage of V ss since to drive this node any further negative would cause transistor 62 to become conductive and pull the voltage on node 64 upward. Thus node 64 is clamped at a voltage of 2 v fc below V ss -
  • node 64 is connected to the gate terminals of transistors 12, 14 and other similar transistors, these natural transistors will be affirmatively -turned off thereby preventing essentially any current flow to the elements connected to these transistors.
  • transistor 18 When signal CE transitions from the low state to the high state transistor 18 is rendered conductive thereby charging node 20 to essentially V •
  • the Schmidtt trigger inverter circuit 46 drives its output to a low level thereby turning off transistors 50 and 60.
  • the delay due to the hystersis of circuit 46 ' permits node 52 to be charged before transistor 50 is turned off. This serves to isolate node 20 from node 52 and to disconnect the capacitor 58 from connection to the ground node V •
  • transistor 54 When node 52 rises in voltage, transistor 54 will be rendered conductive and the source terminal of transistor 54 will be pulled to near the supply voltage V .
  • This sudden rise in voltage at node 56 causes a coupling effect through capacitor 58 which causes node 52 to be elevated above the supply voltage V__ by a voltage differential ⁇ .
  • the capacitive coupling effect is shown as a small step in the positive going section of the wave form for node 52 in FIGURE 2.
  • transistor 62 When node 52 is driven to a high level, transistor 62 will be rendered conductive thereby charging node 64 to essentially the supply voltage V .
  • the keeper circuit 70 will pull the node 64 to the full supply voltage VvC•
  • transistor 80 When node 64 is driven to a higher voltage state, transistor 80 is turned on thereby charging node 28 to one voltage threshold below V •

Abstract

Un circuit tampon (10) recoit un signal de validation pour actionner des transistors de transfert de puissance (12, 4) qui alimentent en courant des elements de circuit dans une memoire a semi-conducteur. Lorsqu'un signal de validation est entraine sur un etat eleve les bornes de porte des transistors de transfert de puissance (12, 14) seront commandees sur le positif rendant ainsi les transistors conducteurs. Lorsque les signaux de validation passent a un etat de basse tension un premier et un second signaux d'horloge (oC1 et oC2) sont generes. L'action des signaux d'horloge sert a tirer un noeud (20) sur un seuil de tension inferieur a la tension de reference Vss. Un second noeud (64) est amene sur deux seuils sous la reference de Vss. Le second noeud (64) est connecte a la borne de porte des transistors de transfert de puissance (12, 14) pour maintenir effectivement les transistors de transfert de puissance (12, 14) dans un etat de non conduction pour bloquer essentiellement le transfert de tout courant au travers de ces transistors vers les elements de circuit de la memoire a semi-conducteur eliminant ainsi toute perte de courant due a des fuites de courant par les transistors de transfert de puissance (12, 14).
PCT/US1980/001495 1980-11-07 1980-11-07 Circuit tampon pour memoire a semi-conducteur WO1982001795A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US1980/001495 WO1982001795A1 (fr) 1980-11-07 1980-11-07 Circuit tampon pour memoire a semi-conducteur
EP19810901370 EP0064977A1 (fr) 1980-11-07 1980-11-07 Circuit tampon pour memoire a semi-conducteur

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
WOUS80/01495801107 1980-11-07
PCT/US1980/001495 WO1982001795A1 (fr) 1980-11-07 1980-11-07 Circuit tampon pour memoire a semi-conducteur

Publications (1)

Publication Number Publication Date
WO1982001795A1 true WO1982001795A1 (fr) 1982-05-27

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Application Number Title Priority Date Filing Date
PCT/US1980/001495 WO1982001795A1 (fr) 1980-11-07 1980-11-07 Circuit tampon pour memoire a semi-conducteur

Country Status (2)

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EP (1) EP0064977A1 (fr)
WO (1) WO1982001795A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0092809A2 (fr) * 1982-04-24 1983-11-02 Kabushiki Kaisha Toshiba Circuit logique avec augmentation de tension
US6711719B2 (en) * 2001-08-13 2004-03-23 International Business Machines Corporation Method and apparatus for reducing power consumption in VLSI circuit designs

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3778784A (en) * 1972-02-14 1973-12-11 Intel Corp Memory system incorporating a memory cell and timing means on a single semiconductor substrate
US3906464A (en) * 1974-06-03 1975-09-16 Motorola Inc External data control preset system for inverting cell random access memory
US4019068A (en) * 1975-09-02 1977-04-19 Motorola, Inc. Low power output disable circuit for random access memory
US4259594A (en) * 1979-09-17 1981-03-31 Gte Laboratories Incorporated Electrical power supply apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3778784A (en) * 1972-02-14 1973-12-11 Intel Corp Memory system incorporating a memory cell and timing means on a single semiconductor substrate
US3906464A (en) * 1974-06-03 1975-09-16 Motorola Inc External data control preset system for inverting cell random access memory
US4019068A (en) * 1975-09-02 1977-04-19 Motorola, Inc. Low power output disable circuit for random access memory
US4259594A (en) * 1979-09-17 1981-03-31 Gte Laboratories Incorporated Electrical power supply apparatus

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, Volume 21, No. 4, issued September 1978, GRAYet al, 'Power Supply Stabilization Circuit', see pages 1384 to 1385. *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0092809A2 (fr) * 1982-04-24 1983-11-02 Kabushiki Kaisha Toshiba Circuit logique avec augmentation de tension
EP0092809A3 (en) * 1982-04-24 1984-02-22 Tokyo Shibaura Denki Kabushiki Kaisha Logic circuit having voltage booster
US4612462A (en) * 1982-04-24 1986-09-16 Tokyo Shibaura Denki Kabushiki Kaisha Logic circuit having voltage booster
US6711719B2 (en) * 2001-08-13 2004-03-23 International Business Machines Corporation Method and apparatus for reducing power consumption in VLSI circuit designs

Also Published As

Publication number Publication date
EP0064977A1 (fr) 1982-11-24

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