WO1982000917A1 - Circuit de vieillissement accelere de bande - Google Patents

Circuit de vieillissement accelere de bande Download PDF

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Publication number
WO1982000917A1
WO1982000917A1 PCT/US1980/001149 US8001149W WO8200917A1 WO 1982000917 A1 WO1982000917 A1 WO 1982000917A1 US 8001149 W US8001149 W US 8001149W WO 8200917 A1 WO8200917 A1 WO 8200917A1
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WIPO (PCT)
Prior art keywords
burn
gate
row
receive
signal
Prior art date
Application number
PCT/US1980/001149
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English (en)
Inventor
Corp Mostek
Original Assignee
Proebsting R
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Proebsting R filed Critical Proebsting R
Priority to PCT/US1980/001149 priority Critical patent/WO1982000917A1/fr
Priority to EP19810901719 priority patent/EP0059188A1/fr
Publication of WO1982000917A1 publication Critical patent/WO1982000917A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing

Definitions

  • the present invention pertains to semiconductor integrated circuits and more particularly to a circuit for burn-in operation of such circuits for minimizing the number of external inputs required for burn-in operation.
  • Integrated semiconductor circuits have the potential for operating for long periods of time without failure. However, a substantial percentage of such circuits fail within the first few hours or days of operation due to marginal defects in manufacture. Such marginal circuits frequently test good under initial screening, but fail shortly thereafter. It is therefore incumbent upon the manufacturer of such circuits to burn-in each of the circuits for a period of time at elevated voltages and temperatures to cause failure of the marginal circuits before shipment. Without burn-in a substantial number of marginal circuits could be shipped to users and these circuits would be installed in the user's products only to fail a short time later. A failure of a component under such circumstances has severe economic impacts on both the user and the producer of integrated circuits.
  • integrated circuits have been burned-in after the circuits have been packaged in the manner that they will be delivered to the customer.
  • a group of packaged circuits are mounted on a convential circuit board which has a plurality of sockets.
  • the board is then placed in an oven for operating the circuits under stress.
  • the integrated circuits are cycled through their operational states while an elevated voltage is supplied thereto and the temperature is set to a stress level.
  • the burn- in of each individual circuit is essential but this is a very expensive process.
  • a circuit for burning-in an integrated circuit which has a first set of terminals for receiving signals for normal operation of the integrated circuit.
  • the burn-in circuit receives an externally produced burn-in command and generates a test signal.
  • the burn-in circuit receives signals through a second set of terminals, which may comprise a subset of the first set of terminals, to exercise the majority of the components of the integrated circuit.
  • the second set comprises fewer terminals than the first set and the second set has, for example, four terminals.
  • FIGURE 1 is a plan view of a burn-in tape having an integrated circuit semiconductor memory connected thereto;
  • FIGURE 2 is a schematic diagram of a burn in circuit for use in conjunction with the tape of the present invention.
  • a procedure termed "tape bonding" has been widely used in the semiconductor industry for connecting bonding pads on an integrated circuit to the pins in the circuit package.
  • the burn- in tape of the present invention is illustrated in reference to "FIGURE 1.
  • the wafer is cut to separate each of the circuits to be an individual chip.
  • An individual semiconductor memory chip produced in this fashion is shown by reference numeral 10.
  • chip 10 is provided with a plurality of bonding pads 12-46, each of which provides a connection to the circuit included on chip 10.
  • the bonding process is carried out with a continuous tape 48 which comprises an insulating backing 50 together with a single layer of metallization which has been etched to produce a plurality of conductor lines.
  • the tape 48 is provided with continuous power bus lines 52 and 54 which in most applications are designated as the supply voltage bus and ground.
  • Tape 48 is provided with openings 56 and 58 on either side of a bridge 60.
  • the metallization pattern on tape 48 includes a plurality of conductive leads which extend from tape 48 into the openings 56 and 58. One lead is provided for each of the bonding pads on the chip 10. Leads 52-78 are connected respectively to bonding pads 12-28. Likewise, leads 80-96 are connected respectively to bonding pads 30-46. The signal conducting leads 62-68, 72-78, 80-86 and 90-96 are each connected to a corresponding test pad 62a-68a, 72a-78a, 80a-86a and 90a-96a on tape 48. Test probes (not shown) are placed in contact with the test pads to control and test the operation of the integrated circuit while mounted on the tape 48. Tape 48 is provided with sprocket holes 98 which engage sprockets that move the tape into an accurate position for automatically bonding the leads to the bonding pads of the integrated circuit, and for aligning the tape to receive test probes.
  • the integrated circuit 10 is connected to the extending leads as shown in FIGURE 1 and the leads are then severed along dotted lines 100 and 102 for disconnecting chip 10 from tape 48 and thereby providing the chip with lines for connection to the pins in the chip package.
  • the various leads are simultaneously bonded to pads in a package which are in turn connected to the pins which extend from the package to enable electrical connection from the chip to a printed circuit board.
  • the tape bonding procedure has been used solely as a method for rapidly and inexpensively connecting bonding leads to the integrated circuit. But in the present invention, the use of the tape is expanded and additional conductor lines are added to the tape such that the memory chip 10 can be burned-in while it is attached to the tape.
  • Such burning-in can be carried out when the chip 10 itself is provided with additional circuitry to permit operation without connections to all inputs 12-46 of the circuit 10.
  • line 104 is connected to bonding pad 12 through lead 62 and line 106 is connected to bonding pad 30 through lead 80.
  • the chip 10 is provided with four connections thereto, the two control lines 104 and 106 together with the power lines 52 and 54.
  • none of the conductor lines on tape 48 cross so that there can be etched out of a single conductive layer.
  • the configuration of tape and conductors illustrated in FIGURE 1 is repeated along tape 48 such that a plurality of integrated circuits can be burned-in simultaneously.
  • the chip 10 has the bonding pads fabricated at opposing ends of the chip. With this fabrication configuration the maximum number of conductors which can be fabricated on tape 48 to extend along the length of the tape without crossovers and using only a single layer of metallization is four.
  • the chip 10 is an integrated circuit which has a first set of terminals selected from the bonding pads 12-46 normally used to receive power, addresses, data and operational command signals to operate the circuit. With the present invention the chip 10 can be exercised through a second set of terminals selected from the bonding pads 12-46. The second set of terminals may or may not include terminals in the first set.
  • the chip 10 is typically a memory circuit but other types of integrated circuits, such as microprocessors, can equally well be exercised in this manner.
  • FIGURE 2 The circuit for use in conjunction with the signals transmitted over lines 104 and 106 for burning-in semiconductor chip 10 is illustrated in FIGURE 2.
  • Voltage states representing binary information are supplied to a memory array 107 through input/output lines 108 and 110. These lines are connected through column select transistors 112 and 114 to digit lines 116 and 118. Column select signals are provided to activate transistors 112 and 114 to connect the input/output lines 108 and 110 to the corresponding digit lines 116 and 118.
  • Capacitors 120 and 122 are illustrative of the plurality of storage capacitors included within a semiconductor memory.
  • An access transistor 124 connects capacitor 120 to digit line 116.
  • the gate terminal of transistor 124 is connected to a word line 126 which receives commands to activate transistor 124 and thereby connect capacitor 120 to digit line 116.
  • the terms word line and row line are interchangable.
  • an access transistor 128 connects capacitor 122 to digit line 118.
  • a word line 130 is connected to the gate terminal of transistor 128 to control the operation thereof and selectively connect capacitor 122 to digit line 118.
  • a plurality of access transistors and corresponding memory cells are connected along each of the word lines 126 and 130 within the semiconductor memory.
  • a word line such as 126
  • all of the access transistors along the word line will be simultaneously activated to connect the corresponding storage capacitors to the corresponding digit lines.
  • only one memory cell is connected to a digit line at any one given time.
  • Each pair of digit lines, such as 116 and 118 are connected to a sense amplifier such as amplifier 132.
  • a transistor 134 is provided for connecting amplifier 132 to digit line 116 and a transistor 136 is provided for connecting digit line 118 to amplifier 132.
  • Sense amplifier 132 comprises transistors 138 and 140 which have the source terminals thereof connected in common to a latch node 142.
  • the drain terminal of transistor 138 and the gate terminal of transistor 140 are connected to transistor 134 while the drain terminal of transistor 140 and the gate terminal of transistor 138 are connected to transistor 136.
  • the voltages on digit lines 116 and 118 are equalized by operation of precharge transistors 144 and 146.
  • the drain and source terminals of transistor 144 are connected between digit line 116 and the latch node 142 and the source and drain terminals of transistor 146 are connected between digit line 118 and latch node 142.
  • a precharge signal is provided to the gate terminals of transistors 144 and 146 to turn these transistors on and equilibrate the voltages on lines 116 and 118 between memory cycles.
  • Each of the digit lines in the semiconductor memory is provided with a pullup circuit such as circuit 148 shown in FIGURE 2.
  • Pullup circuit 148 includes a transistor 150 which has the source terminal connected to digit, line 116 and the drain terminal connected to a node 152.
  • the gate terminal of transistor 150 is connected to receive a P o signal.
  • a transistor 154 has the source terminal connected to node 152 and the drain terminal connected to the power supply V cc .
  • the gate terminal of transistor 154 is connected to receive a P signal.
  • Pullup circuit 148 further includes a transistor 156 which has the gate terminal thereof connected to node 152 and the drain terminal thereof connected to receive a P 1 signal.
  • the source terminal of transistor 156 is connected to the gate terminal of a transistor 158.
  • the drain terminal of transistor 158 is also connected to the power supply V cc while the source terminal of transistor 158 is connected to digit line 116.
  • a pullup circuit such as circuit 148 is connected to each of the digit lines within the memory circuit, such a duplication of circuits is indicated by lines 160 and 162 connected to digit line 118.
  • the operation of the memory circuit 107 is described in reference to FIGURE 2.
  • the voltages on digit lines 116 and 118 are equilibrated by operation of precharge transistors 144 arid 146. These transistors are activated by a precharge signal which is applied to the gate terminals thereof to cause the transistors to be rendered conductive.
  • the latch node 142 is connected to the digit lines 116 and 118. This connection causes the voltages on lines 116 and 118 to be eventually balanced and have approximately the same charge thereon.
  • the voltage on lines 116 and 118 is driven to 2.0 volts by operation of the precharge transistors.
  • a signal is applied to the word line 126 to cause activation of access transistor 124 which then connects digit line 116 to capacitor 120. If a high voltage state has previously been stored on capacitor 120, the digit line 116 is elevated by a few tenths of a volt. But if a low voltage state has previously been stored on capacitor 120, the digit line 116 will be reduced in voltage by a few tenths of a volt. After a memory cell is connected to a digit line, one of the digit lines 116 and 118 will have a lesser voltage thereon.
  • a latch signal is applied to the latch node 142 of sense amplifier 132. This signal descends relatively slowly from an initial voltage state to a low voltage state. During the downward transistion of the signal on latch node 142, one of the two transistors 138 or 140 will be gradually turned on to cause the digit line connected to the conductive transistor to be discharged. The line with the lesser voltage will be discharged through the latch node to essentially zero volts. The digit line with the greater voltage will not be discharged.
  • sense amplifier 132 causes the small voltage differential produced by a storage capacitor to be transformed into a substantial voltage differential between digit lines 116 and 118 and this voltage differential can be transmitted to the input/output lines 108 and 110 through the column select transistors.
  • the pullup circuit 148 is activated by a sequence of the signals P, P o and P 1 .
  • the P signal is supplied initially to precharge node 152 and is turned off before occurance of the other signals.
  • the P o signal follows the P signal and goes from 0.0 volts to approximately 1.0 volts.
  • transistor 150 will be turned on by signal P o thereby discharging node 152. But if digit line 116 has remained at a charged state of approximately 2.0 volts, transistor 150 will not be turned on and node 152 will remain charged at its initial 5.0 volt level.
  • the P 1 signal arrives after the P o signal and the P 1 signal is transmitted to the gate terminal of transistor 158 if node 152 has not been discharged.
  • signal P 1 is applied to the gate of transistor 158 the supply voltage V cc is coupled to digit line 116. This line is then pulled to the full supply voltage.
  • the pullup circuit 148 causes the digit line with the remaining elevated voltage to be pulled to the full voltage state of the supply voltage V cc .
  • the digit line discharged by the sense amplifier 132 will not be affected by operation of pullup circuit 148. While the pullup operation is occurring, an elevated voltage is applied to word line 126 to transfer the voltage state on digit line 116 into the storage capacitor 120.
  • the burn in circuit for use with the memory array circuit 107 is now described in reference to FIGURE 2.
  • the conductor line 104 on tape 48 is connected to a burn-in terminal 168 while the conductor line 106 is connected to the refresh terminal 170.
  • the memory 107 operates in the normal sense in response to a (row address strobe) signal which is received at terminal 172 and a (column address strobe) signal which is received at terminal 174.
  • the signals When the memory circuit 100 is installed as a part of a user's device, the signals , and will be supplied from external circuitry to control operation of the memory circuit 107.
  • the signal going to a logical 0 causes generation of row clock chain signals by the row clock chain generator 176.
  • the signal going to a logical 0 in conjunction with a logical 0 on the signal produces column clock chain signals by activation of a column clock chain generator 178.
  • the burn-in terminal 168 is connected as a first input to a NOR gate 176.
  • the second input to gate 176 is connected to the terminal 172.
  • the output of NOR gate 176 is connected as a first input to a NOR gate 178 which. has the burn-in signal on line 168 provided as the second input thereto.
  • the CAS signal is provided through terminal 174 to a first input of a NOR gate 180.
  • the output of NOR gate 178 is connected at the second input to gate 180.
  • the burn- in signal transmitted through terminal 168 is also connected as a first input to a NOR gate 182 which receives the output of gate 180 as the second input.
  • NOR gate 182 The output of NOR gate 182 is provided as a first input to a NOR gate 184 which has the output thereof connected to drive the column clock chain generator 178.
  • the refresh signal on terminal 170 is connected to the input of an inverter 186 which has the output thereof connected as the first input to a NOR gate 188.
  • the second input to NOR gate 188 is received from the output of NOR gate 176.
  • the output from NOR gate 188 is provided as a second input to NOR gate 184 and as the input to inverter 190.
  • the row clock chain generator 176 is driven in response to the output from inverter 190.
  • the refresh signal, , provided on terminal 170 is transmitted to a refresh counter 192 that generates a sequence of addresses which are provided to row decoders 194 and column decoders 196.
  • the row decoders 194 select the addressed word lines within memory array 107 and the column decoders 196 activate the addressed column select transistors for each digit line, such as transistors 112 and 114.
  • a resistor 198 is connected between burn-in terminal 168 and ground to hold this terminal at ground potential when no input signal is supplied thereto.
  • Terminal 168 is further connected to a voltage divider network comprising resistors 200 and 202.
  • Resistor 202 has one terminal thereof connected to ground. Preferred values for these resistors are 3K ohms for resistor 200 and 6K ohms for resistor 202.
  • the junction of these two resistors is connected to the non-inverting input of a differential amplifier 204.
  • the inverting input of amplifier 204 is connected to the voltage source V cc .
  • the output of amplifier 204 is connected to the gate terminal of a transistor 206 which has the source terminal thereof grounded.
  • the drain terminal of transistor 206 is connected to a load resistor 208 which has the remaining terminal thereof connected to the supply voltage V cc .
  • the drain terminal of transistor 206 is also connected to the gate terminals of transistors 134 and 136, and all similar transistors throughout memory array 107.
  • the purpose of the present invention is to provide burn-in for the integrated circuit memory chip 10 while the circuit is attached to the tape 48. After the circuit has undergone burn-in, it is then tested while still mounted on tape 48 using pads 62a-68a, 72a-78a, 80a-86a and 90a-96a. If the circuit proves to be functional it is then, and only then, incorporated into a package to constitute the final product.
  • the integrated circuit chip 10. is bonded to the tape 48, four connections are made to the circuitry on the chip for burn in. The supply voltage and ground terminals are connected to the appropriate pads on the chip. Further, as noted above, line 104 is connected to the burn-in terminal 168 of the semiconductor memory circuit and the line 106 is connected to the refresh pin 170 for the circuit. After the circuit has been tested and packaged there will be no connection made to the burn-in terminal 168. With no connection to terminal 168, resistor 198 maintains a logic 0 on terminal 168.
  • a burn-in command is supplied to the burn-in terminal 168 during burn-in of the circuit 10.
  • This command has two active states; a first state, which is approximately 8.0 volts, is applied to cause a block write of a high voltage state into all of the memory cells in memory array 107, and a second state of approximately 5.0 volts is provided to sequentially exercise all rows and all columns of memory array 107.
  • the voltage at the junction of the voltage divider resistors 200 and 202 will be in excess of V cc which is normally 5.0 volts.
  • the output of differential amplifier 204 is normally a logical 0, but upon application of the high burn-in voltage, the output of differential amplifier 204 will transition from a logical 0 to a logical 1.
  • the transistor 206 is turned off, and resistor 208 supplies voltage V cc to the gate terminals of transistors 134 and 136. The application of this voltage to the gate terminals causes these transistors to be turned on and to connect sense amplifier 132 to digi t lines 116 and 118 .
  • the refresh counter 192 produces a sequence of all possible word line addresses to the memory array 107. Each time the refresh signal 170 is activated the word line corresponding to the refresh counter address is selected and the refresh counter is incremented to the next address. In normal operation this is used to refresh the logic states of all memory cells in array 107. When a cycle is initiated by the refresh command, if conditions are established for a column to be selected, the column address will be the same as the row address, both being provided by the refresh counter 192.
  • a clock signal applied to the refresh terminal 170 causes the refresh counter 192 to cycle through its various states.
  • Counter 192 produces in sequence each of the addresses for the row and column decoders in the memory circuit 107. In this case, the same address is applied to the row decoders 194 and the column decoders 196.
  • the burn-in terminal 168 is at a logical 1, the logic shown at the top of FIGURE 2, to be described below, causes the input 170 to select both the row and the column addressed by refresh counter 192.
  • the burn-in command when the burn-in command is at a logical 1, either 5.0 volts or 8.0 volts, and a sequence of clock signals is applied to the refresh line 170, the memory cells which have column address the same as row address will be sequentially addressed by the operation of the refresh counter.
  • the burn-in command is at the 8.0 volt level, as described above, all cells in a row are simultaneously written high. With the sequencing of the rows by the refresh counter 102, all cells in the memory array 107 are established at the high stress condition even though only the memory cells whose column address is identical to the row address are actually selected.
  • the sense amplifiers such as 132
  • all rows are sequentially operated to receive stress as are all columns and other elements such as clock generators, address buffers, row decoders, column decoders and memory cells.
  • the burn-in command on line 168 would normally be at 8.0 volts for sufficient refresh cycles to establish the high stress condition in all cells. Thereafter the burn-in command would be reduced to 5.0 volts to exercise essentially all of the elements of the integrated circuit for the duration of the burn-in.
  • the and signals In normal operation of the memory circuit, the and signals must be provided from external sources to cause operation of the row clock chain generator 176 and column clock chain generator 178. But in the burn-in condition for stressing the circuit, no input signals are provided on lines 172 and 174. Thus, the signal on the refresh pin must cause the equivalent result to receiving both and signals.
  • the signal produces two results when it is in the low (active) state. First, it activates the row clock chain generator 176 and second, it enables the operation of the signal. In normal operation the burn-in terminal 168 is pulled to a low level thereby causing
  • NOR gate 176 to operate as an inverter. Similarly, under such circumstances, the signal on terminal 170 is at a high state which is transformed to a low state at the output of inverter 186. This causes NOR gate 188 to function as an inverter as well. Thus, when the signal on line 172 is at a low state the output of NOR gate 176 is at a high state, the output of NOR gate 188 is at a low state and the output of inverter 190 is at a high state to activate row clock chain generator 176. Further, under normal operations, the NOR gate 176 to operate as an inverter. Similarly, under such circumstances, the signal on terminal 170 is at a high state which is transformed to a low state at the output of inverter 186. This causes NOR gate 188 to function as an inverter as well. Thus, when the signal on line 172 is at a low state the output of NOR gate 176 is at a high state, the output of NOR gate 188 is at a low state and
  • NOR gate 178 operates as an inverter and the signal inhibits the signal when the signal is in a high state.
  • the signal on terminal 172 is high, the output of NOR gate 176 is low and the output of NOR gate 178 is high thereby driving the output of NOR gate 180 low regardless of the state of the signal on line 174.
  • the high state on line 168 also drives the output of NOR gate 178 to a low state, the output of NOR gate 180 to a high state since is low and the output of NOR gate 182 to a low state This permits the remaining input to NOR gate 184 to control the output thereof. Therefore, when the signal on terminal 170 goes to a low state, the output of inverter 186 is driven high, the output of NOR gate 188 is driven low and the output of inverter 190 is driven high thereby activating row clock chain generator 176.
  • the output of NOR gate 188 is connected as an input to NOR gate 184. When this output goes low, the output of NOR gate 184 is driven high thereby activating the column clock chain generator 178.
  • the row and column clock chain generators will be activated by the signal transitioning from a high level to a low level. As toggles between these two states, the row and column clock chain signals are repeatedly generated. The toggling further causes the refresh counter 192 to generate sequential address signals that are applied to the row and column decoders 194 and 196.
  • the burn-in command to the burn-in terminal 163 is at the 5.0 volt level, the transistors 134 and 136 are rendered conductive thereby connecting the sense amplifier 132 to the digit lines 116 and 118.
  • the sense amplifier for each of the digit lines is likewise stressed and caused to operate in its normal manner.
  • the high state initially written into all the memory cells is maintained by these repetitive memory cycles.
  • the memory can be operated in the sequential mode in response to the clock signal provided to the terminal 170 to stress the memory cells, the sense amplifiers, the row and column clock chain circuitry, the row decoders, the column decoders, the data output circuit and the pullup circuits. All circuits so exercised constitute well over 99% of the circuit components within the semiconductor memory.
  • the burn-in command provided to the burn-in terminal 168 is elevated to the 8.0 volt level for approximately .25 milliseconds during which time the signal is clocked at least 256 times. In a memory circuit having this number of rows and columns, this operation will cause the high voltage state to be written into each of the memory cells. After the burn-in command is at the 3.0 volt level for .25 milliseconds, it is lowered to the 5.0 volt level.
  • the clock signal provided through the terminal 170 is clocked at the same rate as before to repeatedly stress the circuit components within the memory.
  • the sequence of burning-in is carried out for a period of hours at elevated temperatures to cause failure of. marginal chips and insure! the reliability of those. chips which successfully complete the burn-in.
  • the supply voltage V cc can be elevated at the same time to further stress the chips.

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  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

Un circuit de vieillissement accelere d'une memoire a circuit integre recoit un signal a deux etapes a une borne de vieillissement accelere (168). Un signal d'horloge de regeneration est fourni a une borne de regeneration (170) qui commande un compteur de regeneration (192). Une sequence d'adresses est produite par le compteur de regeneration (192) et envoyee au decodeur de rangees (194) et au decodeur de colonnes (196). Lorsque la commande envoyee a la borne (168) se trouve dans un premier etat, les amplificateurs de detection (132) a l'interieur d'un reseau de memoire (107) sont invalides de maniere telle que les circuits d'elevation (148) elevent les lignes de chiffres (116, 118) a un niveau eleve de tension. Le niveau eleve de tension est transfere dans des condensateurs de stockage de la cellule de memoire (120, 122). Lorsque la commande se trouve soit dans le premier soit dans le deuxieme etat, le signal de regeneration force un generateur de chaine d'horloge de rangee (176) a produire des signaux d'horloge de rangee et un generateur de chaine d'horloge de colonne (178) a produire des signaux d'horloge de colonne. Les adresses produites par le compteur de regeneration avec les signaux produits par les generateurs d'horloge de rangee et de colonne produisent le vieillissement des cellules de memoire (120), de l'amplificateur de detection (132) et des circuits associes a l'interieur du reseau de memoire (107). Le reseau de memoire (107) peut etre teste avec des signaux recus uniquement par l'intermediaire de quatre bornes afin de rendre possible le test simultane d'une pluralite de circuits integres sur une bande ne possedant pas de croisement de lignes conductrices.
PCT/US1980/001149 1980-09-08 1980-09-08 Circuit de vieillissement accelere de bande WO1982000917A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US1980/001149 WO1982000917A1 (fr) 1980-09-08 1980-09-08 Circuit de vieillissement accelere de bande
EP19810901719 EP0059188A1 (fr) 1980-09-08 1980-09-08 Circuit de vieillissement accelere de bande

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Application Number Priority Date Filing Date Title
PCT/US1980/001149 WO1982000917A1 (fr) 1980-09-08 1980-09-08 Circuit de vieillissement accelere de bande
WOUS80/01149800908 1980-09-08

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0108114A1 (fr) * 1982-05-17 1984-05-16 Motorola Inc Bloc pour test de controle accelere d'une memoire.
EP0456255A2 (fr) * 1990-05-11 1991-11-13 Kabushiki Kaisha Toshiba Dispositif de mémoire dynamique et méthode pour l'examiner
EP0492609A2 (fr) * 1990-12-27 1992-07-01 Kabushiki Kaisha Toshiba Dispositif à semi-conducteur comprenant des plages de test en tension élevée
EP0516364A2 (fr) * 1991-05-28 1992-12-02 Texas Instruments Incorporated Dispositif de mémoire à semi-conducteur comportant un circuit de test vieillissement
FR2693288A1 (fr) * 1992-07-06 1994-01-07 Sgs Thomson Microelectronics Mémoire comprenant un circuit d'adressage interne pour les tests en vieillissement.
EP0615253A2 (fr) * 1993-03-10 1994-09-14 Kabushiki Kaisha Toshiba Mémoire à semi-conducteur comportant un test de vieillissement
US5475646A (en) * 1992-08-31 1995-12-12 Kabushiki Kaisha Toshiba Screening circuitry for a dynamic random access memory
EP1136833A1 (fr) * 2000-03-23 2001-09-26 Infineon Technologies AG Procédé de vieillissement par stress électrique d'une mémoire semi-conducteur
US6781397B2 (en) * 1996-12-03 2004-08-24 Micron Technology, Inc. Electrical communication system for circuitry

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961251A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US3961252A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US4183096A (en) * 1978-05-25 1980-01-08 Bell Telephone Laboratories, Incorporated Self checking dynamic memory system
US4243937A (en) * 1979-04-06 1981-01-06 General Instrument Corporation Microelectronic device and method for testing same
JPH05222443A (ja) * 1992-02-07 1993-08-31 Kawasaki Steel Corp 加熱炉のスラブ装入装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961251A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US3961252A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US4183096A (en) * 1978-05-25 1980-01-08 Bell Telephone Laboratories, Incorporated Self checking dynamic memory system
US4243937A (en) * 1979-04-06 1981-01-06 General Instrument Corporation Microelectronic device and method for testing same
JPH05222443A (ja) * 1992-02-07 1993-08-31 Kawasaki Steel Corp 加熱炉のスラブ装入装置

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin", Imbedded Memory Test Methods", pp. 4911-4913, S.D. KELLEY, Vol. 21, No. 12, published May 1979. *
IBM Technical Disclosure Bulletin", Memory Initialization by Deferred Refresh", p. 1457, F.J. AICHELMANN et al. Vol. 18, No. 5, published October 1975. *

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0108114A4 (fr) * 1982-05-17 1984-06-29 Motorola Inc Bloc pour test de controle accelere d'une memoire.
EP0108114A1 (fr) * 1982-05-17 1984-05-16 Motorola Inc Bloc pour test de controle accelere d'une memoire.
EP0456255A2 (fr) * 1990-05-11 1991-11-13 Kabushiki Kaisha Toshiba Dispositif de mémoire dynamique et méthode pour l'examiner
EP0456255A3 (en) * 1990-05-11 1991-12-27 Kabushiki Kaisha Toshiba Dynamic memory device and method for screening the same
US5343430A (en) * 1990-05-11 1994-08-30 Kabushiki Kaisha Toshiba Method and circuitry for screening a dynamic memory device for defective circuits
US5357193A (en) * 1990-12-27 1994-10-18 Kabushiki Kaisha Toshiba Semiconductor memory having a voltage stress applying circuit
EP0492609A2 (fr) * 1990-12-27 1992-07-01 Kabushiki Kaisha Toshiba Dispositif à semi-conducteur comprenant des plages de test en tension élevée
EP0492609A3 (en) * 1990-12-27 1993-04-21 Kabushiki Kaisha Toshiba Semiconductor device with voltage stress testing pads
EP0516364A2 (fr) * 1991-05-28 1992-12-02 Texas Instruments Incorporated Dispositif de mémoire à semi-conducteur comportant un circuit de test vieillissement
EP0516364A3 (en) * 1991-05-28 1993-11-24 Texas Instruments Inc Semiconductor memory device having burn-in test circuit
FR2693288A1 (fr) * 1992-07-06 1994-01-07 Sgs Thomson Microelectronics Mémoire comprenant un circuit d'adressage interne pour les tests en vieillissement.
US5475646A (en) * 1992-08-31 1995-12-12 Kabushiki Kaisha Toshiba Screening circuitry for a dynamic random access memory
EP0615253A2 (fr) * 1993-03-10 1994-09-14 Kabushiki Kaisha Toshiba Mémoire à semi-conducteur comportant un test de vieillissement
US5424990A (en) * 1993-03-10 1995-06-13 Kabushiki Kaisha Toshiba Semiconductor memory having built-in voltage stress test mode
EP0615253A3 (fr) * 1993-03-10 1994-10-12 Toshiba Kk Mémoire à semi-conducteur comportant un test de vieillissement.
US6781397B2 (en) * 1996-12-03 2004-08-24 Micron Technology, Inc. Electrical communication system for circuitry
US7161372B2 (en) 1996-12-03 2007-01-09 Micron Technology, Inc. Input system for an operations circuit
US7187190B2 (en) 1996-12-03 2007-03-06 Micron Technology, Inc. Contact pad arrangement on a die
US7282939B2 (en) 1996-12-03 2007-10-16 Micron Technology, Inc. Circuit having a long device configured for testing
EP1136833A1 (fr) * 2000-03-23 2001-09-26 Infineon Technologies AG Procédé de vieillissement par stress électrique d'une mémoire semi-conducteur
US6445630B2 (en) 2000-03-23 2002-09-03 Infineon Technologies Ag Method for carrying out a burn-in process for electrically stressing a semiconductor memory

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