Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
  • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
  • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
  • G11C11/418—Address circuits

Definitions

• each of the memory cells is accessed by applying a high voltage level to the row line that drives an access transistor for the addressed memory cells.
• the row line is activated by a decoder circuit which is driven by a multi-bit memory address signal.
• the row line selected by the address is driven to a high level by the decoder circuit.
• memory circuits have become increasingly dense, there can be greater capacitive coupling between adjacent row lines.
• a row line is charged or discharged, a voltage will be capacitively coupled into the adjacent floating row lines and the voltage thus coupled can turn on the access transistors from the memory cells connected to the floating row lines.
• This inadvertent activation of memory cells can destroy the data states stored therein. The most serious coupling occurs between immediately adjacent row lines. Thus, when these memory cells are later accessed, erroneous data will be read out.
• a decoder circuit includes a row driver transistor for each of the row lines in the memory. Circuit means are provided for decoding an address signal for rendering conductive a selected row driver transistors and for rendering conductive the row driver transistor for the adjacent row line on either side of the row line corresponding to the selected row driver transistor. Circuit means are provided for generating a first row line signal for transmission through said selected row transistor to charge the selected row line. Further circuit means are provided for generating a second row line signal for transmission through the row driver transistors for said adjacent row lines to affirmatively hold said adjacent row lines to a low voltage state.
• FIGURE 1 is a schematic illustration of a decoder circuit for activating a selected row line in a semiconductor memory, and holding some unselected row lines, including the adjacent row lines, to ground.
• FIGURE 2 is a schematic illustration of a circuit generating the RD0 and RD1 signals utilized in the circuit of FIGURE 1,
• FIGURE 3 is a schematic illustration of a circuit for generating a CT0 signal utilized in the circuit of FIGURE 1, and
• FIGURE 4 is a schematic illustration of a circuit for generating the signal CT1 which is utilized in the circuit of FIGURE 1.
• the circuit 10 includes a decoder OR circuit 12 which comprises a plurality of input transistors 14-22. Each of the input transistors has a drain terminal thereof connected to a power terminal 24 which is in turn connected to the power source V cc . The source terminals on the input transistors 14-22 are connected to a node 26. Address bits A 1 -A 5 are provided respectively to the gate terminals of transistors 14-22.
• a precharge transistor 28 has the drain terminal thereof connected to node 26, the source terminal thereof connected to a common ground node 30 and the gate terminal thereof connected to receive a precharge signal P.
• the transistor 28 When the precharge signal is received the transistor 28 is made conductive thereby discharging node 26 to the ground node 30.
• the precharge signal When the precharge signal is terminated the transistor 28 is rendered nonconductive thereby leaving node 26 floating at ground potential.
• Node 26 is connected to the gate terminal of a transistor 32 which has the source terminal thereof connected to the common node 30.
• the drain terminal of transistor 32 is connected to a node 34.
• a precharge transistor 36 has the source terminal thereof connected to the node 34, the drain terminal thereof connected to the power terminal 24 and the gate terminal thereof connected to receive a precharge signal P.
• Node 34 is connected to the drain terminal of a pass transistor 38 which has the source terminal thereof connected to a node 40 and the gate terminal thereof connected to a line 42 to receive a signal CT0.
• Node 34 is further connected to the drain terminal of a transistor 44 which has the source terminal thereof connected to a node 46 and the gate terminal thereof connected to a line 48 to receive a signal CT1.
• Node 40 is connected to the gate terminal of a row driver transistor 54 which has the source terminal thereof connected to a row line 56 and the drain terminal thereof connected a line 58 which receives a row driver signal RD0.
• the row line 56 has a plurality of memory cells such as 60 connected thereto for transfering data states to or from a bit line 62.
• Node 46 is connected to the gate terminal of a row driver transistor 64 which has the source terminal thereof connected to a row line 66 and the drain terminal thereof connected to a line 68 which receives a row driver signal RD1.
• the row line 66 has a plurality of memory cells such as 67 connected thereto for transferring data states to or from bit line 62.
• the circuit 10 is provided for each pair of row lines within the memory.
• the row lines for a corresponding circuit above circuit 10 are labeled as 70 and 72.
• the row lines for a corresponding circuit below circuit 10 are labeled as 74 and 76.
• the row lines 56, 66, 70, 72, 74 and 76 are layed out in an array within a semiconductor memory. In dense memory circuits the row lines are spaced closely together such that when one row line is charged or discharged a voltage can be capacitively coupled into the immediately adjacent row lines.
• the signal RD0 is connected to alternate row lines across the array of row lines and the signal RDl is connected to the other alternate row lines in the array.
• the circuit for generating the row driver signals RD0 and RD1 is illustrated in FIGURE 2.
• the memory address bit A 0 is provided to the gate terminal of a transistor 82 which has the source terminal thereof connected to a node 84 and the drain terminal thereof connected to the power terminal 24.
• a precharge signal P is provided to the gate terminal of a transistor 86 which has the source terminal thereof connected to the common node 30 and the drain terminal thereof connected to node 84.
• a precharge signal P is provided to the gate terminal of a transistor 88 which has the source terminal thereof connected to a node 90 and the drain terminal thereof connected to the power terminal 24.
• Node 84 is connected to the gate terminal of a transistor 92 which has the source terminal thereof connected to the common node 30 and the drain terminal thereof connected to node 90.
• the node 90 is connected to the gate terminal of a transistor 94, which has the drain terminal thereof connected to receive a row driver clock signal RD.
• the row driver signal RD0 is generated at the source terminal of transistor 94 and transmitted through line 58.
• the complement of the A 0 address bit is provided to the input terminal of a transistor 96 which has the source terminal thereof connected to a node 98 and the drain terminal thereof connected to the power terminal 24.
• the precharge signal P is supplied to the gate terminal of a transistor 100 which has the source terminal thereof connected to the common node 30 and the drain terminal thereof connected to node 98.
• the precharge signal P is also supplied to the gate terminal of a transistor 101 which has the source terminal thereof connected to a node 102 and the drain terminal thereof connected to the power terminal 24.
• Node 98 is further connected to the gate terminal of a transistor 104 which has the source terminal thereof connected to the common ground node 30 and the drain terminal thereof connected to the node 102.
• the node 102 is connected to the gate terminal of a transistor 106 which has the source terminal thereof connected to line 68 and the drain terminal thereof connected to receive the row drive clock signal RD.
• the row driver signal RD1 is generated at the source terminal of transistor 106 and transmitted through line 68.
• the row driver signals RD0 and RD1 are cross-coupled through transistors 108 and 110.
• the gate terminal of transistor 108 is connected to line 68 and the gate terminal of transistor 110 is connected to line 58.
• the drain terminal of transistor 108 is connected to line 58 and the drain terminal of transistor 110 is connected to line 68.
• the source terminals for both transistors 108 and 110 are connected to the common ground node 30.
• the signal CT0 is generated by circuit illustrated in FIGURE 3.
• a precharge signal P is provided to the gate terminal of a transistor 112 which has the source terminal thereof connected to line 42 and the drain terminal thereof connected to the power terminal 24.
• the address bit A 0 is supplied to the gate terminal of a transistor 114 which has the source terminal thereof connected to the common ground node 30 and the drain terminal thereof connected to line 42.
• the signal CT0 is generated at line 42.
• the precharge signal P goes to a high state the transistor 112 is turned on thereby precharging line 42 and driving signal CT0 to a high state.
• address bit A 0 is at a high state the transistor 114 is turned on thereby discharging line 42 and pulling the signal CT0 to a low voltage state.
• the circuit for generating signal CT1 is illustrated in FIGURE 4.
• a precharge signal P is provided to the gate terminal of a transistor 116 which has the source terminal thereof connected to line 48 and the drain terminal thereof connected to the power terminal 24.
• the complement of the A 0 address bit is supplied to the gate terminal of a transistor 118 which has the source terminal thereof connected to the common ground node 30 and the drain terminal thereof connected to line 48.
• the signal CT1 is generated on line 48.
• the precharge signal P goes to a high state the transistor 116 is turned on thereby precharging line 48 which drives signal CT1 to a high voltage state.
• the complement of the A 0 address bit goes to a high voltage level the transistor 118 is turned on thereby discharging line 48 and pulling the signal CT1 to a low voltage level.
• transistor 82 If the address bit A 0 goes to a high level the transistor 82 is turned on thereby charging node 84 to a high potential. When node 84 is thus charged transistor 92 is rendered conductive to discharge node 90 and turn off transistor 94. When transistor 94 is turned off the row driver clock signal RD cannot be transmitted to line 58.
• transistor 82 If the A 0 address bit is received at a low level transistor 82 is maintained nonconductive and the charge state on nodes 84 and 90 are not changed. Transistor 94 is rendered conductive by the high voltage state on node 90 such that the row driver clock signal RD is transmitted to line 58 to produce the signal RD0.
• the RD1 is generated in this same manner as the signal RD0 by the circuit in the lower half of FIGURE 2. As noted above, the signals RD0 and RD1 are cross-coupled through transistors 108 and 110 such that when one of the signals is driven to a high level the other signal is pulled to ground potential.
• the precharge signal turns on transistor 28 to discharge node 26 and subsequently turns off transistor 28 so that node 26 floats at ground potential.
• the decoder circuit 12 receives various combinations of the address bits A 1 -A 5 . If any one of the address bits A 1 -A 5 goes to a high level the corresponding input transistor is turned on thereby charging node 26 to a high voltage state. If none of the address bits A 1 -A 5 goes to a high level, the node 26 is maintained at ground potential.
• the precharge signal P turns on transistor 36 to precharge node 34 to a high voltage state. This occurs before the start of each memory cycle.
• node 26 When the address bits A 1 -A 5 do not select the decoder circuit 12 the node 26 is pulled to a high voltage state which turns on transistor 32 thereby discharging node 34 to ground. Thus, node 34 is held at a high voltage state when the address bits A 1 -A 5 select decoder 12 but node 34 is discharged when the address bits do not select decoder 12.
• the node 34 When the node 34 is being precharged the signals CT0 and CT1 are also being precharged to a high level thereby turning on pass transistors 38 and 44. Thus when node 34 is charged, nodes 40 and 46 are likewise charged.
• Transistor 54 is rendered conductive when node 40 is at a high voltage state and transistor 64 is likewise rendered conductive when node 46 is at a high voltage state.
• transistors 54 and 64 When transistors 54 and 64 are turned on the corresponding row drive signals RD0 and RD1 are coupled through the row driver transistors to the respective row lines 56 and 66.
• the signal CT0 or CT1 is driven to a low voltage state before node 34 can be discharged.
• Transistor 114 or 118 is rendered conductive when the A 0 address bit, or its complement, reaches one threshold voltage level. But node 34 cannot be discharged until one of the A 1 -A 5 address bits has risen to at least two threshold voltages since one threshold voltage is required to turn on one of the input transistors and node 26 must be driven to at least one threshold voltage to turn on transistor 32. Thus either transistor 38 or 44 is turned off before node 34 can be discharged.
• the address bit A 0 determines whether signal RD0 or signal RD1 is driven to a high voltage state.
• This high voltage state serves to charge one of the row lines 56 or 66 to a high state thereby accessing the memory cells connected thereto.
• the other row driver signal is pulled to ground and this ground state is transmitted through the conductive row driver transistor to the corresponding row line thereby holding that row line to ground.
• any charge capacitively coupled to the row line is discharged to ground.
• a memory cycle sequence is accomplished as follows.
• the node 34 is initially charged to a high voltage state by transistor 36.
• signals CT0 and CT1 are at a high level thereby turning on transistors 38 and 44 which serves to precharge nodes 40 and 46 to a high level.
• This operation is carried out for all pairs of row lines within the memory.
• the decoder circuits (not shown) for the row lines 70 and 72 and the row lines 74 and 76.
• CT1 when A 0 is low CT0 remains high.
• CT1 when is high, CT1 is quickly discharged to ground.
• CT1 is discharged to ground when reaches one threshold voltage.
• the remaining addresses are either still at ground (FIGURE 1) or are at only one threshold voltage Thus node 26 is just starting to rise and transistor

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Read Only Memory (AREA)
• Static Random-Access Memory (AREA)

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Citations (3)

• 1980
  • 1980-06-02 JP JP56500642A patent/JPS57501004A/ja active Pending
  • 1980-06-02 WO PCT/US1980/000674 patent/WO1981003569A1/en not_active Application Discontinuation
  • 1980-06-02 EP EP19810900351 patent/EP0052605A1/en not_active Withdrawn

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