Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
  • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
  • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
  • H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
  • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
  • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
  • H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle

Definitions

• This invention relates generally to the electronic signal processing art and in particular to an improved frequency synthesizer using multiple dual modulus pre- scalers.
• Digital frequency synthesizers commonly employ standard phase locked loop circuitry wherein a controlled oscillator signal is divided by a loop divider.
• the output of the loop divider is fed back and compared in a phase comparator to a reference frequency signal.
• Phase comparator generates a control signal which is then cou ⁇ pled to the controlled oscillator, thereby providing an output signal from the control oscillator which has the desired frequency.
• the loop divider produces an output signal in response to every nth input pulse thereby dividing the input frequency by n.
• the reference frequency is determined by the desired VCO frequency increments. This is of particular importance in the radio communication art since channel spacing will therefore be related to the reference fre ⁇ quency. As smaller increments are needed, the reference frequency must be lowered. With a lower reference frequency, however, the short term stability decreases and the phase noise increases.
• the first counter is program ⁇ med to divide the output of the dual modulus prescaler by a number N .
• the second counter often referred to as “swallow counter” is programmed to divide the output of the dual modulus prescaler by a number N legal , which is less than N p .
• the output of the controlled oscillator is divided by the prescaler, with first modulus P + 1, and applied to both counters..
• the swallow counter actuates the dual modulus prescaler to a new modulus P.
• the output of the prescaler then continues to be divided by the first counter.
• the dual modulus prescaler approach permits a change in the divide ratio in incre- ments of one merely by reprogramming the value of A and thereby permits the reference frequency to be equal to the channel spacing.
• an improved frequency synthesizer which is capable of operating at very high frequencies a a result of using two dual modulus prescalers as part of the loop dividing function.
• a reference signal is applied to a first input of a phas comparator.
• This reference signal is then compared to a signal applied to second input of the phase comparator and a control signal representative of the phase differ ⁇ ence between the two signals is generated.
• This control signal is then applied to a signal controlled oscillator which produces an oscillator signal of frequency f in response to the control signal.
• the controlled oscil ⁇ lator signal of frequency f is then applied to a pro ⁇ grammable frequency divider for frequency dividing the controlled oscillator signal by a divisor N .
• the programmable divider includes a first prescaler for frequency dividing the controlled oscillator signal by one of two predetermined integer divisors, M and M 1 . Th output of the first prescaling means is then counted in counter circuit so that an output signal is generated when the counter has counted a given number of signal pulses C.
• the output of the first prescale is applied to a second prescaler for frequency dividing by one of two predetermined integer divisors P and P' .
• the frequency divided output of the second prescaler is then applied to a frequency divider so that the output signal of the divider is a signal of frequency f/N .
• a control circuit controls the first prescaler and the counter circuit such that the counter circuit is enabled when the first prescaler is dividing the input signal by its divisor Q 1 and such that the first prescaler is actu ated from its Q' divisor to its Q divisor in response to the output signal from the first counter circuit and such that the first prescaler is actuated from its Q divisor to its Q - divisor in response to the output signal from the frequency divider circuit.
• the invention as described elim ⁇ inates the need for one large high speed prescaler to enable the synthesizer to operate at very high frequen ⁇ cies. This is a result of the fact that only the first prescaler need be capable of operating at the very high frequencies.
• the overall result is an improved frequency synthesizer which can operate at very high frequencies without excessive manufacturing costs and excessive cur ⁇ rent drain while retaining the capability of being pro- grammable in frequency increments equal to the reference frequency. It is therefore highly suitable for high frequency mobile and portable radio applications.
• Fig. 1 is a block diagram illustrating the inventive frequency synthesizer utilizing multiple dual modulus prescalers.
• Fig. 2 is a schematic diagram illustrating in greater detail the multiple dual modulus prescaler circuit illustrated in Fig. 1. Description of the Preferred Embodiment of the Invention
• Fig. 1 is a block diagram of a frequency synthesize according to the invention.
• a phase locked loop is utilized including a reference oscillator 100 which produces a reference signal of a frequency f RF * ⁇ he signal of frequency f REF is fed to the first input 112 of a phase detector 110 (an example of which is a Motorola type MC4044) .
• the phase detector 11 has a second input 114 and an output 116. Acting in the conventional manner, the phase detector 110 produces an error signal at its output 116 which error signal is representative of the phase difference between the signals received at the input terminals 112 and 114.
• the output error signal at the output terminal 116 of the phase detector 110 is optionally low pass filtere through an optional low pass filter circuit 118 and applied to the control input 122 of a voltage controlled oscillator 120 (for example, a Motorola type MC1648).
• the voltage controlled oscillator 120 produces an oscil ⁇ lator signal of predetermined frequency at its output 12 responsive to a control signal (i.e., the phase detector error signal) received at the control input 122.
• the output terminal 124 of the voltage controlled oscillator 120 feeds to the input terminal 130 of a loop divider 200 (The loop divider 200 is shown in greater detail in Fig. 2).
• the loop divider 200 responds to the signal of frequency f at its input 130 to divide the signal received at the input 130 by an integer number N ⁇ .
• the output 230 of the loop divider 200 is coupled to the second phase detector input 114 thereby applying to the input 114 a signal of frequency f/N ⁇ .
• the loop divider 200 in order to have the capability of generating frequencies with increments of f ⁇ --.--, the loop divider 200 must have a divide ratio -p which is programmable in increments of one.
• Fig. 2 is a schematic diagram of the loop divider 200 shown in Fig. 1.
• a signal of frequency f from the control oscillator 120 (See Fig. 1) is applied to the input 130 of a dual modulus prescaler 132 with moduli M and M' where M 1 is equal to M + 1 in the prefer ⁇ red embodiment.
• the dual modulus prescaler 132 produces a frequency divided signal at its output 134.
• This output 134 is coupled both to the input 138 of a control logic circuit 140 and the input 168 of a second dual modulus prescaler 170.
• the signal at the output 134 ' of the dual modulus prescaler 132 will have a frequency, indicated as f' , equal to the frequency f divided by the divisor M or M + 1.
• This signal is then applied to the input 138 of the control logic 140 and is thereby coupled directly to the clock input 144 of a D flip-flop 142 and to the input 152 of an AND gate 150.
• the Q output 148 of the D flip-flop 142 is coupled directly to the enable input 136 of the dual modulus prescaler 132 and directly to the input 154 of the AND gate 150.
• a signal applied to a second input 139 of the control logic 140 is coupled to the input 145 of a NAND gate 143 and to the set input 156 of a counter 160 (preferably programmable) of modulus C.
• the programmable counter 160 is programmed via inputs C fi -C 7 and its clock signal is supplied at the clock input 158 from the output 151 of the AND gate 150.
• the zero output 162 of the counter 160 is coupled to the second input 147 of the NAND gate 143.
• the outpu of the NAND gate 143 is then coupled directly to the D input 146 of the D flip-flop 142.
• the divided signal f at the output 134 of the dual modulus prescaler 132 is also applied to the input 168 of the second dual modulus prescaler 170.
• the second dual ⁇ modulus prescaler 170 produces a divided signal at its Q output 172 and at its Q output 174.
• the Q output 172 is coupled to the input 176 of the counter control logic 180 and the " Q output 174 is coupled to the input 178 of the control logic 180.
• the control logic 180 is composed of AND gates and NAND gates.
• a counter 210, to divide by the number B and a counter- 220, to divide by the number A are also coupled to the control logic 180 as shown.
• the B counter 210 and the A counter 220 are preferably programmable down counters (programmable via the inputs B_-B and A Q -A ⁇ , respectively) . These counters are coupled to the control logic so as to fre ⁇ quency divide the signal of -f* to produce a divided output frequency f n ⁇ m at the output 230, as indicated. This output signal of frequency is coupled to the output 230 and to the input 139 of control logic 140.
• the divider circuit shown in Fig. 2 functions as follows.
• the signal of frequency f n ⁇ Tm applied to the input 139 is coupled to the set input of the C counter 160 and the input 145 of the NAND gate 143, When the signal of frequency f o ⁇ on the SET input 156 is low, the counter C is set to its programmed value. When the signal on the input 139 of the control logic 140 goes high, a high will be applied to the input 145 of NAND
• the high on the Q output 148 is applied to the input 154 of the AND gate 150.
• This enables the AND gate 150 so that the signal on the input 138 of control logic 140 is transmitted through the AND gate 150 to its output 151 and applied to the clock input 158 of the C counter 160.
• the C counter begins to count down to zero.
• the zero output 162 will go low thus applying a low to the input 147 of the NAND gate 143. This results in a high at the output of the NAND gate 143 which is then applied to the input 146 of the D flip-flop.
• the counter C When the signal of frequency f o ⁇ applied to the input 139 of control logic 140 goes low, the counter C will be reset to its programmed value. In addition, the low will be applied to the input 145 of the NAND gate 143 resulting in a high being applied to the input 146 of th D flip-flop. As a result, the D flip-flop will remain in a state with Q being low and the dual modulus pre- sealer will maintain its state of division by M while the C counter remains disabled. However, when the signal of frequency n ⁇ which is applied to the input 139 goes high, the C counter will again be enabled and the dual modulus prescaler 132 will again shift to the M + 1 divisor state. Thus, the signal f applied to the input 130 is divided alternately by the divisor M and M + 1 by the prescaler 132.
• the divided signal of frequency f 1 is then applied to the input 168 of the second dual modulus prescaler 170.
• the modulus will be determined by a signal applied to the enable input 175 of the pre ⁇ scaler 170.
• the divided signal on the Q output 172 is coupled to the input 176 of the control logic 180. With ⁇ in the control logic 180 the signal applied to the input 176 is coupled directly to the input 193 of an AND gate 194 and to the input 198 of an AND gate 196.
• a second input 195 of the AND gate 194 and a second input 197 of the AND gate 196 are controlled by a flip-flop composed of the NAND gates 188 and 192, as shown.
• the input 195 of the gate 194 and the gate 196 will be disabled since the low from the output 190 is applied to the input 197 of the AND gate 196.
• the signal from the Q output 172 applied to the input 193 of the AND gate 194 will be gated through to the CLK B input 214 of the B counter 210.
• the output 189 of the NAND gate 188 is coupled to the SET A input 222 of the A counter 220. Since the output 189 of the gate 188 was high, the SET A input 222 will also be high which will cause the A counter to reset.
• This low on the output 190 is also applied to the SET B input 216 of the B counter 210 which allows the B counter 210 to be decremented by the signal on the CLK B input 214.
• the input 195 of the AND gate 194 will be low thus disabling the AND gate 194, and the input 197 of the AND gate 196 will be high thus enabling the AND gate 196.
• the result of this is that the signal from the Q output 172 of the prescaler 170 is now gated through the AND gate 196 and applied to the C K A input 224 of the A counter 220. Simultaneously, the same signal from the prescaler output 172 is blocked by the disabled AND gate 194 so that no signal is applied to th CLK B input 214 of the B counter 210.
• the high on the output 190 of the NAND gate 192 is applied t the SET B input 216 of the B counter 210. This causes the B counter to be reset.
• the lov; on the output 189 of the NAND gate 188 is also applied to the SET A input 222 of the A counter 220, which allows the A counter 220 to be decremented by the signal on the CLK A input 224. This results in the B counter 210 being set while the A counter 220 is decrementing.
• a high signal is generated on its ZERO A output 226 which is applied to the input 181 of the NAND gate 182.
• This signal together with the signal from the ⁇ Q output'174 applied to the input 183 of NAND .gate 182 fro the control logic input 178, results in a signal applied to the input 187 of the NAND gate 188 causing the flip- flop composed of NAND gates 188 and 192 to change to the opposite state.
• the B counter 210 will begin to decrement and the A counter 220 will be reset in the same manner as described previ ⁇ ously.
• the signal which occurs on the SET B input 216 of the B counter 210 is also coupled via the feedback line 199 to the enable input 175 of the dual modulus prescaler 170. Whenever a transition occurs at the enable input 175, the modulus of the prescaler 170 will be changed. In the preferred embodiment of the divider, the prescale 170 will have a modulus of P during the B count and a modulus of P + 1 during the A count.
• the signal on the feedback line 199 is also coupled to the output 230. Thus, the signal on the output 190 of the NAND gate 192 is coupled to the output 230.
• the divide ratio can be incremented by one by the process of reprograrnming the value of B to be reduced by one and reprograrnming the value of A to be increased by one, resulting in the net increase in the divide ratio N of one.
• the value of C is made at least equal to M and the value of A is equal at least to P.
• the value of N ⁇ can be programmed in increments of one by appropriate changes in the values of A, B and C.
• the value of M is made to be small so that a small very high speed pre ⁇ scaler can be used thereby permitting the divider to operate at very high speeds while maintaining low cost and low current drain.
• an improved frequency synthesizer is provided which is capable of operating at very high speeds and is particularly suited for radio communication system applications.
• the frequency synthesizer not only has th capability of operating at very high frequencies, but also maintains minimum current drain and minimum manufacturing costs.

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• Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

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• 1980
  • 1980-02-13 US US06/121,333 patent/US4316151A/en not_active Expired - Lifetime
• 1981
  • 1981-01-05 BR BR8106699A patent/BR8106699A/pt unknown
  • 1981-01-05 JP JP56501129A patent/JPH0255976B2/ja not_active Expired
  • 1981-01-05 EP EP19810900769 patent/EP0045799A4/en not_active Withdrawn
  • 1981-01-05 WO PCT/US1981/000010 patent/WO1981002371A1/en not_active Application Discontinuation
  • 1981-01-12 CA CA000368265A patent/CA1150371A/en not_active Expired

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