Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G1/00—Details of arrangements for controlling amplification
  • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
  • H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid-state elements
  • H03G1/0023—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid-state elements in emitter-coupled or cascode amplifiers

Definitions

• the present invention relates to a gain control circuit suitable to be implemented in a monolitic technique and substantially intended to be used in Line and microphone amplifiers for telephone instruments.
• a gain control circuit according to the above patent publications is working according to the current sharing principle implying that the signal current is shared by one or more differential stages the shares being determined by a control current.
• the controlled signal voltage is taken out across one (or more) load impedances where the current share determined by the control voltage is transformed into an output voltage.
• the gain control circuits previously known are intended as volume controls in radio sets and audio amplifiers. Therefore, they must have a large control range whereas the total gain and a possible drift of the gain is of minor importance. It is also obvious that gain control circuits of this type cannot be used in telephone instruments with their great demands of the nominal attenuation as well as of the control range.
• the tolerated deviation from the specified attenuation value is of magnitude ⁇ 0.1 dB when the cont ro l range i s 6 dB.
• the object of the present invention is to achieve a gain control circuit which fulfils the above requirements which includes at least a first and a second transistor differential amplifier the inputs of which are connected in parallel to a signal source and the characteristics of the invention appear from the attached patent claims.
• a gain control circuit according to the invention thoroughly fulfils the demands for a defined amplification required in an amplifier for telephone purposes at the same time as low noise, low distortion and low power consumption are obtained.
• Fig 1 shows a gain control circuit according to the invention with an unbalanced output
• Fig 2 shows a similar circuit with a balanced output.
• the circuit shown in Fig 1 includes a first differential stage with the transistors T1 and T2, a second differential stage with the transistors T3 and T4 and a third differential stage with the transistors T5 and T6.
• a signal is applied across the input terminals 11 and 12.
• the input 11 is connected through the resistor R1 to the base of the transistor T1 and through the resistor R1 + R2 to the base of the transistor T4.
• the base electrodes of the transistors T2 and T3 are interconnected and connected to the input 12 and the output 14.
• the collectors in the transistors T1 and T4 are connected to a constant current source 11 and to an input of an amplifier F while the collectors of the transistors T2 and T3 are connected to a constant current source 12 and the second input of the amplifier F.
• the interconnected emitters of the transistors T1 and T2 are connected to the collector of the transistor T5 in the third differential amplifier.
• the collect of the transistor T6 in the same differential amplifier is connected the same way to the emitters of the transistors T3 and T4.
• the emitters of the transistors T5 and T6 are connected to a constant current source Is.
• the base electrodes of the transistors T5 and T6 are connected to a DC controL voltage Uc.
• the differential amplifiers T1, T2 and T3, T4 have different negative feed back factors.
• the circuit operates in the following way.
• the sharing of the constant current Is between the transistors T5 and To can be controlled through the DC voltage Uc. This implies that the emitters in the differential amplifiers T1, T2 and T3, T4 receive corresponding currents. It is well known that the amplification of a differential stage increases with the emitter current. If, for example, the greater part of the current Is is sent through the transistors T1, T2 while the transistors T3, T4 carry a very small current the differential amplifier T1, T2 will amplify the input signal with maximum amplification while the contribution from T3, T4 is negligible.
• the negative feed-back circuit including the amplifier F gives a loop amplification which.is proportional to
• Fig 2 shows a modified gain control circuit according to the invention with the negative feed back amplifier F1 where both the input and th e output are balanced. In this case collectors of the transistors T1 and T3 are connected together as well as the collectors of the transistor T2 and T4.
• the input 11 is connected to the base of the transistor T1 through the resistor R4 and to the base of the transistor T3 through the resistor R4 + R5.
• One output of the amplifier F1 is connected as well to the output 13, as to the base of the transistor T3 through the resistor R6.
• the input 12 is connected to the base of the transistor T2 through the resistor R7 and to the base of the transistor T4 through the resistor R7 + R8 while the second output of the amplifier F1 is connected as well to the output 14, as to the base of the transistor T4 through the resistor R8.
• the bases of the transistors T2 and T3 are not connected together in this case.
• the circuit according to Fig 2 essentially works in the same way as described in Fi g 1 , the on ly di fference bei ng that a lso the negative feed bac k circuit is balanced.

Landscapes

• Amplifiers (AREA)
• Control Of Amplification And Gain Control (AREA)
• Contacts (AREA)
• Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
• Picture Signal Circuits (AREA)

Priority Applications (1)

Applications Claiming Priority (2)

Publications (1)

Family

ID=20337505

Family Applications (1)

Country Status (8)

Cited By (1)

Families Citing this family (15)

Citations (2)

Family Cites Families (3)

• 1979
  • 1979-03-09 SE SE7902171A patent/SE416694B/sv not_active IP Right Cessation
• 1980
  • 1980-02-18 FI FI800475A patent/FI68334C/sv not_active IP Right Cessation
  • 1980-02-20 GB GB8106792A patent/GB2067038B/en not_active Expired
  • 1980-02-20 US US06/191,769 patent/US4396891A/en not_active Expired - Lifetime
  • 1980-02-20 WO PCT/SE1980/000047 patent/WO1980001975A1/en active Application Filing
  • 1980-02-20 DE DE803036764A patent/DE3036764A1/de active Granted
  • 1980-11-07 DK DK475780A patent/DK152470C/da not_active IP Right Cessation
  • 1980-11-07 NO NO803368A patent/NO149158C/no unknown

Patent Citations (2)

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